i915_reg.h 13 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  4. * All Rights Reserved.
  5. */
  6. #ifndef _I915_REG_H_
  7. #define _I915_REG_H_
  8. /* Hotplug control (945+ only) */
  9. #define PORT_HOTPLUG_EN 0x61110
  10. #define HDMIB_HOTPLUG_INT_EN (1 << 29)
  11. #define DPB_HOTPLUG_INT_EN (1 << 29)
  12. #define HDMIC_HOTPLUG_INT_EN (1 << 28)
  13. #define DPC_HOTPLUG_INT_EN (1 << 28)
  14. #define HDMID_HOTPLUG_INT_EN (1 << 27)
  15. #define DPD_HOTPLUG_INT_EN (1 << 27)
  16. #define SDVOB_HOTPLUG_INT_EN (1 << 26)
  17. #define SDVOC_HOTPLUG_INT_EN (1 << 25)
  18. #define TV_HOTPLUG_INT_EN (1 << 18)
  19. #define CRT_HOTPLUG_INT_EN (1 << 9)
  20. #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
  21. #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
  22. /* must use period 64 on GM45 according to docs */
  23. #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
  24. #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
  25. #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
  26. #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
  27. #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
  28. #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
  29. #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
  30. #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
  31. #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
  32. #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
  33. #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
  34. #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
  35. /* Backlight control */
  36. #define BLC_PWM_CTL2 0x61250 /* 965+ only */
  37. #define BLM_PWM_ENABLE (1 << 31)
  38. #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
  39. #define BLM_PIPE_SELECT (1 << 29)
  40. #define BLM_PIPE_SELECT_IVB (3 << 29)
  41. #define BLM_PIPE_A (0 << 29)
  42. #define BLM_PIPE_B (1 << 29)
  43. #define BLM_PIPE_C (2 << 29) /* ivb + */
  44. #define BLM_PIPE(pipe) ((pipe) << 29)
  45. #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
  46. #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
  47. #define BLM_PHASE_IN_ENABLE (1 << 25)
  48. #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
  49. #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
  50. #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
  51. #define BLM_PHASE_IN_COUNT_SHIFT (8)
  52. #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
  53. #define BLM_PHASE_IN_INCR_SHIFT (0)
  54. #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
  55. #define BLC_PWM_CTL 0x61254
  56. /*
  57. * This is the most significant 15 bits of the number of backlight cycles in a
  58. * complete cycle of the modulated backlight control.
  59. *
  60. * The actual value is this field multiplied by two.
  61. */
  62. #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
  63. #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
  64. #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
  65. /*
  66. * This is the number of cycles out of the backlight modulation cycle for which
  67. * the backlight is on.
  68. *
  69. * This field must be no greater than the number of cycles in the complete
  70. * backlight modulation cycle.
  71. */
  72. #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
  73. #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
  74. #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
  75. #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
  76. #define BLC_HIST_CTL 0x61260
  77. /*
  78. * New registers for PCH-split platforms. Safe where new bits show up, the
  79. * register layout machtes with gen4 BLC_PWM_CTL[12]
  80. */
  81. #define BLC_PWM_CPU_CTL2 0x48250
  82. #define BLC_PWM2_ENABLE (1<<31)
  83. #define BLC_PWM_CPU_CTL 0x48254
  84. #define BLM_HIST_CTL 0x48260
  85. #define ENH_HIST_ENABLE (1<<31)
  86. #define ENH_MODIF_TBL_ENABLE (1<<30)
  87. #define ENH_PIPE_A_SELECT (0<<29)
  88. #define ENH_PIPE_B_SELECT (1<<29)
  89. #define ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
  90. #define HIST_MODE_YUV (0<<24)
  91. #define HIST_MODE_HSV (1<<24)
  92. #define ENH_MODE_DIRECT (0<<13)
  93. #define ENH_MODE_ADDITIVE (1<<13)
  94. #define ENH_MODE_MULTIPLICATIVE (2<<13)
  95. #define BIN_REGISTER_SET (1<<11)
  96. #define ENH_NUM_BINS 32
  97. #define BLM_HIST_ENH 0x48264
  98. #define BLM_HIST_GUARD_BAND 0x48268
  99. #define BLM_HIST_INTR_ENABLE (1<<31)
  100. #define BLM_HIST_EVENT_STATUS (1<<30)
  101. #define BLM_HIST_INTR_DELAY_MASK (0xFF<<22)
  102. #define BLM_HIST_INTR_DELAY_SHIFT 22
  103. /*
  104. * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  105. * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
  106. */
  107. #define BLC_PWM_PCH_CTL1 0xc8250
  108. #define BLM_PCH_PWM_ENABLE (1 << 31)
  109. #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
  110. #define BLM_PCH_POLARITY (1 << 29)
  111. #define BLC_PWM_PCH_CTL2 0xc8254
  112. /* digital port hotplug */
  113. #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
  114. #define PORTD_HOTPLUG_ENABLE (1 << 20)
  115. #define PORTD_PULSE_DURATION_2ms (0)
  116. #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
  117. #define PORTD_PULSE_DURATION_6ms (2 << 18)
  118. #define PORTD_PULSE_DURATION_100ms (3 << 18)
  119. #define PORTD_PULSE_DURATION_MASK (3 << 18)
  120. #define PORTD_HOTPLUG_NO_DETECT (0)
  121. #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
  122. #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
  123. #define PORTC_HOTPLUG_ENABLE (1 << 12)
  124. #define PORTC_PULSE_DURATION_2ms (0)
  125. #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
  126. #define PORTC_PULSE_DURATION_6ms (2 << 10)
  127. #define PORTC_PULSE_DURATION_100ms (3 << 10)
  128. #define PORTC_PULSE_DURATION_MASK (3 << 10)
  129. #define PORTC_HOTPLUG_NO_DETECT (0)
  130. #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
  131. #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
  132. #define PORTB_HOTPLUG_ENABLE (1 << 4)
  133. #define PORTB_PULSE_DURATION_2ms (0)
  134. #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
  135. #define PORTB_PULSE_DURATION_6ms (2 << 2)
  136. #define PORTB_PULSE_DURATION_100ms (3 << 2)
  137. #define PORTB_PULSE_DURATION_MASK (3 << 2)
  138. #define PORTB_HOTPLUG_NO_DETECT (0)
  139. #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
  140. #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
  141. #define PCH_GPIOA 0xc5010
  142. #define PCH_GPIOB 0xc5014
  143. #define PCH_GPIOC 0xc5018
  144. #define PCH_GPIOD 0xc501c
  145. #define PCH_GPIOE 0xc5020
  146. #define PCH_GPIOF 0xc5024
  147. #define PCH_GMBUS0 0xc5100
  148. #define PCH_GMBUS1 0xc5104
  149. #define PCH_GMBUS2 0xc5108
  150. #define PCH_GMBUS3 0xc510c
  151. #define PCH_GMBUS4 0xc5110
  152. #define PCH_GMBUS5 0xc5120
  153. #define _PCH_DPLL_A 0xc6014
  154. #define _PCH_DPLL_B 0xc6018
  155. #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
  156. #define _PCH_FPA0 0xc6040
  157. #define FP_CB_TUNE (0x3<<22)
  158. #define _PCH_FPA1 0xc6044
  159. #define _PCH_FPB0 0xc6048
  160. #define _PCH_FPB1 0xc604c
  161. #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
  162. #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
  163. #define PCH_DPLL_TEST 0xc606c
  164. #define PCH_DREF_CONTROL 0xC6200
  165. #define DREF_CONTROL_MASK 0x7fc3
  166. #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
  167. #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
  168. #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
  169. #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
  170. #define DREF_SSC_SOURCE_DISABLE (0<<11)
  171. #define DREF_SSC_SOURCE_ENABLE (2<<11)
  172. #define DREF_SSC_SOURCE_MASK (3<<11)
  173. #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
  174. #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
  175. #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
  176. #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
  177. #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
  178. #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
  179. #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
  180. #define DREF_SSC4_DOWNSPREAD (0<<6)
  181. #define DREF_SSC4_CENTERSPREAD (1<<6)
  182. #define DREF_SSC1_DISABLE (0<<1)
  183. #define DREF_SSC1_ENABLE (1<<1)
  184. #define DREF_SSC4_DISABLE (0)
  185. #define DREF_SSC4_ENABLE (1)
  186. #define PCH_RAWCLK_FREQ 0xc6204
  187. #define FDL_TP1_TIMER_SHIFT 12
  188. #define FDL_TP1_TIMER_MASK (3<<12)
  189. #define FDL_TP2_TIMER_SHIFT 10
  190. #define FDL_TP2_TIMER_MASK (3<<10)
  191. #define RAWCLK_FREQ_MASK 0x3ff
  192. #define PCH_DPLL_TMR_CFG 0xc6208
  193. #define PCH_SSC4_PARMS 0xc6210
  194. #define PCH_SSC4_AUX_PARMS 0xc6214
  195. #define PCH_DPLL_SEL 0xc7000
  196. #define TRANSA_DPLL_ENABLE (1<<3)
  197. #define TRANSA_DPLLB_SEL (1<<0)
  198. #define TRANSA_DPLLA_SEL 0
  199. #define TRANSB_DPLL_ENABLE (1<<7)
  200. #define TRANSB_DPLLB_SEL (1<<4)
  201. #define TRANSB_DPLLA_SEL (0)
  202. #define TRANSC_DPLL_ENABLE (1<<11)
  203. #define TRANSC_DPLLB_SEL (1<<8)
  204. #define TRANSC_DPLLA_SEL (0)
  205. /* transcoder */
  206. #define _TRANS_HTOTAL_A 0xe0000
  207. #define TRANS_HTOTAL_SHIFT 16
  208. #define TRANS_HACTIVE_SHIFT 0
  209. #define _TRANS_HBLANK_A 0xe0004
  210. #define TRANS_HBLANK_END_SHIFT 16
  211. #define TRANS_HBLANK_START_SHIFT 0
  212. #define _TRANS_HSYNC_A 0xe0008
  213. #define TRANS_HSYNC_END_SHIFT 16
  214. #define TRANS_HSYNC_START_SHIFT 0
  215. #define _TRANS_VTOTAL_A 0xe000c
  216. #define TRANS_VTOTAL_SHIFT 16
  217. #define TRANS_VACTIVE_SHIFT 0
  218. #define _TRANS_VBLANK_A 0xe0010
  219. #define TRANS_VBLANK_END_SHIFT 16
  220. #define TRANS_VBLANK_START_SHIFT 0
  221. #define _TRANS_VSYNC_A 0xe0014
  222. #define TRANS_VSYNC_END_SHIFT 16
  223. #define TRANS_VSYNC_START_SHIFT 0
  224. #define _TRANS_VSYNCSHIFT_A 0xe0028
  225. #define _TRANSA_DATA_M1 0xe0030
  226. #define _TRANSA_DATA_N1 0xe0034
  227. #define _TRANSA_DATA_M2 0xe0038
  228. #define _TRANSA_DATA_N2 0xe003c
  229. #define _TRANSA_DP_LINK_M1 0xe0040
  230. #define _TRANSA_DP_LINK_N1 0xe0044
  231. #define _TRANSA_DP_LINK_M2 0xe0048
  232. #define _TRANSA_DP_LINK_N2 0xe004c
  233. /* Per-transcoder DIP controls */
  234. #define _VIDEO_DIP_CTL_A 0xe0200
  235. #define _VIDEO_DIP_DATA_A 0xe0208
  236. #define _VIDEO_DIP_GCP_A 0xe0210
  237. #define _VIDEO_DIP_CTL_B 0xe1200
  238. #define _VIDEO_DIP_DATA_B 0xe1208
  239. #define _VIDEO_DIP_GCP_B 0xe1210
  240. #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
  241. #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
  242. #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
  243. #define VLV_VIDEO_DIP_CTL_A 0x60200
  244. #define VLV_VIDEO_DIP_DATA_A 0x60208
  245. #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
  246. #define VLV_VIDEO_DIP_CTL_B 0x61170
  247. #define VLV_VIDEO_DIP_DATA_B 0x61174
  248. #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
  249. #define VLV_TVIDEO_DIP_CTL(pipe) \
  250. _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
  251. #define VLV_TVIDEO_DIP_DATA(pipe) \
  252. _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
  253. #define VLV_TVIDEO_DIP_GCP(pipe) \
  254. _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
  255. /* vlv has 2 sets of panel control regs. */
  256. #define PIPEA_PP_STATUS 0x61200
  257. #define PIPEA_PP_CONTROL 0x61204
  258. #define PIPEA_PP_ON_DELAYS 0x61208
  259. #define PIPEA_PP_OFF_DELAYS 0x6120c
  260. #define PIPEA_PP_DIVISOR 0x61210
  261. #define PIPEB_PP_STATUS 0x61300
  262. #define PIPEB_PP_CONTROL 0x61304
  263. #define PIPEB_PP_ON_DELAYS 0x61308
  264. #define PIPEB_PP_OFF_DELAYS 0x6130c
  265. #define PIPEB_PP_DIVISOR 0x61310
  266. #define PCH_PP_STATUS 0xc7200
  267. #define PCH_PP_CONTROL 0xc7204
  268. #define PANEL_UNLOCK_REGS (0xabcd << 16)
  269. #define PANEL_UNLOCK_MASK (0xffff << 16)
  270. #define EDP_FORCE_VDD (1 << 3)
  271. #define EDP_BLC_ENABLE (1 << 2)
  272. #define PANEL_POWER_RESET (1 << 1)
  273. #define PANEL_POWER_OFF (0 << 0)
  274. #define PANEL_POWER_ON (1 << 0)
  275. #define PCH_PP_ON_DELAYS 0xc7208
  276. #define PANEL_PORT_SELECT_MASK (3 << 30)
  277. #define PANEL_PORT_SELECT_LVDS (0 << 30)
  278. #define PANEL_PORT_SELECT_DPA (1 << 30)
  279. #define EDP_PANEL (1 << 30)
  280. #define PANEL_PORT_SELECT_DPC (2 << 30)
  281. #define PANEL_PORT_SELECT_DPD (3 << 30)
  282. #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
  283. #define PANEL_POWER_UP_DELAY_SHIFT 16
  284. #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
  285. #define PANEL_LIGHT_ON_DELAY_SHIFT 0
  286. #define PCH_PP_OFF_DELAYS 0xc720c
  287. #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
  288. #define PANEL_POWER_PORT_LVDS (0 << 30)
  289. #define PANEL_POWER_PORT_DP_A (1 << 30)
  290. #define PANEL_POWER_PORT_DP_C (2 << 30)
  291. #define PANEL_POWER_PORT_DP_D (3 << 30)
  292. #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
  293. #define PANEL_POWER_DOWN_DELAY_SHIFT 16
  294. #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
  295. #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
  296. #define PCH_PP_DIVISOR 0xc7210
  297. #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
  298. #define PP_REFERENCE_DIVIDER_SHIFT 8
  299. #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
  300. #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
  301. #define PCH_DP_B 0xe4100
  302. #define PCH_DPB_AUX_CH_CTL 0xe4110
  303. #define PCH_DPB_AUX_CH_DATA1 0xe4114
  304. #define PCH_DPB_AUX_CH_DATA2 0xe4118
  305. #define PCH_DPB_AUX_CH_DATA3 0xe411c
  306. #define PCH_DPB_AUX_CH_DATA4 0xe4120
  307. #define PCH_DPB_AUX_CH_DATA5 0xe4124
  308. #define PCH_DP_C 0xe4200
  309. #define PCH_DPC_AUX_CH_CTL 0xe4210
  310. #define PCH_DPC_AUX_CH_DATA1 0xe4214
  311. #define PCH_DPC_AUX_CH_DATA2 0xe4218
  312. #define PCH_DPC_AUX_CH_DATA3 0xe421c
  313. #define PCH_DPC_AUX_CH_DATA4 0xe4220
  314. #define PCH_DPC_AUX_CH_DATA5 0xe4224
  315. #define PCH_DP_D 0xe4300
  316. #define PCH_DPD_AUX_CH_CTL 0xe4310
  317. #define PCH_DPD_AUX_CH_DATA1 0xe4314
  318. #define PCH_DPD_AUX_CH_DATA2 0xe4318
  319. #define PCH_DPD_AUX_CH_DATA3 0xe431c
  320. #define PCH_DPD_AUX_CH_DATA4 0xe4320
  321. #define PCH_DPD_AUX_CH_DATA5 0xe4324
  322. #endif /* _I915_REG_H_ */