broadwell_igd.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot src/soc/intel/broadwell/igd.c
  4. *
  5. * Copyright (C) 2016 Google, Inc
  6. */
  7. #include <common.h>
  8. #include <bios_emul.h>
  9. #include <bootstage.h>
  10. #include <dm.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <vbe.h>
  14. #include <video.h>
  15. #include <asm/cpu.h>
  16. #include <asm/global_data.h>
  17. #include <asm/intel_regs.h>
  18. #include <asm/io.h>
  19. #include <asm/mtrr.h>
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/iomap.h>
  22. #include <asm/arch/pch.h>
  23. #include <linux/delay.h>
  24. #include "i915_reg.h"
  25. struct broadwell_igd_priv {
  26. u8 *regs;
  27. };
  28. struct broadwell_igd_plat {
  29. u32 dp_hotplug[3];
  30. int port_select;
  31. int power_up_delay;
  32. int power_backlight_on_delay;
  33. int power_down_delay;
  34. int power_backlight_off_delay;
  35. int power_cycle_delay;
  36. int cpu_backlight;
  37. int pch_backlight;
  38. int cdclk;
  39. int pre_graphics_delay;
  40. };
  41. #define GT_RETRY 1000
  42. #define GT_CDCLK_337 0
  43. #define GT_CDCLK_450 1
  44. #define GT_CDCLK_540 2
  45. #define GT_CDCLK_675 3
  46. u32 board_map_oprom_vendev(u32 vendev)
  47. {
  48. return SA_IGD_OPROM_VENDEV;
  49. }
  50. static int poll32(u8 *addr, uint mask, uint value)
  51. {
  52. ulong start;
  53. start = get_timer(0);
  54. debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  55. while ((readl(addr) & mask) != value) {
  56. if (get_timer(start) > GT_RETRY) {
  57. debug("poll32: timeout: %x\n", readl(addr));
  58. return -ETIMEDOUT;
  59. }
  60. }
  61. return 0;
  62. }
  63. static int haswell_early_init(struct udevice *dev)
  64. {
  65. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  66. u8 *regs = priv->regs;
  67. int ret;
  68. /* Enable Force Wake */
  69. writel(0x00000020, regs + 0xa180);
  70. writel(0x00010001, regs + 0xa188);
  71. ret = poll32(regs + 0x130044, 1, 1);
  72. if (ret)
  73. goto err;
  74. /* Enable Counters */
  75. setbits_le32(regs + 0xa248, 0x00000016);
  76. /* GFXPAUSE settings */
  77. writel(0x00070020, regs + 0xa000);
  78. /* ECO Settings */
  79. clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  80. /* Enable DOP Clock Gating */
  81. writel(0x000003fd, regs + 0x9424);
  82. /* Enable Unit Level Clock Gating */
  83. writel(0x00000080, regs + 0x9400);
  84. writel(0x40401000, regs + 0x9404);
  85. writel(0x00000000, regs + 0x9408);
  86. writel(0x02000001, regs + 0x940c);
  87. /*
  88. * RC6 Settings
  89. */
  90. /* Wake Rate Limits */
  91. setbits_le32(regs + 0xa090, 0x00000000);
  92. setbits_le32(regs + 0xa098, 0x03e80000);
  93. setbits_le32(regs + 0xa09c, 0x00280000);
  94. setbits_le32(regs + 0xa0a8, 0x0001e848);
  95. setbits_le32(regs + 0xa0ac, 0x00000019);
  96. /* Render/Video/Blitter Idle Max Count */
  97. writel(0x0000000a, regs + 0x02054);
  98. writel(0x0000000a, regs + 0x12054);
  99. writel(0x0000000a, regs + 0x22054);
  100. writel(0x0000000a, regs + 0x1a054);
  101. /* RC Sleep / RCx Thresholds */
  102. setbits_le32(regs + 0xa0b0, 0x00000000);
  103. setbits_le32(regs + 0xa0b4, 0x000003e8);
  104. setbits_le32(regs + 0xa0b8, 0x0000c350);
  105. /* RP Settings */
  106. setbits_le32(regs + 0xa010, 0x000f4240);
  107. setbits_le32(regs + 0xa014, 0x12060000);
  108. setbits_le32(regs + 0xa02c, 0x0000e808);
  109. setbits_le32(regs + 0xa030, 0x0003bd08);
  110. setbits_le32(regs + 0xa068, 0x000101d0);
  111. setbits_le32(regs + 0xa06c, 0x00055730);
  112. setbits_le32(regs + 0xa070, 0x0000000a);
  113. /* RP Control */
  114. writel(0x00000b92, regs + 0xa024);
  115. /* HW RC6 Control */
  116. writel(0x88040000, regs + 0xa090);
  117. /* Video Frequency Request */
  118. writel(0x08000000, regs + 0xa00c);
  119. /* Set RC6 VIDs */
  120. ret = poll32(regs + 0x138124, (1 << 31), 0);
  121. if (ret)
  122. goto err;
  123. writel(0, regs + 0x138128);
  124. writel(0x80000004, regs + 0x138124);
  125. ret = poll32(regs + 0x138124, (1 << 31), 0);
  126. if (ret)
  127. goto err;
  128. /* Enable PM Interrupts */
  129. writel(0x03000076, regs + 0x4402c);
  130. /* Enable RC6 in idle */
  131. writel(0x00040000, regs + 0xa094);
  132. return 0;
  133. err:
  134. debug("%s: ret=%d\n", __func__, ret);
  135. return ret;
  136. };
  137. static int haswell_late_init(struct udevice *dev)
  138. {
  139. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  140. u8 *regs = priv->regs;
  141. int ret;
  142. /* Lock settings */
  143. setbits_le32(regs + 0x0a248, (1 << 31));
  144. setbits_le32(regs + 0x0a004, (1 << 4));
  145. setbits_le32(regs + 0x0a080, (1 << 2));
  146. setbits_le32(regs + 0x0a180, (1 << 31));
  147. /* Disable Force Wake */
  148. writel(0x00010000, regs + 0xa188);
  149. ret = poll32(regs + 0x130044, 1, 0);
  150. if (ret)
  151. goto err;
  152. writel(0x00000001, regs + 0xa188);
  153. /* Enable power well for DP and Audio */
  154. setbits_le32(regs + 0x45400, (1 << 31));
  155. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  156. if (ret)
  157. goto err;
  158. return 0;
  159. err:
  160. debug("%s: ret=%d\n", __func__, ret);
  161. return ret;
  162. };
  163. static int broadwell_early_init(struct udevice *dev)
  164. {
  165. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  166. u8 *regs = priv->regs;
  167. int ret;
  168. /* Enable Force Wake */
  169. writel(0x00010001, regs + 0xa188);
  170. ret = poll32(regs + 0x130044, 1, 1);
  171. if (ret)
  172. goto err;
  173. /* Enable push bus metric control and shift */
  174. writel(0x00000004, regs + 0xa248);
  175. writel(0x000000ff, regs + 0xa250);
  176. writel(0x00000010, regs + 0xa25c);
  177. /* GFXPAUSE settings (set based on stepping) */
  178. /* ECO Settings */
  179. writel(0x45200000, regs + 0xa180);
  180. /* Enable DOP Clock Gating */
  181. writel(0x000000fd, regs + 0x9424);
  182. /* Enable Unit Level Clock Gating */
  183. writel(0x00000000, regs + 0x9400);
  184. writel(0x40401000, regs + 0x9404);
  185. writel(0x00000000, regs + 0x9408);
  186. writel(0x02000001, regs + 0x940c);
  187. writel(0x0000000a, regs + 0x1a054);
  188. /* Video Frequency Request */
  189. writel(0x08000000, regs + 0xa00c);
  190. writel(0x00000009, regs + 0x138158);
  191. writel(0x0000000d, regs + 0x13815c);
  192. /*
  193. * RC6 Settings
  194. */
  195. /* Wake Rate Limits */
  196. clrsetbits_le32(regs + 0x0a090, ~0, 0);
  197. setbits_le32(regs + 0x0a098, 0x03e80000);
  198. setbits_le32(regs + 0x0a09c, 0x00280000);
  199. setbits_le32(regs + 0x0a0a8, 0x0001e848);
  200. setbits_le32(regs + 0x0a0ac, 0x00000019);
  201. /* Render/Video/Blitter Idle Max Count */
  202. writel(0x0000000a, regs + 0x02054);
  203. writel(0x0000000a, regs + 0x12054);
  204. writel(0x0000000a, regs + 0x22054);
  205. /* RC Sleep / RCx Thresholds */
  206. setbits_le32(regs + 0x0a0b0, 0x00000000);
  207. setbits_le32(regs + 0x0a0b8, 0x00000271);
  208. /* RP Settings */
  209. setbits_le32(regs + 0x0a010, 0x000f4240);
  210. setbits_le32(regs + 0x0a014, 0x12060000);
  211. setbits_le32(regs + 0x0a02c, 0x0000e808);
  212. setbits_le32(regs + 0x0a030, 0x0003bd08);
  213. setbits_le32(regs + 0x0a068, 0x000101d0);
  214. setbits_le32(regs + 0x0a06c, 0x00055730);
  215. setbits_le32(regs + 0x0a070, 0x0000000a);
  216. setbits_le32(regs + 0x0a168, 0x00000006);
  217. /* RP Control */
  218. writel(0x00000b92, regs + 0xa024);
  219. /* HW RC6 Control */
  220. writel(0x90040000, regs + 0xa090);
  221. /* Set RC6 VIDs */
  222. ret = poll32(regs + 0x138124, (1 << 31), 0);
  223. if (ret)
  224. goto err;
  225. writel(0, regs + 0x138128);
  226. writel(0x80000004, regs + 0x138124);
  227. ret = poll32(regs + 0x138124, (1 << 31), 0);
  228. if (ret)
  229. goto err;
  230. /* Enable PM Interrupts */
  231. writel(0x03000076, regs + 0x4402c);
  232. /* Enable RC6 in idle */
  233. writel(0x00040000, regs + 0xa094);
  234. return 0;
  235. err:
  236. debug("%s: ret=%d\n", __func__, ret);
  237. return ret;
  238. }
  239. static int broadwell_late_init(struct udevice *dev)
  240. {
  241. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  242. u8 *regs = priv->regs;
  243. int ret;
  244. /* Lock settings */
  245. setbits_le32(regs + 0x0a248, 1 << 31);
  246. setbits_le32(regs + 0x0a000, 1 << 18);
  247. setbits_le32(regs + 0x0a180, 1 << 31);
  248. /* Disable Force Wake */
  249. writel(0x00010000, regs + 0xa188);
  250. ret = poll32(regs + 0x130044, 1, 0);
  251. if (ret)
  252. goto err;
  253. /* Enable power well for DP and Audio */
  254. setbits_le32(regs + 0x45400, 1 << 31);
  255. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  256. if (ret)
  257. goto err;
  258. return 0;
  259. err:
  260. debug("%s: ret=%d\n", __func__, ret);
  261. return ret;
  262. };
  263. static unsigned long gtt_read(struct broadwell_igd_priv *priv,
  264. unsigned long reg)
  265. {
  266. return readl(priv->regs + reg);
  267. }
  268. static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
  269. unsigned long data)
  270. {
  271. writel(data, priv->regs + reg);
  272. }
  273. static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
  274. u32 bic, u32 or)
  275. {
  276. clrsetbits_le32(priv->regs + reg, bic, or);
  277. }
  278. static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
  279. u32 value)
  280. {
  281. unsigned try = GT_RETRY;
  282. u32 data;
  283. while (try--) {
  284. data = gtt_read(priv, reg);
  285. if ((data & mask) == value)
  286. return 0;
  287. udelay(10);
  288. }
  289. debug("GT init timeout\n");
  290. return -ETIMEDOUT;
  291. }
  292. static void igd_setup_panel(struct udevice *dev)
  293. {
  294. struct broadwell_igd_plat *plat = dev_get_plat(dev);
  295. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  296. u32 reg32;
  297. /* Setup Digital Port Hotplug */
  298. reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
  299. reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
  300. reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
  301. gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
  302. /* Setup Panel Power On Delays */
  303. reg32 = (plat->port_select & 0x3) << 30;
  304. reg32 |= (plat->power_up_delay & 0x1fff) << 16;
  305. reg32 |= (plat->power_backlight_on_delay & 0x1fff);
  306. gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
  307. /* Setup Panel Power Off Delays */
  308. reg32 = (plat->power_down_delay & 0x1fff) << 16;
  309. reg32 |= (plat->power_backlight_off_delay & 0x1fff);
  310. gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
  311. /* Setup Panel Power Cycle Delay */
  312. if (plat->power_cycle_delay) {
  313. reg32 = gtt_read(priv, PCH_PP_DIVISOR);
  314. reg32 &= ~0xff;
  315. reg32 |= plat->power_cycle_delay & 0xff;
  316. gtt_write(priv, PCH_PP_DIVISOR, reg32);
  317. }
  318. /* Enable Backlight if needed */
  319. if (plat->cpu_backlight) {
  320. gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
  321. gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
  322. }
  323. if (plat->pch_backlight) {
  324. gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
  325. gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
  326. }
  327. }
  328. static int igd_cdclk_init_haswell(struct udevice *dev)
  329. {
  330. struct broadwell_igd_plat *plat = dev_get_plat(dev);
  331. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  332. int cdclk = plat->cdclk;
  333. u16 devid;
  334. int gpu_is_ulx = 0;
  335. u32 dpdiv, lpcll;
  336. int ret;
  337. dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
  338. /* Check for ULX GT1 or GT2 */
  339. if (devid == 0x0a0e || devid == 0x0a1e)
  340. gpu_is_ulx = 1;
  341. /* 675MHz is not supported on haswell */
  342. if (cdclk == GT_CDCLK_675)
  343. cdclk = GT_CDCLK_337;
  344. /* If CD clock is fixed or ULT then set to 450MHz */
  345. if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
  346. cdclk = GT_CDCLK_450;
  347. /* 540MHz is not supported on ULX */
  348. if (gpu_is_ulx && cdclk == GT_CDCLK_540)
  349. cdclk = GT_CDCLK_337;
  350. /* 337.5MHz is not supported on non-ULT/ULX */
  351. if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
  352. cdclk = GT_CDCLK_450;
  353. /* Set variables based on CD Clock setting */
  354. switch (cdclk) {
  355. case GT_CDCLK_337:
  356. dpdiv = 169;
  357. lpcll = (1 << 26);
  358. break;
  359. case GT_CDCLK_450:
  360. dpdiv = 225;
  361. lpcll = 0;
  362. break;
  363. case GT_CDCLK_540:
  364. dpdiv = 270;
  365. lpcll = (1 << 26);
  366. break;
  367. default:
  368. ret = -EDOM;
  369. goto err;
  370. }
  371. /* Set LPCLL_CTL CD Clock Frequency Select */
  372. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  373. /* ULX: Inform power controller of selected frequency */
  374. if (gpu_is_ulx) {
  375. if (cdclk == GT_CDCLK_450)
  376. gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
  377. else
  378. gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
  379. gtt_write(priv, 0x13812c, 0x00000000);
  380. gtt_write(priv, 0x138124, 0x80000017);
  381. }
  382. /* Set CPU DP AUX 2X bit clock dividers */
  383. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  384. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  385. return 0;
  386. err:
  387. debug("%s: ret=%d\n", __func__, ret);
  388. return ret;
  389. }
  390. static int igd_cdclk_init_broadwell(struct udevice *dev)
  391. {
  392. struct broadwell_igd_plat *plat = dev_get_plat(dev);
  393. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  394. int cdclk = plat->cdclk;
  395. u32 dpdiv, lpcll, pwctl, cdset;
  396. int ret;
  397. /* Inform power controller of upcoming frequency change */
  398. gtt_write(priv, 0x138128, 0);
  399. gtt_write(priv, 0x13812c, 0);
  400. gtt_write(priv, 0x138124, 0x80000018);
  401. /* Poll GT driver mailbox for run/busy clear */
  402. if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
  403. cdclk = GT_CDCLK_450;
  404. if (gtt_read(priv, 0x42014) & 0x1000000) {
  405. /* If CD clock is fixed then set to 450MHz */
  406. cdclk = GT_CDCLK_450;
  407. } else {
  408. /* Program CD clock to highest supported freq */
  409. if (cpu_is_ult())
  410. cdclk = GT_CDCLK_540;
  411. else
  412. cdclk = GT_CDCLK_675;
  413. }
  414. /* CD clock frequency 675MHz not supported on ULT */
  415. if (cpu_is_ult() && cdclk == GT_CDCLK_675)
  416. cdclk = GT_CDCLK_540;
  417. /* Set variables based on CD Clock setting */
  418. switch (cdclk) {
  419. case GT_CDCLK_337:
  420. cdset = 337;
  421. lpcll = (1 << 27);
  422. pwctl = 2;
  423. dpdiv = 169;
  424. break;
  425. case GT_CDCLK_450:
  426. cdset = 449;
  427. lpcll = 0;
  428. pwctl = 0;
  429. dpdiv = 225;
  430. break;
  431. case GT_CDCLK_540:
  432. cdset = 539;
  433. lpcll = (1 << 26);
  434. pwctl = 1;
  435. dpdiv = 270;
  436. break;
  437. case GT_CDCLK_675:
  438. cdset = 674;
  439. lpcll = (1 << 26) | (1 << 27);
  440. pwctl = 3;
  441. dpdiv = 338;
  442. break;
  443. default:
  444. ret = -EDOM;
  445. goto err;
  446. }
  447. debug("%s: frequency = %d\n", __func__, cdclk);
  448. /* Set LPCLL_CTL CD Clock Frequency Select */
  449. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  450. /* Inform power controller of selected frequency */
  451. gtt_write(priv, 0x138128, pwctl);
  452. gtt_write(priv, 0x13812c, 0);
  453. gtt_write(priv, 0x138124, 0x80000017);
  454. /* Program CD Clock Frequency */
  455. gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
  456. /* Set CPU DP AUX 2X bit clock dividers */
  457. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  458. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  459. return 0;
  460. err:
  461. debug("%s: ret=%d\n", __func__, ret);
  462. return ret;
  463. }
  464. u8 systemagent_revision(struct udevice *bus)
  465. {
  466. ulong val;
  467. pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
  468. PCI_SIZE_32);
  469. return val;
  470. }
  471. static int igd_pre_init(struct udevice *dev, bool is_broadwell)
  472. {
  473. struct broadwell_igd_plat *plat = dev_get_plat(dev);
  474. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  475. u32 rp1_gfx_freq;
  476. int ret;
  477. mdelay(plat->pre_graphics_delay);
  478. /* Early init steps */
  479. if (is_broadwell) {
  480. ret = broadwell_early_init(dev);
  481. if (ret)
  482. goto err;
  483. /* Set GFXPAUSE based on stepping */
  484. if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
  485. systemagent_revision(pci_get_controller(dev)) <= 9) {
  486. gtt_write(priv, 0xa000, 0x300ff);
  487. } else {
  488. gtt_write(priv, 0xa000, 0x30020);
  489. }
  490. } else {
  491. ret = haswell_early_init(dev);
  492. if (ret)
  493. goto err;
  494. }
  495. /* Set RP1 graphics frequency */
  496. rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
  497. gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
  498. /* Post VBIOS panel setup */
  499. igd_setup_panel(dev);
  500. return 0;
  501. err:
  502. debug("%s: ret=%d\n", __func__, ret);
  503. return ret;
  504. }
  505. static int igd_post_init(struct udevice *dev, bool is_broadwell)
  506. {
  507. int ret;
  508. /* Late init steps */
  509. if (is_broadwell) {
  510. ret = igd_cdclk_init_broadwell(dev);
  511. if (ret)
  512. return ret;
  513. ret = broadwell_late_init(dev);
  514. if (ret)
  515. return ret;
  516. } else {
  517. igd_cdclk_init_haswell(dev);
  518. ret = haswell_late_init(dev);
  519. if (ret)
  520. return ret;
  521. }
  522. return 0;
  523. }
  524. static int broadwell_igd_int15_handler(void)
  525. {
  526. int res = 0;
  527. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  528. switch (M.x86.R_AX) {
  529. case 0x5f35:
  530. /*
  531. * Boot Display Device Hook:
  532. * bit 0 = CRT
  533. * bit 1 = TV (eDP)
  534. * bit 2 = EFP
  535. * bit 3 = LFP
  536. * bit 4 = CRT2
  537. * bit 5 = TV2 (eDP)
  538. * bit 6 = EFP2
  539. * bit 7 = LFP2
  540. */
  541. M.x86.R_AX = 0x005f;
  542. M.x86.R_CX = 0x0000; /* Use video bios default */
  543. res = 1;
  544. break;
  545. default:
  546. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  547. break;
  548. }
  549. return res;
  550. }
  551. static int broadwell_igd_probe(struct udevice *dev)
  552. {
  553. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  554. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  555. bool is_broadwell;
  556. ulong fbbase;
  557. int ret;
  558. if (!ll_boot_init()) {
  559. /*
  560. * If we are running from EFI or coreboot, this driver can't
  561. * work.
  562. */
  563. printf("Not available (previous bootloader prevents it)\n");
  564. return -EPERM;
  565. }
  566. is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
  567. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
  568. debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
  569. ret = igd_pre_init(dev, is_broadwell);
  570. if (!ret) {
  571. ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
  572. if (ret)
  573. debug("failed to run video BIOS: %d\n", ret);
  574. }
  575. if (!ret)
  576. ret = igd_post_init(dev, is_broadwell);
  577. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  578. if (ret)
  579. return ret;
  580. /* Use write-combining for the graphics memory, 256MB */
  581. fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
  582. ret = mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
  583. if (!ret)
  584. ret = mtrr_commit(true);
  585. if (ret && ret != -ENOSYS) {
  586. printf("Failed to add MTRR: Display will be slow (err %d)\n",
  587. ret);
  588. }
  589. debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
  590. plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
  591. return 0;
  592. }
  593. static int broadwell_igd_of_to_plat(struct udevice *dev)
  594. {
  595. struct broadwell_igd_plat *plat = dev_get_plat(dev);
  596. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  597. int node = dev_of_offset(dev);
  598. const void *blob = gd->fdt_blob;
  599. if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
  600. plat->dp_hotplug,
  601. ARRAY_SIZE(plat->dp_hotplug)))
  602. return -EINVAL;
  603. plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
  604. plat->power_cycle_delay = fdtdec_get_int(blob, node,
  605. "intel,power-cycle-delay", 0);
  606. plat->power_up_delay = fdtdec_get_int(blob, node,
  607. "intel,power-up-delay", 0);
  608. plat->power_down_delay = fdtdec_get_int(blob, node,
  609. "intel,power-down-delay", 0);
  610. plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
  611. "intel,power-backlight-on-delay", 0);
  612. plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
  613. "intel,power-backlight-off-delay", 0);
  614. plat->cpu_backlight = fdtdec_get_int(blob, node,
  615. "intel,cpu-backlight", 0);
  616. plat->pch_backlight = fdtdec_get_int(blob, node,
  617. "intel,pch-backlight", 0);
  618. plat->pre_graphics_delay = fdtdec_get_int(blob, node,
  619. "intel,pre-graphics-delay", 0);
  620. priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
  621. debug("%s: regs at %p\n", __func__, priv->regs);
  622. debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
  623. plat->dp_hotplug[2]);
  624. debug("port_select = %d\n", plat->port_select);
  625. debug("power_up_delay = %d\n", plat->power_up_delay);
  626. debug("power_backlight_on_delay = %d\n",
  627. plat->power_backlight_on_delay);
  628. debug("power_down_delay = %d\n", plat->power_down_delay);
  629. debug("power_backlight_off_delay = %d\n",
  630. plat->power_backlight_off_delay);
  631. debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
  632. debug("cpu_backlight = %x\n", plat->cpu_backlight);
  633. debug("pch_backlight = %x\n", plat->pch_backlight);
  634. debug("cdclk = %d\n", plat->cdclk);
  635. debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
  636. return 0;
  637. }
  638. static int broadwell_igd_bind(struct udevice *dev)
  639. {
  640. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  641. /* Set the maximum supported resolution */
  642. uc_plat->size = 2560 * 1600 * 4;
  643. log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  644. return 0;
  645. }
  646. static const struct video_ops broadwell_igd_ops = {
  647. };
  648. static const struct udevice_id broadwell_igd_ids[] = {
  649. { .compatible = "intel,broadwell-igd" },
  650. { }
  651. };
  652. U_BOOT_DRIVER(broadwell_igd) = {
  653. .name = "broadwell_igd",
  654. .id = UCLASS_VIDEO,
  655. .of_match = broadwell_igd_ids,
  656. .ops = &broadwell_igd_ops,
  657. .of_to_plat = broadwell_igd_of_to_plat,
  658. .bind = broadwell_igd_bind,
  659. .probe = broadwell_igd_probe,
  660. .priv_auto = sizeof(struct broadwell_igd_priv),
  661. .plat_auto = sizeof(struct broadwell_igd_plat),
  662. };