atmel_lcdfb.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 LCD Controller
  4. *
  5. * Copyright (C) 2007 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <atmel_lcd.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <log.h>
  12. #include <part.h>
  13. #include <video.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/arch/clk.h>
  18. #include <lcd.h>
  19. #include <bmp_layout.h>
  20. #include <atmel_lcdc.h>
  21. #include <linux/delay.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #ifdef CONFIG_DM_VIDEO
  24. enum {
  25. /* Maximum LCD size we support */
  26. LCD_MAX_WIDTH = 1366,
  27. LCD_MAX_HEIGHT = 768,
  28. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  29. };
  30. #endif
  31. struct atmel_fb_priv {
  32. struct display_timing timing;
  33. };
  34. /* configurable parameters */
  35. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  36. #define ATMEL_LCDC_DMA_BURST_LEN 8
  37. #ifndef ATMEL_LCDC_GUARD_TIME
  38. #define ATMEL_LCDC_GUARD_TIME 1
  39. #endif
  40. #if defined(CONFIG_AT91SAM9263)
  41. #define ATMEL_LCDC_FIFO_SIZE 2048
  42. #else
  43. #define ATMEL_LCDC_FIFO_SIZE 512
  44. #endif
  45. #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
  46. #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
  47. #ifndef CONFIG_DM_VIDEO
  48. ushort *configuration_get_cmap(void)
  49. {
  50. return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  51. }
  52. #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  53. void fb_put_word(uchar **fb, uchar **from)
  54. {
  55. *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  56. *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  57. *from += 2;
  58. }
  59. #endif
  60. #ifdef CONFIG_LCD_LOGO
  61. #include <bmp_logo.h>
  62. void lcd_logo_set_cmap(void)
  63. {
  64. int i;
  65. uint lut_entry;
  66. ushort colreg;
  67. uint *cmap = (uint *)configuration_get_cmap();
  68. for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  69. colreg = bmp_logo_palette[i];
  70. #ifdef CONFIG_ATMEL_LCD_BGR555
  71. lut_entry = ((colreg & 0x000F) << 11) |
  72. ((colreg & 0x00F0) << 2) |
  73. ((colreg & 0x0F00) >> 7);
  74. #else
  75. lut_entry = ((colreg & 0x000F) << 1) |
  76. ((colreg & 0x00F0) << 3) |
  77. ((colreg & 0x0F00) << 4);
  78. #endif
  79. *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  80. cmap++;
  81. }
  82. }
  83. #endif
  84. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  85. {
  86. #if defined(CONFIG_ATMEL_LCD_BGR555)
  87. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  88. (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  89. #else
  90. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  91. (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  92. #endif
  93. }
  94. void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
  95. {
  96. int i;
  97. for (i = 0; i < colors; ++i) {
  98. struct bmp_color_table_entry cte = bmp->color_table[i];
  99. lcd_setcolreg(i, cte.red, cte.green, cte.blue);
  100. }
  101. }
  102. #endif
  103. static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
  104. bool tft, bool cont_pol_low, ulong lcdbase)
  105. {
  106. unsigned long value;
  107. void *reg = (void *)addr;
  108. /* Turn off the LCD controller and the DMA controller */
  109. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  110. ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
  111. /* Wait for the LCDC core to become idle */
  112. while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  113. udelay(10);
  114. lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
  115. /* Reset LCDC DMA */
  116. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
  117. /* ...set frame size and burst length = 8 words (?) */
  118. value = (timing->hactive.typ * timing->vactive.typ *
  119. (1 << bpix)) / 32;
  120. value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
  121. lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
  122. /* Set pixel clock */
  123. value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
  124. if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
  125. value++;
  126. value = (value / 2) - 1;
  127. if (!value) {
  128. lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
  129. } else
  130. lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
  131. value << ATMEL_LCDC_CLKVAL_OFFSET);
  132. /* Initialize control register 2 */
  133. value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
  134. if (tft)
  135. value |= ATMEL_LCDC_DISTYPE_TFT;
  136. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  137. value |= ATMEL_LCDC_INVLINE_INVERTED;
  138. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  139. value |= ATMEL_LCDC_INVFRAME_INVERTED;
  140. value |= bpix << 5;
  141. lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
  142. /* Vertical timing */
  143. value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
  144. value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
  145. value |= timing->vfront_porch.typ;
  146. /* Magic! (Datasheet says "Bit 31 must be written to 1") */
  147. value |= 1U << 31;
  148. lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
  149. /* Horizontal timing */
  150. value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
  151. value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
  152. value |= (timing->hback_porch.typ - 1);
  153. lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
  154. /* Display size */
  155. value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
  156. value |= timing->vactive.typ - 1;
  157. lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
  158. /* FIFO Threshold: Use formula from data sheet */
  159. value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
  160. lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
  161. /* Toggle LCD_MODE every frame */
  162. lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
  163. /* Disable all interrupts */
  164. lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
  165. /* Set contrast */
  166. value = ATMEL_LCDC_PS_DIV8 |
  167. ATMEL_LCDC_ENA_PWMENABLE;
  168. if (!cont_pol_low)
  169. value |= ATMEL_LCDC_POL_POSITIVE;
  170. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
  171. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
  172. /* Set framebuffer DMA base address and pixel offset */
  173. lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
  174. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
  175. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  176. (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
  177. }
  178. #ifndef CONFIG_DM_VIDEO
  179. void lcd_ctrl_init(void *lcdbase)
  180. {
  181. struct display_timing timing;
  182. timing.flags = 0;
  183. if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
  184. timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
  185. if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
  186. timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
  187. timing.pixelclock.typ = panel_info.vl_clk;
  188. timing.hactive.typ = panel_info.vl_col;
  189. timing.hfront_porch.typ = panel_info.vl_right_margin;
  190. timing.hback_porch.typ = panel_info.vl_left_margin;
  191. timing.hsync_len.typ = panel_info.vl_hsync_len;
  192. timing.vactive.typ = panel_info.vl_row;
  193. timing.vfront_porch.typ = panel_info.vl_clk;
  194. timing.vback_porch.typ = panel_info.vl_clk;
  195. timing.vsync_len.typ = panel_info.vl_clk;
  196. atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
  197. panel_info.vl_tft, panel_info.vl_cont_pol_low,
  198. (ulong)lcdbase);
  199. }
  200. ulong calc_fbsize(void)
  201. {
  202. return ((panel_info.vl_col * panel_info.vl_row *
  203. NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
  204. }
  205. #endif
  206. #ifdef CONFIG_DM_VIDEO
  207. static int atmel_fb_lcd_probe(struct udevice *dev)
  208. {
  209. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  210. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  211. struct atmel_fb_priv *priv = dev_get_priv(dev);
  212. struct display_timing *timing = &priv->timing;
  213. /*
  214. * For now some values are hard-coded. We could use the device tree
  215. * bindings in simple-framebuffer.txt to specify the format/bpp and
  216. * some Atmel-specific binding for tft and cont_pol_low.
  217. */
  218. atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
  219. uc_plat->base);
  220. uc_priv->xsize = timing->hactive.typ;
  221. uc_priv->ysize = timing->vactive.typ;
  222. uc_priv->bpix = VIDEO_BPP16;
  223. video_set_flush_dcache(dev, true);
  224. debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
  225. uc_plat->size, uc_priv->xsize, uc_priv->ysize);
  226. return 0;
  227. }
  228. static int atmel_fb_of_to_plat(struct udevice *dev)
  229. {
  230. struct atmel_lcd_plat *plat = dev_get_plat(dev);
  231. struct atmel_fb_priv *priv = dev_get_priv(dev);
  232. struct display_timing *timing = &priv->timing;
  233. const void *blob = gd->fdt_blob;
  234. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  235. plat->timing_index, timing)) {
  236. debug("%s: Failed to decode display timing\n", __func__);
  237. return -EINVAL;
  238. }
  239. return 0;
  240. }
  241. static int atmel_fb_lcd_bind(struct udevice *dev)
  242. {
  243. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  244. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  245. (1 << VIDEO_BPP16) / 8;
  246. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  247. return 0;
  248. }
  249. static const struct udevice_id atmel_fb_lcd_ids[] = {
  250. { .compatible = "atmel,at91sam9g45-lcdc" },
  251. { }
  252. };
  253. U_BOOT_DRIVER(atmel_fb) = {
  254. .name = "atmel_fb",
  255. .id = UCLASS_VIDEO,
  256. .of_match = atmel_fb_lcd_ids,
  257. .bind = atmel_fb_lcd_bind,
  258. .of_to_plat = atmel_fb_of_to_plat,
  259. .probe = atmel_fb_lcd_probe,
  260. .plat_auto = sizeof(struct atmel_lcd_plat),
  261. .priv_auto = sizeof(struct atmel_fb_priv),
  262. };
  263. #endif