ati_radeon_fb.h 6.7 KB

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  1. #ifndef __ATI_RADEON_FB_H
  2. #define __ATI_RADEON_FB_H
  3. /***************************************************************
  4. * Most of the definitions here are adapted right from XFree86 *
  5. ***************************************************************/
  6. /*
  7. * Chip families. Must fit in the low 16 bits of a long word
  8. */
  9. enum radeon_family {
  10. CHIP_FAMILY_UNKNOW,
  11. CHIP_FAMILY_LEGACY,
  12. CHIP_FAMILY_RADEON,
  13. CHIP_FAMILY_RV100,
  14. CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
  15. CHIP_FAMILY_RV200,
  16. CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
  17. RS250 (IGP 7000) */
  18. CHIP_FAMILY_R200,
  19. CHIP_FAMILY_RV250,
  20. CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
  21. CHIP_FAMILY_RV280,
  22. CHIP_FAMILY_R300,
  23. CHIP_FAMILY_R350,
  24. CHIP_FAMILY_RV350,
  25. CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
  26. CHIP_FAMILY_R420, /* R420/R423/M18 */
  27. CHIP_FAMILY_LAST,
  28. };
  29. #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
  30. ((rinfo)->family == CHIP_FAMILY_RV200) || \
  31. ((rinfo)->family == CHIP_FAMILY_RS100) || \
  32. ((rinfo)->family == CHIP_FAMILY_RS200) || \
  33. ((rinfo)->family == CHIP_FAMILY_RV250) || \
  34. ((rinfo)->family == CHIP_FAMILY_RV280) || \
  35. ((rinfo)->family == CHIP_FAMILY_RS300))
  36. #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
  37. ((rinfo)->family == CHIP_FAMILY_RV350) || \
  38. ((rinfo)->family == CHIP_FAMILY_R350) || \
  39. ((rinfo)->family == CHIP_FAMILY_RV380) || \
  40. ((rinfo)->family == CHIP_FAMILY_R420))
  41. struct radeonfb_info {
  42. char name[20];
  43. struct pci_device_id pdev;
  44. u16 family;
  45. u32 fb_base_bus;
  46. u32 mmio_base_bus;
  47. void *mmio_base;
  48. void *fb_base;
  49. u32 video_ram;
  50. u32 mapped_vram;
  51. int vram_width;
  52. int vram_ddr;
  53. u32 fb_local_base;
  54. };
  55. #define INREG8(addr) readb((rinfo->mmio_base)+addr)
  56. #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
  57. #define INREG16(addr) readw((rinfo->mmio_base)+addr)
  58. #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
  59. #define INREG(addr) readl((rinfo->mmio_base)+addr)
  60. #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
  61. static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
  62. u32 val, u32 mask)
  63. {
  64. unsigned int tmp;
  65. tmp = INREG(addr);
  66. tmp &= (mask);
  67. tmp |= (val);
  68. OUTREG(addr, tmp);
  69. }
  70. #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
  71. /*
  72. * 2D Engine helper routines
  73. */
  74. static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
  75. {
  76. int i;
  77. /* initiate flush */
  78. OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
  79. ~RB2D_DC_FLUSH_ALL);
  80. for (i=0; i < 2000000; i++) {
  81. if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
  82. return;
  83. udelay(1);
  84. }
  85. printf("radeonfb: Flush Timeout !\n");
  86. }
  87. static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
  88. {
  89. int i;
  90. for (i=0; i<2000000; i++) {
  91. if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
  92. return;
  93. udelay(1);
  94. }
  95. printf("radeonfb: FIFO Timeout !\n");
  96. }
  97. static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
  98. {
  99. int i;
  100. /* ensure FIFO is empty before waiting for idle */
  101. _radeon_fifo_wait (rinfo, 64);
  102. for (i=0; i<2000000; i++) {
  103. if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
  104. radeon_engine_flush (rinfo);
  105. return;
  106. }
  107. udelay(1);
  108. }
  109. printf("radeonfb: Idle Timeout !\n");
  110. }
  111. #define radeon_engine_idle() _radeon_engine_idle(rinfo)
  112. #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
  113. #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
  114. /*
  115. * This structure contains the various registers manipulated by this
  116. * driver for setting or restoring a mode. It's mostly copied from
  117. * XFree's RADEONSaveRec structure. A few chip settings might still be
  118. * tweaked without beeing reflected or saved in these registers though
  119. */
  120. struct radeon_regs {
  121. /* Common registers */
  122. u32 ovr_clr;
  123. u32 ovr_wid_left_right;
  124. u32 ovr_wid_top_bottom;
  125. u32 ov0_scale_cntl;
  126. u32 mpp_tb_config;
  127. u32 mpp_gp_config;
  128. u32 subpic_cntl;
  129. u32 viph_control;
  130. u32 i2c_cntl_1;
  131. u32 gen_int_cntl;
  132. u32 cap0_trig_cntl;
  133. u32 cap1_trig_cntl;
  134. u32 bus_cntl;
  135. u32 surface_cntl;
  136. u32 bios_5_scratch;
  137. /* Other registers to save for VT switches or driver load/unload */
  138. u32 dp_datatype;
  139. u32 rbbm_soft_reset;
  140. u32 clock_cntl_index;
  141. u32 amcgpio_en_reg;
  142. u32 amcgpio_mask;
  143. /* Surface/tiling registers */
  144. u32 surf_lower_bound[8];
  145. u32 surf_upper_bound[8];
  146. u32 surf_info[8];
  147. /* CRTC registers */
  148. u32 crtc_gen_cntl;
  149. u32 crtc_ext_cntl;
  150. u32 dac_cntl;
  151. u32 crtc_h_total_disp;
  152. u32 crtc_h_sync_strt_wid;
  153. u32 crtc_v_total_disp;
  154. u32 crtc_v_sync_strt_wid;
  155. u32 crtc_offset;
  156. u32 crtc_offset_cntl;
  157. u32 crtc_pitch;
  158. u32 disp_merge_cntl;
  159. u32 grph_buffer_cntl;
  160. u32 crtc_more_cntl;
  161. /* CRTC2 registers */
  162. u32 crtc2_gen_cntl;
  163. u32 dac2_cntl;
  164. u32 disp_output_cntl;
  165. u32 disp_hw_debug;
  166. u32 disp2_merge_cntl;
  167. u32 grph2_buffer_cntl;
  168. u32 crtc2_h_total_disp;
  169. u32 crtc2_h_sync_strt_wid;
  170. u32 crtc2_v_total_disp;
  171. u32 crtc2_v_sync_strt_wid;
  172. u32 crtc2_offset;
  173. u32 crtc2_offset_cntl;
  174. u32 crtc2_pitch;
  175. /* Flat panel regs */
  176. u32 fp_crtc_h_total_disp;
  177. u32 fp_crtc_v_total_disp;
  178. u32 fp_gen_cntl;
  179. u32 fp2_gen_cntl;
  180. u32 fp_h_sync_strt_wid;
  181. u32 fp2_h_sync_strt_wid;
  182. u32 fp_horz_stretch;
  183. u32 fp_panel_cntl;
  184. u32 fp_v_sync_strt_wid;
  185. u32 fp2_v_sync_strt_wid;
  186. u32 fp_vert_stretch;
  187. u32 lvds_gen_cntl;
  188. u32 lvds_pll_cntl;
  189. u32 tmds_crc;
  190. u32 tmds_transmitter_cntl;
  191. /* Computed values for PLL */
  192. u32 dot_clock_freq;
  193. int feedback_div;
  194. int post_div;
  195. /* PLL registers */
  196. u32 ppll_div_3;
  197. u32 ppll_ref_div;
  198. u32 vclk_ecp_cntl;
  199. u32 clk_cntl_index;
  200. /* Computed values for PLL2 */
  201. u32 dot_clock_freq_2;
  202. int feedback_div_2;
  203. int post_div_2;
  204. /* PLL2 registers */
  205. u32 p2pll_ref_div;
  206. u32 p2pll_div_0;
  207. u32 htotal_cntl2;
  208. /* Palette */
  209. int palette_valid;
  210. };
  211. static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
  212. {
  213. u32 data;
  214. OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
  215. /* radeon_pll_errata_after_index(rinfo); */
  216. data = INREG(CLOCK_CNTL_DATA);
  217. /* radeon_pll_errata_after_data(rinfo); */
  218. return data;
  219. }
  220. static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
  221. u32 val)
  222. {
  223. OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
  224. /* radeon_pll_errata_after_index(rinfo); */
  225. OUTREG(CLOCK_CNTL_DATA, val);
  226. /* radeon_pll_errata_after_data(rinfo); */
  227. }
  228. static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
  229. u32 val, u32 mask)
  230. {
  231. unsigned int tmp;
  232. tmp = __INPLL(rinfo, index);
  233. tmp &= (mask);
  234. tmp |= (val);
  235. __OUTPLL(rinfo, index, tmp);
  236. }
  237. #define INPLL(addr) __INPLL(rinfo, addr)
  238. #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
  239. #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
  240. #endif