anx9804.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) 2015 Hans de Goede <hdegoede@redhat.com>
  4. */
  5. /*
  6. * Support for the ANX9804 bridge chip, which can take pixel data coming
  7. * from a parallel LCD interface and translate it on the flight into a DP
  8. * interface for driving eDP TFT displays.
  9. */
  10. #include <common.h>
  11. #include <i2c.h>
  12. #include <linux/delay.h>
  13. #include "anx98xx-edp.h"
  14. #include "anx9804.h"
  15. /**
  16. * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
  17. *
  18. * This function will init an anx9804 parallel lcd to dp bridge chip
  19. * using the passed in parameters.
  20. *
  21. * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
  22. * @lanes: Number of displayport lanes to use
  23. * @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
  24. * @bpp: Bits per pixel, must be 18 or 24
  25. */
  26. void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
  27. {
  28. unsigned int orig_i2c_bus = i2c_get_bus_num();
  29. u8 c, colordepth;
  30. int i;
  31. i2c_set_bus_num(i2c_bus);
  32. if (bpp == 18)
  33. colordepth = 0x00; /* 6 bit */
  34. else
  35. colordepth = 0x10; /* 8 bit */
  36. /* Reset */
  37. i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
  38. mdelay(100);
  39. i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
  40. /* Write 0 to the powerdown reg (powerup everything) */
  41. i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
  42. c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
  43. if (c != 0x98) {
  44. printf("Error anx9804 chipid mismatch\n");
  45. i2c_set_bus_num(orig_i2c_bus);
  46. return;
  47. }
  48. for (i = 0; i < 100; i++) {
  49. c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
  50. i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
  51. c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
  52. if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
  53. break;
  54. mdelay(5);
  55. }
  56. if (i == 100)
  57. printf("Error anx9804 clock is not stable\n");
  58. i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
  59. /* Set a bunch of analog related register values */
  60. i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
  61. i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
  62. i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
  63. i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
  64. i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
  65. i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
  66. i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
  67. i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
  68. i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
  69. /* Force HPD */
  70. i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
  71. ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
  72. /* Power up and configure lanes */
  73. i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
  74. i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
  75. i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
  76. i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
  77. i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
  78. /* Reset AUX CH */
  79. i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
  80. ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
  81. i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
  82. ANX9804_RST_CTRL2_AC_MODE);
  83. /* Powerdown audio and some other unused bits */
  84. i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
  85. i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
  86. i2c_reg_write(0x38, 0xa7, 0x00);
  87. /* Set data-rate / lanes */
  88. i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
  89. i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
  90. /* Link training */
  91. i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
  92. ANX9804_LINK_TRAINING_CTRL_EN);
  93. mdelay(5);
  94. for (i = 0; i < 100; i++) {
  95. c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
  96. if ((c & 0x01) == 0)
  97. break;
  98. mdelay(5);
  99. }
  100. if(i == 100) {
  101. printf("Error anx9804 link training timeout\n");
  102. i2c_set_bus_num(orig_i2c_bus);
  103. return;
  104. }
  105. /* Enable */
  106. i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
  107. ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
  108. /* Force stream valid */
  109. i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
  110. ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
  111. ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
  112. i2c_set_bus_num(orig_i2c_bus);
  113. }