pic32.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Microchip PIC32 MUSB "glue layer"
  4. *
  5. * Copyright (C) 2015, Microchip Technology Inc.
  6. * Cristian Birsan <cristian.birsan@microchip.com>
  7. * Purna Chandra Mandal <purna.mandal@microchip.com>
  8. *
  9. * Based on the dsps "glue layer" code.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <asm/global_data.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <linux/usb/musb.h>
  18. #include "linux-compat.h"
  19. #include "musb_core.h"
  20. #include "musb_uboot.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define PIC32_TX_EP_MASK 0x0f /* EP0 + 7 Tx EPs */
  23. #define PIC32_RX_EP_MASK 0x0e /* 7 Rx EPs */
  24. #define MUSB_SOFTRST 0x7f
  25. #define MUSB_SOFTRST_NRST BIT(0)
  26. #define MUSB_SOFTRST_NRSTX BIT(1)
  27. #define USBCRCON 0
  28. #define USBCRCON_USBWKUPEN BIT(0) /* Enable Wakeup Interrupt */
  29. #define USBCRCON_USBRIE BIT(1) /* Enable Remote resume Interrupt */
  30. #define USBCRCON_USBIE BIT(2) /* Enable USB General interrupt */
  31. #define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring */
  32. #define USBCRCON_BSVALMONEN BIT(4) /* Enable B-Device VBUS monitoring */
  33. #define USBCRCON_ASVALMONEN BIT(5) /* Enable A-Device VBUS monitoring */
  34. #define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
  35. #define USBCRCON_PHYIDEN BIT(7) /* PHY ID monitoring enable */
  36. #define USBCRCON_USBIDVAL BIT(8) /* USB ID value */
  37. #define USBCRCON_USBIDOVEN BIT(9) /* USB ID override enable */
  38. #define USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
  39. #define USBCRCON_USBRF BIT(25) /* USB Resume Status */
  40. #define USBCRCON_USBIF BIT(26) /* USB General Interrupt Status */
  41. /* PIC32 controller data */
  42. struct pic32_musb_data {
  43. struct musb_host_data mdata;
  44. struct device dev;
  45. void __iomem *musb_glue;
  46. };
  47. #define to_pic32_musb_data(d) \
  48. container_of(d, struct pic32_musb_data, dev)
  49. static void pic32_musb_disable(struct musb *musb)
  50. {
  51. /* no way to shut the controller */
  52. }
  53. static int pic32_musb_enable(struct musb *musb)
  54. {
  55. /* soft reset by NRSTx */
  56. musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
  57. /* set mode */
  58. musb_platform_set_mode(musb, musb->board_mode);
  59. return 0;
  60. }
  61. static irqreturn_t pic32_interrupt(int irq, void *hci)
  62. {
  63. struct musb *musb = hci;
  64. irqreturn_t ret = IRQ_NONE;
  65. u32 epintr, usbintr;
  66. /* ack usb core interrupts */
  67. musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
  68. if (musb->int_usb)
  69. musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
  70. /* ack endpoint interrupts */
  71. musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
  72. if (musb->int_rx)
  73. musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
  74. musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
  75. if (musb->int_tx)
  76. musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
  77. /* drop spurious RX and TX if device is disconnected */
  78. if (musb->int_usb & MUSB_INTR_DISCONNECT) {
  79. musb->int_tx = 0;
  80. musb->int_rx = 0;
  81. }
  82. if (musb->int_tx || musb->int_rx || musb->int_usb)
  83. ret = musb_interrupt(musb);
  84. return ret;
  85. }
  86. static int pic32_musb_set_mode(struct musb *musb, u8 mode)
  87. {
  88. struct device *dev = musb->controller;
  89. struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
  90. switch (mode) {
  91. case MUSB_HOST:
  92. clrsetbits_le32(pdata->musb_glue + USBCRCON,
  93. USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
  94. break;
  95. case MUSB_PERIPHERAL:
  96. setbits_le32(pdata->musb_glue + USBCRCON,
  97. USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
  98. break;
  99. case MUSB_OTG:
  100. dev_err(dev, "support for OTG is unimplemented\n");
  101. break;
  102. default:
  103. dev_err(dev, "unsupported mode %d\n", mode);
  104. return -EINVAL;
  105. }
  106. return 0;
  107. }
  108. static int pic32_musb_init(struct musb *musb)
  109. {
  110. struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
  111. u32 ctrl, hwvers;
  112. u8 power;
  113. /* Returns zero if not clocked */
  114. hwvers = musb_read_hwvers(musb->mregs);
  115. if (!hwvers)
  116. return -ENODEV;
  117. /* Reset the musb */
  118. power = musb_readb(musb->mregs, MUSB_POWER);
  119. power = power | MUSB_POWER_RESET;
  120. musb_writeb(musb->mregs, MUSB_POWER, power);
  121. mdelay(100);
  122. /* Start the on-chip PHY and its PLL. */
  123. power = power & ~MUSB_POWER_RESET;
  124. musb_writeb(musb->mregs, MUSB_POWER, power);
  125. musb->isr = pic32_interrupt;
  126. ctrl = USBCRCON_USBIF | USBCRCON_USBRF |
  127. USBCRCON_USBWK | USBCRCON_USBIDOVEN |
  128. USBCRCON_PHYIDEN | USBCRCON_USBIE |
  129. USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
  130. USBCRCON_VBUSMONEN;
  131. writel(ctrl, pdata->musb_glue + USBCRCON);
  132. return 0;
  133. }
  134. /* PIC32 supports only 32bit read operation */
  135. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  136. {
  137. void __iomem *fifo = hw_ep->fifo;
  138. u32 val, rem = len % 4;
  139. /* USB stack ensures dst is always 32bit aligned. */
  140. readsl(fifo, dst, len / 4);
  141. if (rem) {
  142. dst += len & ~0x03;
  143. val = musb_readl(fifo, 0);
  144. memcpy(dst, &val, rem);
  145. }
  146. }
  147. const struct musb_platform_ops pic32_musb_ops = {
  148. .init = pic32_musb_init,
  149. .set_mode = pic32_musb_set_mode,
  150. .disable = pic32_musb_disable,
  151. .enable = pic32_musb_enable,
  152. };
  153. /* PIC32 default FIFO config - fits in 8KB */
  154. static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
  155. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  156. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  157. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  158. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  159. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  160. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  161. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  162. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  163. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  164. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  165. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
  166. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
  167. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
  168. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
  169. };
  170. static struct musb_hdrc_config pic32_musb_config = {
  171. .fifo_cfg = pic32_musb_fifo_config,
  172. .fifo_cfg_size = ARRAY_SIZE(pic32_musb_fifo_config),
  173. .multipoint = 1,
  174. .dyn_fifo = 1,
  175. .num_eps = 8,
  176. .ram_bits = 11,
  177. };
  178. /* PIC32 has one MUSB controller which can be host or gadget */
  179. static struct musb_hdrc_platform_data pic32_musb_plat = {
  180. .mode = MUSB_HOST,
  181. .config = &pic32_musb_config,
  182. .power = 250, /* 500mA */
  183. .platform_ops = &pic32_musb_ops,
  184. };
  185. static int musb_usb_probe(struct udevice *dev)
  186. {
  187. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  188. struct pic32_musb_data *pdata = dev_get_priv(dev);
  189. struct musb_host_data *mdata = &pdata->mdata;
  190. struct fdt_resource mc, glue;
  191. void *fdt = (void *)gd->fdt_blob;
  192. int node = dev_of_offset(dev);
  193. void __iomem *mregs;
  194. int ret;
  195. priv->desc_before_addr = true;
  196. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  197. "mc", &mc);
  198. if (ret < 0) {
  199. printf("pic32-musb: resource \"mc\" not found\n");
  200. return ret;
  201. }
  202. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  203. "control", &glue);
  204. if (ret < 0) {
  205. printf("pic32-musb: resource \"control\" not found\n");
  206. return ret;
  207. }
  208. mregs = ioremap(mc.start, fdt_resource_size(&mc));
  209. pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
  210. /* init controller */
  211. #ifdef CONFIG_USB_MUSB_HOST
  212. mdata->host = musb_init_controller(&pic32_musb_plat,
  213. &pdata->dev, mregs);
  214. if (!mdata->host)
  215. return -EIO;
  216. ret = musb_lowlevel_init(mdata);
  217. #else
  218. pic32_musb_plat.mode = MUSB_PERIPHERAL;
  219. mdata->host = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
  220. if (!mdata->host)
  221. return -EIO;
  222. #endif
  223. if ((ret == 0) && mdata->host)
  224. printf("PIC32 MUSB OTG\n");
  225. return ret;
  226. }
  227. static int musb_usb_remove(struct udevice *dev)
  228. {
  229. struct pic32_musb_data *pdata = dev_get_priv(dev);
  230. musb_stop(pdata->mdata.host);
  231. return 0;
  232. }
  233. static const struct udevice_id pic32_musb_ids[] = {
  234. { .compatible = "microchip,pic32mzda-usb" },
  235. { }
  236. };
  237. U_BOOT_DRIVER(usb_musb) = {
  238. .name = "pic32-musb",
  239. .id = UCLASS_USB,
  240. .of_match = pic32_musb_ids,
  241. .probe = musb_usb_probe,
  242. .remove = musb_usb_remove,
  243. #ifdef CONFIG_USB_MUSB_HOST
  244. .ops = &musb_usb_ops,
  245. #endif
  246. .plat_auto = sizeof(struct usb_plat),
  247. .priv_auto = sizeof(struct pic32_musb_data),
  248. };