tsc_timer.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. *
  5. * TSC calibration codes are adapted from Linux kernel
  6. * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
  7. */
  8. #include <common.h>
  9. #include <bootstage.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <time.h>
  14. #include <timer.h>
  15. #include <asm/cpu.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <asm/i8254.h>
  19. #include <asm/ibmpc.h>
  20. #include <asm/msr.h>
  21. #include <asm/u-boot-x86.h>
  22. #include <linux/delay.h>
  23. #define MAX_NUM_FREQS 9
  24. #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
  25. #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
  26. #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
  27. #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
  28. #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
  29. #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /*
  32. * native_calibrate_tsc
  33. * Determine TSC frequency via CPUID, else return 0.
  34. */
  35. static unsigned long native_calibrate_tsc(void)
  36. {
  37. struct cpuid_result tsc_info;
  38. unsigned int crystal_freq;
  39. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  40. return 0;
  41. if (cpuid_eax(0) < 0x15)
  42. return 0;
  43. tsc_info = cpuid(0x15);
  44. if (tsc_info.ebx == 0 || tsc_info.eax == 0)
  45. return 0;
  46. crystal_freq = tsc_info.ecx / 1000;
  47. if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
  48. switch (gd->arch.x86_model) {
  49. case INTEL_FAM6_SKYLAKE_MOBILE:
  50. case INTEL_FAM6_SKYLAKE_DESKTOP:
  51. case INTEL_FAM6_KABYLAKE_MOBILE:
  52. case INTEL_FAM6_KABYLAKE_DESKTOP:
  53. crystal_freq = 24000; /* 24.0 MHz */
  54. break;
  55. case INTEL_FAM6_ATOM_GOLDMONT_X:
  56. crystal_freq = 25000; /* 25.0 MHz */
  57. break;
  58. case INTEL_FAM6_ATOM_GOLDMONT:
  59. crystal_freq = 19200; /* 19.2 MHz */
  60. break;
  61. default:
  62. return 0;
  63. }
  64. }
  65. return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
  66. }
  67. static unsigned long cpu_mhz_from_cpuid(void)
  68. {
  69. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  70. return 0;
  71. if (cpuid_eax(0) < 0x16)
  72. return 0;
  73. return cpuid_eax(0x16);
  74. }
  75. /*
  76. * According to Intel 64 and IA-32 System Programming Guide,
  77. * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  78. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  79. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  80. * so we need manually differentiate SoC families. This is what the
  81. * field msr_plat does.
  82. */
  83. struct freq_desc {
  84. u8 x86_family; /* CPU family */
  85. u8 x86_model; /* model */
  86. /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  87. u8 msr_plat;
  88. u32 freqs[MAX_NUM_FREQS];
  89. };
  90. static struct freq_desc freq_desc_tables[] = {
  91. /* PNW */
  92. { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
  93. /* CLV+ */
  94. { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
  95. /* TNG - Intel Atom processor Z3400 series */
  96. { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
  97. /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
  98. { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
  99. /* ANN - Intel Atom processor Z3500 series */
  100. { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
  101. /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
  102. { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
  103. 80000, 93300, 90000, 88900, 87500 } },
  104. /* Ivybridge */
  105. { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
  106. };
  107. static int match_cpu(u8 family, u8 model)
  108. {
  109. int i;
  110. for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
  111. if ((family == freq_desc_tables[i].x86_family) &&
  112. (model == freq_desc_tables[i].x86_model))
  113. return i;
  114. }
  115. return -1;
  116. }
  117. /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  118. #define id_to_freq(cpu_index, freq_id) \
  119. (freq_desc_tables[cpu_index].freqs[freq_id])
  120. /*
  121. * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
  122. * reliable and the frequency is known (provided by HW).
  123. *
  124. * On these platforms PIT/HPET is generally not available so calibration won't
  125. * work at all and there is no other clocksource to act as a watchdog for the
  126. * TSC, so we have no other choice than to trust it.
  127. *
  128. * Returns the TSC frequency in MHz or 0 if HW does not provide it.
  129. */
  130. static unsigned long __maybe_unused cpu_mhz_from_msr(void)
  131. {
  132. u32 lo, hi, ratio, freq_id, freq;
  133. unsigned long res;
  134. int cpu_index;
  135. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  136. return 0;
  137. cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
  138. if (cpu_index < 0)
  139. return 0;
  140. if (freq_desc_tables[cpu_index].msr_plat) {
  141. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  142. ratio = (lo >> 8) & 0xff;
  143. } else {
  144. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  145. ratio = (hi >> 8) & 0x1f;
  146. }
  147. debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
  148. if (freq_desc_tables[cpu_index].msr_plat == 2) {
  149. /* TODO: Figure out how best to deal with this */
  150. freq = 100000;
  151. debug("Using frequency: %u KHz\n", freq);
  152. } else {
  153. /* Get FSB FREQ ID */
  154. rdmsr(MSR_FSB_FREQ, lo, hi);
  155. freq_id = lo & 0x7;
  156. freq = id_to_freq(cpu_index, freq_id);
  157. debug("Resolved frequency ID: %u, frequency: %u KHz\n",
  158. freq_id, freq);
  159. }
  160. /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  161. res = freq * ratio / 1000;
  162. debug("TSC runs at %lu MHz\n", res);
  163. return res;
  164. }
  165. /*
  166. * This reads the current MSB of the PIT counter, and
  167. * checks if we are running on sufficiently fast and
  168. * non-virtualized hardware.
  169. *
  170. * Our expectations are:
  171. *
  172. * - the PIT is running at roughly 1.19MHz
  173. *
  174. * - each IO is going to take about 1us on real hardware,
  175. * but we allow it to be much faster (by a factor of 10) or
  176. * _slightly_ slower (ie we allow up to a 2us read+counter
  177. * update - anything else implies a unacceptably slow CPU
  178. * or PIT for the fast calibration to work.
  179. *
  180. * - with 256 PIT ticks to read the value, we have 214us to
  181. * see the same MSB (and overhead like doing a single TSC
  182. * read per MSB value etc).
  183. *
  184. * - We're doing 2 reads per loop (LSB, MSB), and we expect
  185. * them each to take about a microsecond on real hardware.
  186. * So we expect a count value of around 100. But we'll be
  187. * generous, and accept anything over 50.
  188. *
  189. * - if the PIT is stuck, and we see *many* more reads, we
  190. * return early (and the next caller of pit_expect_msb()
  191. * then consider it a failure when they don't see the
  192. * next expected value).
  193. *
  194. * These expectations mean that we know that we have seen the
  195. * transition from one expected value to another with a fairly
  196. * high accuracy, and we didn't miss any events. We can thus
  197. * use the TSC value at the transitions to calculate a pretty
  198. * good value for the TSC frequencty.
  199. */
  200. static inline int pit_verify_msb(unsigned char val)
  201. {
  202. /* Ignore LSB */
  203. inb(0x42);
  204. return inb(0x42) == val;
  205. }
  206. static inline int pit_expect_msb(unsigned char val, u64 *tscp,
  207. unsigned long *deltap)
  208. {
  209. int count;
  210. u64 tsc = 0, prev_tsc = 0;
  211. for (count = 0; count < 50000; count++) {
  212. if (!pit_verify_msb(val))
  213. break;
  214. prev_tsc = tsc;
  215. tsc = rdtsc();
  216. }
  217. *deltap = rdtsc() - prev_tsc;
  218. *tscp = tsc;
  219. /*
  220. * We require _some_ success, but the quality control
  221. * will be based on the error terms on the TSC values.
  222. */
  223. return count > 5;
  224. }
  225. /*
  226. * How many MSB values do we want to see? We aim for
  227. * a maximum error rate of 500ppm (in practice the
  228. * real error is much smaller), but refuse to spend
  229. * more than 50ms on it.
  230. */
  231. #define MAX_QUICK_PIT_MS 50
  232. #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
  233. static unsigned long __maybe_unused quick_pit_calibrate(void)
  234. {
  235. int i;
  236. u64 tsc, delta;
  237. unsigned long d1, d2;
  238. /* Set the Gate high, disable speaker */
  239. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  240. /*
  241. * Counter 2, mode 0 (one-shot), binary count
  242. *
  243. * NOTE! Mode 2 decrements by two (and then the
  244. * output is flipped each time, giving the same
  245. * final output frequency as a decrement-by-one),
  246. * so mode 0 is much better when looking at the
  247. * individual counts.
  248. */
  249. outb(0xb0, 0x43);
  250. /* Start at 0xffff */
  251. outb(0xff, 0x42);
  252. outb(0xff, 0x42);
  253. /*
  254. * The PIT starts counting at the next edge, so we
  255. * need to delay for a microsecond. The easiest way
  256. * to do that is to just read back the 16-bit counter
  257. * once from the PIT.
  258. */
  259. pit_verify_msb(0);
  260. if (pit_expect_msb(0xff, &tsc, &d1)) {
  261. for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
  262. if (!pit_expect_msb(0xff-i, &delta, &d2))
  263. break;
  264. /*
  265. * Iterate until the error is less than 500 ppm
  266. */
  267. delta -= tsc;
  268. if (d1+d2 >= delta >> 11)
  269. continue;
  270. /*
  271. * Check the PIT one more time to verify that
  272. * all TSC reads were stable wrt the PIT.
  273. *
  274. * This also guarantees serialization of the
  275. * last cycle read ('d2') in pit_expect_msb.
  276. */
  277. if (!pit_verify_msb(0xfe - i))
  278. break;
  279. goto success;
  280. }
  281. }
  282. debug("Fast TSC calibration failed\n");
  283. return 0;
  284. success:
  285. /*
  286. * Ok, if we get here, then we've seen the
  287. * MSB of the PIT decrement 'i' times, and the
  288. * error has shrunk to less than 500 ppm.
  289. *
  290. * As a result, we can depend on there not being
  291. * any odd delays anywhere, and the TSC reads are
  292. * reliable (within the error).
  293. *
  294. * kHz = ticks / time-in-seconds / 1000;
  295. * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
  296. * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
  297. */
  298. delta *= PIT_TICK_RATE;
  299. delta /= (i*256*1000);
  300. debug("Fast TSC calibration using PIT\n");
  301. return delta / 1000;
  302. }
  303. /* Get the speed of the TSC timer in MHz */
  304. unsigned notrace long get_tbclk_mhz(void)
  305. {
  306. return get_tbclk() / 1000000;
  307. }
  308. static ulong get_ms_timer(void)
  309. {
  310. return (get_ticks() * 1000) / get_tbclk();
  311. }
  312. ulong get_timer(ulong base)
  313. {
  314. return get_ms_timer() - base;
  315. }
  316. ulong notrace timer_get_us(void)
  317. {
  318. return get_ticks() / get_tbclk_mhz();
  319. }
  320. ulong timer_get_boot_us(void)
  321. {
  322. return timer_get_us();
  323. }
  324. void __udelay(unsigned long usec)
  325. {
  326. u64 now = get_ticks();
  327. u64 stop;
  328. stop = now + (u64)usec * get_tbclk_mhz();
  329. while ((int64_t)(stop - get_ticks()) > 0)
  330. #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
  331. /*
  332. * Add a 'pause' instruction on qemu target,
  333. * to give other VCPUs a chance to run.
  334. */
  335. asm volatile("pause");
  336. #else
  337. ;
  338. #endif
  339. }
  340. static u64 tsc_timer_get_count(struct udevice *dev)
  341. {
  342. u64 now_tick = rdtsc();
  343. return now_tick - gd->arch.tsc_base;
  344. }
  345. static void tsc_timer_ensure_setup(bool early)
  346. {
  347. if (gd->arch.tsc_inited)
  348. return;
  349. if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
  350. gd->arch.tsc_base = rdtsc();
  351. if (!gd->arch.clock_rate) {
  352. unsigned long fast_calibrate;
  353. fast_calibrate = native_calibrate_tsc();
  354. if (fast_calibrate)
  355. goto done;
  356. /* Reduce code size by dropping other methods */
  357. if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
  358. panic("no timer");
  359. fast_calibrate = cpu_mhz_from_cpuid();
  360. if (fast_calibrate)
  361. goto done;
  362. fast_calibrate = cpu_mhz_from_msr();
  363. if (fast_calibrate)
  364. goto done;
  365. fast_calibrate = quick_pit_calibrate();
  366. if (fast_calibrate)
  367. goto done;
  368. if (early)
  369. gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ;
  370. else
  371. return;
  372. done:
  373. if (!gd->arch.clock_rate)
  374. gd->arch.clock_rate = fast_calibrate * 1000000;
  375. }
  376. gd->arch.tsc_inited = true;
  377. }
  378. static int tsc_timer_probe(struct udevice *dev)
  379. {
  380. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  381. /* Try hardware calibration first */
  382. tsc_timer_ensure_setup(false);
  383. if (!gd->arch.clock_rate) {
  384. /*
  385. * Use the clock frequency specified in the
  386. * device tree as last resort
  387. */
  388. if (!uc_priv->clock_rate)
  389. panic("TSC frequency is ZERO");
  390. } else {
  391. uc_priv->clock_rate = gd->arch.clock_rate;
  392. }
  393. return 0;
  394. }
  395. unsigned long notrace timer_early_get_rate(void)
  396. {
  397. /*
  398. * When TSC timer is used as the early timer, be warned that the timer
  399. * clock rate can only be calibrated via some hardware ways. Specifying
  400. * it in the device tree won't work for the early timer.
  401. */
  402. tsc_timer_ensure_setup(true);
  403. return gd->arch.clock_rate;
  404. }
  405. u64 notrace timer_early_get_count(void)
  406. {
  407. tsc_timer_ensure_setup(true);
  408. return rdtsc() - gd->arch.tsc_base;
  409. }
  410. static const struct timer_ops tsc_timer_ops = {
  411. .get_count = tsc_timer_get_count,
  412. };
  413. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  414. static const struct udevice_id tsc_timer_ids[] = {
  415. { .compatible = "x86,tsc-timer", },
  416. { }
  417. };
  418. #endif
  419. U_BOOT_DRIVER(x86_tsc_timer) = {
  420. .name = "x86_tsc_timer",
  421. .id = UCLASS_TIMER,
  422. .of_match = of_match_ptr(tsc_timer_ids),
  423. .probe = tsc_timer_probe,
  424. .ops = &tsc_timer_ops,
  425. };