rockchip_timer.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
  4. */
  5. #include <common.h>
  6. #include <bootstage.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/global_data.h>
  11. #include <dm/ofnode.h>
  12. #include <mapmem.h>
  13. #include <asm/arch-rockchip/timer.h>
  14. #include <dt-structs.h>
  15. #include <timer.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  19. struct rockchip_timer_plat {
  20. struct dtd_rockchip_rk3368_timer dtd;
  21. };
  22. #endif
  23. /* Driver private data. Contains timer id. Could be either 0 or 1. */
  24. struct rockchip_timer_priv {
  25. struct rk_timer *timer;
  26. };
  27. static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
  28. {
  29. uint64_t timebase_h, timebase_l;
  30. uint64_t cntr;
  31. timebase_l = readl(&timer->timer_curr_value0);
  32. timebase_h = readl(&timer->timer_curr_value1);
  33. cntr = timebase_h << 32 | timebase_l;
  34. return cntr;
  35. }
  36. #if CONFIG_IS_ENABLED(BOOTSTAGE)
  37. ulong timer_get_boot_us(void)
  38. {
  39. uint64_t ticks = 0;
  40. uint32_t rate;
  41. uint64_t us;
  42. int ret;
  43. ret = dm_timer_init();
  44. if (!ret) {
  45. /* The timer is available */
  46. rate = timer_get_rate(gd->timer);
  47. timer_get_count(gd->timer, &ticks);
  48. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  49. } else if (ret == -EAGAIN) {
  50. /* We have been called so early that the DM is not ready,... */
  51. ofnode node = offset_to_ofnode(-1);
  52. struct rk_timer *timer = NULL;
  53. /*
  54. * ... so we try to access the raw timer, if it is specified
  55. * via the tick-timer property in /chosen.
  56. */
  57. node = ofnode_get_chosen_node("tick-timer");
  58. if (!ofnode_valid(node)) {
  59. debug("%s: no /chosen/tick-timer\n", __func__);
  60. return 0;
  61. }
  62. timer = (struct rk_timer *)ofnode_get_addr(node);
  63. /* This timer is down-counting */
  64. ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
  65. if (ofnode_read_u32(node, "clock-frequency", &rate)) {
  66. debug("%s: could not read clock-frequency\n", __func__);
  67. return 0;
  68. }
  69. #endif
  70. } else {
  71. return 0;
  72. }
  73. us = (ticks * 1000) / rate;
  74. return us;
  75. }
  76. #endif
  77. static u64 rockchip_timer_get_count(struct udevice *dev)
  78. {
  79. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  80. uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
  81. /* timers are down-counting */
  82. return ~0ull - cntr;
  83. }
  84. static int rockchip_clk_of_to_plat(struct udevice *dev)
  85. {
  86. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  87. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  88. priv->timer = dev_read_addr_ptr(dev);
  89. if (!priv->timer)
  90. return -ENOENT;
  91. #endif
  92. return 0;
  93. }
  94. static int rockchip_timer_start(struct udevice *dev)
  95. {
  96. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  97. const uint64_t reload_val = ~0uLL;
  98. const uint32_t reload_val_l = reload_val & 0xffffffff;
  99. const uint32_t reload_val_h = reload_val >> 32;
  100. /* don't reinit, if the timer is already running and set up */
  101. if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
  102. (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
  103. (readl(&priv->timer->timer_load_count1) == reload_val_h))
  104. return 0;
  105. /* disable timer and reset all control */
  106. writel(0, &priv->timer->timer_ctrl_reg);
  107. /* write reload value */
  108. writel(reload_val_l, &priv->timer->timer_load_count0);
  109. writel(reload_val_h, &priv->timer->timer_load_count1);
  110. /* enable timer */
  111. writel(1, &priv->timer->timer_ctrl_reg);
  112. return 0;
  113. }
  114. static int rockchip_timer_probe(struct udevice *dev)
  115. {
  116. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  117. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  118. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  119. struct rockchip_timer_plat *plat = dev_get_plat(dev);
  120. priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  121. uc_priv->clock_rate = plat->dtd.clock_frequency;
  122. #endif
  123. return rockchip_timer_start(dev);
  124. }
  125. static const struct timer_ops rockchip_timer_ops = {
  126. .get_count = rockchip_timer_get_count,
  127. };
  128. static const struct udevice_id rockchip_timer_ids[] = {
  129. { .compatible = "rockchip,rk3188-timer" },
  130. { .compatible = "rockchip,rk3288-timer" },
  131. { .compatible = "rockchip,rk3368-timer" },
  132. {}
  133. };
  134. U_BOOT_DRIVER(rockchip_rk3368_timer) = {
  135. .name = "rockchip_rk3368_timer",
  136. .id = UCLASS_TIMER,
  137. .of_match = rockchip_timer_ids,
  138. .probe = rockchip_timer_probe,
  139. .ops = &rockchip_timer_ops,
  140. .priv_auto = sizeof(struct rockchip_timer_priv),
  141. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  142. .plat_auto = sizeof(struct rockchip_timer_plat),
  143. #endif
  144. .of_to_plat = rockchip_clk_of_to_plat,
  145. };