arc_timer.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Synopsys, Inc. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <timer.h>
  9. #include <asm/arcregs.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #define NH_MODE (1 << 1)
  14. /*
  15. * ARC timer control registers are mapped to auxiliary address space.
  16. * There are special ARC asm command to access that addresses.
  17. * Therefore we use built-in functions to read from and write to timer
  18. * control register.
  19. */
  20. /* Driver private data. Contains timer id. Could be either 0 or 1. */
  21. struct arc_timer_priv {
  22. uint timer_id;
  23. };
  24. static u64 arc_timer_get_count(struct udevice *dev)
  25. {
  26. u32 val = 0;
  27. struct arc_timer_priv *priv = dev_get_priv(dev);
  28. switch (priv->timer_id) {
  29. case 0:
  30. val = read_aux_reg(ARC_AUX_TIMER0_CNT);
  31. break;
  32. case 1:
  33. val = read_aux_reg(ARC_AUX_TIMER1_CNT);
  34. break;
  35. }
  36. return timer_conv_64(val);
  37. }
  38. static int arc_timer_probe(struct udevice *dev)
  39. {
  40. int id;
  41. struct arc_timer_priv *priv = dev_get_priv(dev);
  42. /* Get registers offset and size */
  43. id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
  44. if (id < 0)
  45. return -EINVAL;
  46. if (id > 1)
  47. return -ENXIO;
  48. priv->timer_id = (uint)id;
  49. /*
  50. * In ARC core there're special registers (Auxiliary or AUX) in its
  51. * separate memory space that are used for accessing some hardware
  52. * features of the core. They are not mapped in normal memory space
  53. * and also always have the same location regardless core configuration.
  54. * Thus to simplify understanding of the programming model we chose to
  55. * access AUX regs of Timer0 and Timer1 separately instead of using
  56. * offsets from some base address.
  57. */
  58. switch (priv->timer_id) {
  59. case 0:
  60. /* Disable timer if CPU is halted */
  61. write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
  62. /* Set max value for counter/timer */
  63. write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
  64. /* Set initial count value and restart counter/timer */
  65. write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
  66. break;
  67. case 1:
  68. /* Disable timer if CPU is halted */
  69. write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE);
  70. /* Set max value for counter/timer */
  71. write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff);
  72. /* Set initial count value and restart counter/timer */
  73. write_aux_reg(ARC_AUX_TIMER1_CNT, 0);
  74. break;
  75. }
  76. return 0;
  77. }
  78. static const struct timer_ops arc_timer_ops = {
  79. .get_count = arc_timer_get_count,
  80. };
  81. static const struct udevice_id arc_timer_ids[] = {
  82. { .compatible = "snps,arc-timer" },
  83. {}
  84. };
  85. U_BOOT_DRIVER(arc_timer) = {
  86. .name = "arc_timer",
  87. .id = UCLASS_TIMER,
  88. .of_match = arc_timer_ids,
  89. .probe = arc_timer_probe,
  90. .ops = &arc_timer_ops,
  91. .priv_auto = sizeof(struct arc_timer_priv),
  92. };