zynq_spi.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq PS SPI controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <time.h>
  15. #include <clk.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
  22. #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  23. #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  24. #define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
  25. #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  26. #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  27. #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  28. #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  29. #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  30. #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  31. #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  32. #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  33. #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  34. #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  35. #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
  36. #define ZYNQ_SPI_FIFO_DEPTH 128
  37. #define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
  38. /* zynq spi register set */
  39. struct zynq_spi_regs {
  40. u32 cr; /* 0x00 */
  41. u32 isr; /* 0x04 */
  42. u32 ier; /* 0x08 */
  43. u32 idr; /* 0x0C */
  44. u32 imr; /* 0x10 */
  45. u32 enr; /* 0x14 */
  46. u32 dr; /* 0x18 */
  47. u32 txdr; /* 0x1C */
  48. u32 rxdr; /* 0x20 */
  49. };
  50. /* zynq spi platform data */
  51. struct zynq_spi_plat {
  52. struct zynq_spi_regs *regs;
  53. u32 frequency; /* input frequency */
  54. u32 speed_hz;
  55. uint deactivate_delay_us; /* Delay to wait after deactivate */
  56. uint activate_delay_us; /* Delay to wait after activate */
  57. };
  58. /* zynq spi priv */
  59. struct zynq_spi_priv {
  60. struct zynq_spi_regs *regs;
  61. u8 cs;
  62. u8 mode;
  63. ulong last_transaction_us; /* Time of last transaction end */
  64. u8 fifo_depth;
  65. u32 freq; /* required frequency */
  66. };
  67. static int zynq_spi_of_to_plat(struct udevice *bus)
  68. {
  69. struct zynq_spi_plat *plat = dev_get_plat(bus);
  70. const void *blob = gd->fdt_blob;
  71. int node = dev_of_offset(bus);
  72. plat->regs = dev_read_addr_ptr(bus);
  73. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  74. "spi-deactivate-delay", 0);
  75. plat->activate_delay_us = fdtdec_get_int(blob, node,
  76. "spi-activate-delay", 0);
  77. return 0;
  78. }
  79. static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
  80. {
  81. struct zynq_spi_regs *regs = priv->regs;
  82. u32 confr;
  83. /* Disable SPI */
  84. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  85. writel(~confr, &regs->enr);
  86. /* Disable Interrupts */
  87. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
  88. /* Clear RX FIFO */
  89. while (readl(&regs->isr) &
  90. ZYNQ_SPI_IXR_RXNEMPTY_MASK)
  91. readl(&regs->rxdr);
  92. /* Clear Interrupts */
  93. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
  94. /* Manual slave select and Auto start */
  95. confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
  96. ZYNQ_SPI_CR_MSTREN_MASK;
  97. confr &= ~ZYNQ_SPI_CR_MSA_MASK;
  98. writel(confr, &regs->cr);
  99. /* Enable SPI */
  100. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  101. }
  102. static int zynq_spi_probe(struct udevice *bus)
  103. {
  104. struct zynq_spi_plat *plat = dev_get_plat(bus);
  105. struct zynq_spi_priv *priv = dev_get_priv(bus);
  106. struct clk clk;
  107. unsigned long clock;
  108. int ret;
  109. priv->regs = plat->regs;
  110. priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
  111. ret = clk_get_by_name(bus, "ref_clk", &clk);
  112. if (ret < 0) {
  113. dev_err(bus, "failed to get clock\n");
  114. return ret;
  115. }
  116. clock = clk_get_rate(&clk);
  117. if (IS_ERR_VALUE(clock)) {
  118. dev_err(bus, "failed to get rate\n");
  119. return clock;
  120. }
  121. ret = clk_enable(&clk);
  122. if (ret) {
  123. dev_err(bus, "failed to enable clock\n");
  124. return ret;
  125. }
  126. /* init the zynq spi hw */
  127. zynq_spi_init_hw(priv);
  128. plat->frequency = clock;
  129. plat->speed_hz = plat->frequency / 2;
  130. debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
  131. return 0;
  132. }
  133. static void spi_cs_activate(struct udevice *dev)
  134. {
  135. struct udevice *bus = dev->parent;
  136. struct zynq_spi_plat *plat = dev_get_plat(bus);
  137. struct zynq_spi_priv *priv = dev_get_priv(bus);
  138. struct zynq_spi_regs *regs = priv->regs;
  139. u32 cr;
  140. /* If it's too soon to do another transaction, wait */
  141. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  142. ulong delay_us; /* The delay completed so far */
  143. delay_us = timer_get_us() - priv->last_transaction_us;
  144. if (delay_us < plat->deactivate_delay_us)
  145. udelay(plat->deactivate_delay_us - delay_us);
  146. }
  147. clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  148. cr = readl(&regs->cr);
  149. /*
  150. * CS cal logic: CS[13:10]
  151. * xxx0 - cs0
  152. * xx01 - cs1
  153. * x011 - cs2
  154. */
  155. cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
  156. writel(cr, &regs->cr);
  157. if (plat->activate_delay_us)
  158. udelay(plat->activate_delay_us);
  159. }
  160. static void spi_cs_deactivate(struct udevice *dev)
  161. {
  162. struct udevice *bus = dev->parent;
  163. struct zynq_spi_plat *plat = dev_get_plat(bus);
  164. struct zynq_spi_priv *priv = dev_get_priv(bus);
  165. struct zynq_spi_regs *regs = priv->regs;
  166. setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  167. /* Remember time of this transaction so we can honour the bus delay */
  168. if (plat->deactivate_delay_us)
  169. priv->last_transaction_us = timer_get_us();
  170. }
  171. static int zynq_spi_claim_bus(struct udevice *dev)
  172. {
  173. struct udevice *bus = dev->parent;
  174. struct zynq_spi_priv *priv = dev_get_priv(bus);
  175. struct zynq_spi_regs *regs = priv->regs;
  176. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  177. return 0;
  178. }
  179. static int zynq_spi_release_bus(struct udevice *dev)
  180. {
  181. struct udevice *bus = dev->parent;
  182. struct zynq_spi_priv *priv = dev_get_priv(bus);
  183. struct zynq_spi_regs *regs = priv->regs;
  184. u32 confr;
  185. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  186. writel(~confr, &regs->enr);
  187. return 0;
  188. }
  189. static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
  190. const void *dout, void *din, unsigned long flags)
  191. {
  192. struct udevice *bus = dev->parent;
  193. struct zynq_spi_priv *priv = dev_get_priv(bus);
  194. struct zynq_spi_regs *regs = priv->regs;
  195. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  196. u32 len = bitlen / 8;
  197. u32 tx_len = len, rx_len = len, tx_tvl;
  198. const u8 *tx_buf = dout;
  199. u8 *rx_buf = din, buf;
  200. u32 ts, status;
  201. debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  202. dev_seq(bus), slave_plat->cs, bitlen, len, flags);
  203. if (bitlen % 8) {
  204. debug("spi_xfer: Non byte aligned SPI transfer\n");
  205. return -1;
  206. }
  207. priv->cs = slave_plat->cs;
  208. if (flags & SPI_XFER_BEGIN)
  209. spi_cs_activate(dev);
  210. while (rx_len > 0) {
  211. /* Write the data into TX FIFO - tx threshold is fifo_depth */
  212. tx_tvl = 0;
  213. while ((tx_tvl < priv->fifo_depth) && tx_len) {
  214. if (tx_buf)
  215. buf = *tx_buf++;
  216. else
  217. buf = 0;
  218. writel(buf, &regs->txdr);
  219. tx_len--;
  220. tx_tvl++;
  221. }
  222. /* Check TX FIFO completion */
  223. ts = get_timer(0);
  224. status = readl(&regs->isr);
  225. while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
  226. if (get_timer(ts) > ZYNQ_SPI_WAIT) {
  227. printf("spi_xfer: Timeout! TX FIFO not full\n");
  228. return -1;
  229. }
  230. status = readl(&regs->isr);
  231. }
  232. /* Read the data from RX FIFO */
  233. status = readl(&regs->isr);
  234. while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
  235. buf = readl(&regs->rxdr);
  236. if (rx_buf)
  237. *rx_buf++ = buf;
  238. status = readl(&regs->isr);
  239. rx_len--;
  240. }
  241. }
  242. if (flags & SPI_XFER_END)
  243. spi_cs_deactivate(dev);
  244. return 0;
  245. }
  246. static int zynq_spi_set_speed(struct udevice *bus, uint speed)
  247. {
  248. struct zynq_spi_plat *plat = dev_get_plat(bus);
  249. struct zynq_spi_priv *priv = dev_get_priv(bus);
  250. struct zynq_spi_regs *regs = priv->regs;
  251. uint32_t confr;
  252. u8 baud_rate_val = 0;
  253. if (speed > plat->frequency)
  254. speed = plat->frequency;
  255. /* Set the clock frequency */
  256. confr = readl(&regs->cr);
  257. if (speed == 0) {
  258. /* Set baudrate x8, if the freq is 0 */
  259. baud_rate_val = 0x2;
  260. } else if (plat->speed_hz != speed) {
  261. while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
  262. ((plat->frequency /
  263. (2 << baud_rate_val)) > speed))
  264. baud_rate_val++;
  265. plat->speed_hz = speed / (2 << baud_rate_val);
  266. }
  267. confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
  268. confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
  269. writel(confr, &regs->cr);
  270. priv->freq = speed;
  271. debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
  272. priv->regs, priv->freq);
  273. return 0;
  274. }
  275. static int zynq_spi_set_mode(struct udevice *bus, uint mode)
  276. {
  277. struct zynq_spi_priv *priv = dev_get_priv(bus);
  278. struct zynq_spi_regs *regs = priv->regs;
  279. uint32_t confr;
  280. /* Set the SPI Clock phase and polarities */
  281. confr = readl(&regs->cr);
  282. confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
  283. if (mode & SPI_CPHA)
  284. confr |= ZYNQ_SPI_CR_CPHA_MASK;
  285. if (mode & SPI_CPOL)
  286. confr |= ZYNQ_SPI_CR_CPOL_MASK;
  287. writel(confr, &regs->cr);
  288. priv->mode = mode;
  289. debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
  290. return 0;
  291. }
  292. static const struct dm_spi_ops zynq_spi_ops = {
  293. .claim_bus = zynq_spi_claim_bus,
  294. .release_bus = zynq_spi_release_bus,
  295. .xfer = zynq_spi_xfer,
  296. .set_speed = zynq_spi_set_speed,
  297. .set_mode = zynq_spi_set_mode,
  298. };
  299. static const struct udevice_id zynq_spi_ids[] = {
  300. { .compatible = "xlnx,zynq-spi-r1p6" },
  301. { .compatible = "cdns,spi-r1p6" },
  302. { }
  303. };
  304. U_BOOT_DRIVER(zynq_spi) = {
  305. .name = "zynq_spi",
  306. .id = UCLASS_SPI,
  307. .of_match = zynq_spi_ids,
  308. .ops = &zynq_spi_ops,
  309. .of_to_plat = zynq_spi_of_to_plat,
  310. .plat_auto = sizeof(struct zynq_spi_plat),
  311. .priv_auto = sizeof(struct zynq_spi_priv),
  312. .probe = zynq_spi_probe,
  313. };