zynq_qspi.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <dm/device_compat.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <linux/bitops.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
  20. #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
  21. #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  22. #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  23. #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
  24. #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
  25. #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
  26. #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  27. #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  28. #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  29. #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  30. #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  31. #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  32. #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  33. #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  34. #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
  35. /* zynq qspi Transmit Data Register */
  36. #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
  37. #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
  38. #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
  39. #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
  40. #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
  41. #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
  42. #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  43. #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  44. #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
  45. #define ZYNQ_QSPI_FIFO_DEPTH 63
  46. #define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
  47. /* zynq qspi register set */
  48. struct zynq_qspi_regs {
  49. u32 cr; /* 0x00 */
  50. u32 isr; /* 0x04 */
  51. u32 ier; /* 0x08 */
  52. u32 idr; /* 0x0C */
  53. u32 imr; /* 0x10 */
  54. u32 enr; /* 0x14 */
  55. u32 dr; /* 0x18 */
  56. u32 txd0r; /* 0x1C */
  57. u32 drxr; /* 0x20 */
  58. u32 sicr; /* 0x24 */
  59. u32 txftr; /* 0x28 */
  60. u32 rxftr; /* 0x2C */
  61. u32 gpior; /* 0x30 */
  62. u32 reserved0[19];
  63. u32 txd1r; /* 0x80 */
  64. u32 txd2r; /* 0x84 */
  65. u32 txd3r; /* 0x88 */
  66. u32 reserved1[5];
  67. u32 lqspicfg; /* 0xA0 */
  68. u32 lqspists; /* 0xA4 */
  69. };
  70. /* zynq qspi platform data */
  71. struct zynq_qspi_plat {
  72. struct zynq_qspi_regs *regs;
  73. u32 frequency; /* input frequency */
  74. u32 speed_hz;
  75. };
  76. /* zynq qspi priv */
  77. struct zynq_qspi_priv {
  78. struct zynq_qspi_regs *regs;
  79. u8 cs;
  80. u8 mode;
  81. u8 fifo_depth;
  82. u32 freq; /* required frequency */
  83. const void *tx_buf;
  84. void *rx_buf;
  85. unsigned len;
  86. int bytes_to_transfer;
  87. int bytes_to_receive;
  88. unsigned int is_inst;
  89. unsigned cs_change:1;
  90. };
  91. static int zynq_qspi_of_to_plat(struct udevice *bus)
  92. {
  93. struct zynq_qspi_plat *plat = dev_get_plat(bus);
  94. const void *blob = gd->fdt_blob;
  95. int node = dev_of_offset(bus);
  96. plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
  97. node, "reg");
  98. return 0;
  99. }
  100. /**
  101. * zynq_qspi_init_hw - Initialize the hardware
  102. * @priv: Pointer to the zynq_qspi_priv structure
  103. *
  104. * The default settings of the QSPI controller's configurable parameters on
  105. * reset are
  106. * - Master mode
  107. * - Baud rate divisor is set to 2
  108. * - Threshold value for TX FIFO not full interrupt is set to 1
  109. * - Flash memory interface mode enabled
  110. * - Size of the word to be transferred as 8 bit
  111. * This function performs the following actions
  112. * - Disable and clear all the interrupts
  113. * - Enable manual slave select
  114. * - Enable auto start
  115. * - Deselect all the chip select lines
  116. * - Set the size of the word to be transferred as 32 bit
  117. * - Set the little endian mode of TX FIFO and
  118. * - Enable the QSPI controller
  119. */
  120. static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
  121. {
  122. struct zynq_qspi_regs *regs = priv->regs;
  123. u32 confr;
  124. /* Disable QSPI */
  125. writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  126. /* Disable Interrupts */
  127. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
  128. /* Clear the TX and RX threshold reg */
  129. writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
  130. writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
  131. /* Clear the RX FIFO */
  132. while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
  133. readl(&regs->drxr);
  134. /* Clear Interrupts */
  135. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
  136. /* Manual slave select and Auto start */
  137. confr = readl(&regs->cr);
  138. confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
  139. confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
  140. ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
  141. ZYNQ_QSPI_CR_MSTREN_MASK;
  142. writel(confr, &regs->cr);
  143. /* Disable the LQSPI feature */
  144. confr = readl(&regs->lqspicfg);
  145. confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
  146. writel(confr, &regs->lqspicfg);
  147. /* Enable SPI */
  148. writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  149. }
  150. static int zynq_qspi_probe(struct udevice *bus)
  151. {
  152. struct zynq_qspi_plat *plat = dev_get_plat(bus);
  153. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  154. struct clk clk;
  155. unsigned long clock;
  156. int ret;
  157. priv->regs = plat->regs;
  158. priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
  159. ret = clk_get_by_name(bus, "ref_clk", &clk);
  160. if (ret < 0) {
  161. dev_err(bus, "failed to get clock\n");
  162. return ret;
  163. }
  164. clock = clk_get_rate(&clk);
  165. if (IS_ERR_VALUE(clock)) {
  166. dev_err(bus, "failed to get rate\n");
  167. return clock;
  168. }
  169. ret = clk_enable(&clk);
  170. if (ret) {
  171. dev_err(bus, "failed to enable clock\n");
  172. return ret;
  173. }
  174. /* init the zynq spi hw */
  175. zynq_qspi_init_hw(priv);
  176. plat->frequency = clock;
  177. plat->speed_hz = plat->frequency / 2;
  178. debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
  179. return 0;
  180. }
  181. /**
  182. * zynq_qspi_read_data - Copy data to RX buffer
  183. * @priv: Pointer to the zynq_qspi_priv structure
  184. * @data: The 32 bit variable where data is stored
  185. * @size: Number of bytes to be copied from data to RX buffer
  186. */
  187. static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
  188. {
  189. u8 byte3;
  190. debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
  191. data, (unsigned)(priv->rx_buf), size);
  192. if (priv->rx_buf) {
  193. switch (size) {
  194. case 1:
  195. *((u8 *)priv->rx_buf) = data;
  196. priv->rx_buf += 1;
  197. break;
  198. case 2:
  199. *((u16 *)priv->rx_buf) = data;
  200. priv->rx_buf += 2;
  201. break;
  202. case 3:
  203. *((u16 *)priv->rx_buf) = data;
  204. priv->rx_buf += 2;
  205. byte3 = (u8)(data >> 16);
  206. *((u8 *)priv->rx_buf) = byte3;
  207. priv->rx_buf += 1;
  208. break;
  209. case 4:
  210. /* Can not assume word aligned buffer */
  211. memcpy(priv->rx_buf, &data, size);
  212. priv->rx_buf += 4;
  213. break;
  214. default:
  215. /* This will never execute */
  216. break;
  217. }
  218. }
  219. priv->bytes_to_receive -= size;
  220. if (priv->bytes_to_receive < 0)
  221. priv->bytes_to_receive = 0;
  222. }
  223. /**
  224. * zynq_qspi_write_data - Copy data from TX buffer
  225. * @priv: Pointer to the zynq_qspi_priv structure
  226. * @data: Pointer to the 32 bit variable where data is to be copied
  227. * @size: Number of bytes to be copied from TX buffer to data
  228. */
  229. static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
  230. u32 *data, u8 size)
  231. {
  232. if (priv->tx_buf) {
  233. switch (size) {
  234. case 1:
  235. *data = *((u8 *)priv->tx_buf);
  236. priv->tx_buf += 1;
  237. *data |= 0xFFFFFF00;
  238. break;
  239. case 2:
  240. *data = *((u16 *)priv->tx_buf);
  241. priv->tx_buf += 2;
  242. *data |= 0xFFFF0000;
  243. break;
  244. case 3:
  245. *data = *((u16 *)priv->tx_buf);
  246. priv->tx_buf += 2;
  247. *data |= (*((u8 *)priv->tx_buf) << 16);
  248. priv->tx_buf += 1;
  249. *data |= 0xFF000000;
  250. break;
  251. case 4:
  252. /* Can not assume word aligned buffer */
  253. memcpy(data, priv->tx_buf, size);
  254. priv->tx_buf += 4;
  255. break;
  256. default:
  257. /* This will never execute */
  258. break;
  259. }
  260. } else {
  261. *data = 0;
  262. }
  263. debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
  264. *data, (u32)priv->tx_buf, size);
  265. priv->bytes_to_transfer -= size;
  266. if (priv->bytes_to_transfer < 0)
  267. priv->bytes_to_transfer = 0;
  268. }
  269. /**
  270. * zynq_qspi_chipselect - Select or deselect the chip select line
  271. * @priv: Pointer to the zynq_qspi_priv structure
  272. * @is_on: Select(1) or deselect (0) the chip select line
  273. */
  274. static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
  275. {
  276. u32 confr;
  277. struct zynq_qspi_regs *regs = priv->regs;
  278. confr = readl(&regs->cr);
  279. if (is_on) {
  280. /* Select the slave */
  281. confr &= ~ZYNQ_QSPI_CR_SS_MASK;
  282. confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
  283. ZYNQ_QSPI_CR_SS_MASK;
  284. } else
  285. /* Deselect the slave */
  286. confr |= ZYNQ_QSPI_CR_SS_MASK;
  287. writel(confr, &regs->cr);
  288. }
  289. /**
  290. * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
  291. * @priv: Pointer to the zynq_qspi_priv structure
  292. * @size: Number of bytes to be copied to fifo
  293. */
  294. static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
  295. {
  296. u32 data = 0;
  297. u32 fifocount = 0;
  298. unsigned len, offset;
  299. struct zynq_qspi_regs *regs = priv->regs;
  300. static const unsigned offsets[4] = {
  301. ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
  302. ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
  303. while ((fifocount < size) &&
  304. (priv->bytes_to_transfer > 0)) {
  305. if (priv->bytes_to_transfer >= 4) {
  306. if (priv->tx_buf) {
  307. memcpy(&data, priv->tx_buf, 4);
  308. priv->tx_buf += 4;
  309. } else {
  310. data = 0;
  311. }
  312. writel(data, &regs->txd0r);
  313. priv->bytes_to_transfer -= 4;
  314. fifocount++;
  315. } else {
  316. /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
  317. if (!(readl(&regs->isr)
  318. & ZYNQ_QSPI_IXR_TXOW_MASK) &&
  319. !priv->rx_buf)
  320. return;
  321. len = priv->bytes_to_transfer;
  322. zynq_qspi_write_data(priv, &data, len);
  323. offset = (priv->rx_buf) ? offsets[0] : offsets[len];
  324. writel(data, &regs->cr + (offset / 4));
  325. }
  326. }
  327. }
  328. /**
  329. * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
  330. * @priv: Pointer to the zynq_qspi structure
  331. *
  332. * This function handles TX empty and Mode Fault interrupts only.
  333. * On TX empty interrupt this function reads the received data from RX FIFO and
  334. * fills the TX FIFO if there is any data remaining to be transferred.
  335. * On Mode Fault interrupt this function indicates that transfer is completed,
  336. * the SPI subsystem will identify the error as the remaining bytes to be
  337. * transferred is non-zero.
  338. *
  339. * returns: 0 for poll timeout
  340. * 1 transfer operation complete
  341. */
  342. static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
  343. {
  344. struct zynq_qspi_regs *regs = priv->regs;
  345. u32 rxindex = 0;
  346. u32 rxcount;
  347. u32 status, timeout;
  348. /* Poll until any of the interrupt status bits are set */
  349. timeout = get_timer(0);
  350. do {
  351. status = readl(&regs->isr);
  352. } while ((status == 0) &&
  353. (get_timer(timeout) < ZYNQ_QSPI_WAIT));
  354. if (status == 0) {
  355. printf("zynq_qspi_irq_poll: Timeout!\n");
  356. return -ETIMEDOUT;
  357. }
  358. writel(status, &regs->isr);
  359. /* Disable all interrupts */
  360. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
  361. if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
  362. (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
  363. /*
  364. * This bit is set when Tx FIFO has < THRESHOLD entries. We have
  365. * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
  366. * is empty
  367. */
  368. rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
  369. rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
  370. while ((rxindex < rxcount) &&
  371. (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
  372. /* Read out the data from the RX FIFO */
  373. u32 data;
  374. data = readl(&regs->drxr);
  375. if (priv->bytes_to_receive >= 4) {
  376. if (priv->rx_buf) {
  377. memcpy(priv->rx_buf, &data, 4);
  378. priv->rx_buf += 4;
  379. }
  380. priv->bytes_to_receive -= 4;
  381. } else {
  382. zynq_qspi_read_data(priv, data,
  383. priv->bytes_to_receive);
  384. }
  385. rxindex++;
  386. }
  387. if (priv->bytes_to_transfer) {
  388. /* There is more data to send */
  389. zynq_qspi_fill_tx_fifo(priv,
  390. ZYNQ_QSPI_RXFIFO_THRESHOLD);
  391. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
  392. } else {
  393. /*
  394. * If transfer and receive is completed then only send
  395. * complete signal
  396. */
  397. if (!priv->bytes_to_receive) {
  398. /* return operation complete */
  399. writel(ZYNQ_QSPI_IXR_ALL_MASK,
  400. &regs->idr);
  401. return 1;
  402. }
  403. }
  404. }
  405. return 0;
  406. }
  407. /**
  408. * zynq_qspi_start_transfer - Initiates the QSPI transfer
  409. * @priv: Pointer to the zynq_qspi_priv structure
  410. *
  411. * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
  412. * transfer to be completed.
  413. *
  414. * returns: Number of bytes transferred in the last transfer
  415. */
  416. static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
  417. {
  418. u32 data = 0;
  419. struct zynq_qspi_regs *regs = priv->regs;
  420. debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
  421. (u32)priv, (u32)priv, priv->len);
  422. priv->bytes_to_transfer = priv->len;
  423. priv->bytes_to_receive = priv->len;
  424. if (priv->len < 4)
  425. zynq_qspi_fill_tx_fifo(priv, priv->len);
  426. else
  427. zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
  428. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
  429. /* wait for completion */
  430. do {
  431. data = zynq_qspi_irq_poll(priv);
  432. } while (data == 0);
  433. return (priv->len) - (priv->bytes_to_transfer);
  434. }
  435. static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
  436. {
  437. unsigned cs_change = 1;
  438. int status = 0;
  439. while (1) {
  440. /* Select the chip if required */
  441. if (cs_change)
  442. zynq_qspi_chipselect(priv, 1);
  443. cs_change = priv->cs_change;
  444. if (!priv->tx_buf && !priv->rx_buf && priv->len) {
  445. status = -1;
  446. break;
  447. }
  448. /* Request the transfer */
  449. if (priv->len) {
  450. status = zynq_qspi_start_transfer(priv);
  451. priv->is_inst = 0;
  452. }
  453. if (status != priv->len) {
  454. if (status > 0)
  455. status = -EMSGSIZE;
  456. debug("zynq_qspi_transfer:%d len:%d\n",
  457. status, priv->len);
  458. break;
  459. }
  460. status = 0;
  461. if (cs_change)
  462. /* Deselect the chip */
  463. zynq_qspi_chipselect(priv, 0);
  464. break;
  465. }
  466. return status;
  467. }
  468. static int zynq_qspi_claim_bus(struct udevice *dev)
  469. {
  470. struct udevice *bus = dev->parent;
  471. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  472. struct zynq_qspi_regs *regs = priv->regs;
  473. writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  474. return 0;
  475. }
  476. static int zynq_qspi_release_bus(struct udevice *dev)
  477. {
  478. struct udevice *bus = dev->parent;
  479. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  480. struct zynq_qspi_regs *regs = priv->regs;
  481. writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  482. return 0;
  483. }
  484. static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  485. const void *dout, void *din, unsigned long flags)
  486. {
  487. struct udevice *bus = dev->parent;
  488. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  489. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  490. priv->cs = slave_plat->cs;
  491. priv->tx_buf = dout;
  492. priv->rx_buf = din;
  493. priv->len = bitlen / 8;
  494. debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  495. dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
  496. /*
  497. * Festering sore.
  498. * Assume that the beginning of a transfer with bits to
  499. * transmit must contain a device command.
  500. */
  501. if (dout && flags & SPI_XFER_BEGIN)
  502. priv->is_inst = 1;
  503. else
  504. priv->is_inst = 0;
  505. if (flags & SPI_XFER_END)
  506. priv->cs_change = 1;
  507. else
  508. priv->cs_change = 0;
  509. zynq_qspi_transfer(priv);
  510. return 0;
  511. }
  512. static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
  513. {
  514. struct zynq_qspi_plat *plat = dev_get_plat(bus);
  515. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  516. struct zynq_qspi_regs *regs = priv->regs;
  517. uint32_t confr;
  518. u8 baud_rate_val = 0;
  519. if (speed > plat->frequency)
  520. speed = plat->frequency;
  521. /* Set the clock frequency */
  522. confr = readl(&regs->cr);
  523. if (speed == 0) {
  524. /* Set baudrate x8, if the freq is 0 */
  525. baud_rate_val = 0x2;
  526. } else if (plat->speed_hz != speed) {
  527. while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
  528. ((plat->frequency /
  529. (2 << baud_rate_val)) > speed))
  530. baud_rate_val++;
  531. plat->speed_hz = speed / (2 << baud_rate_val);
  532. }
  533. confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
  534. confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
  535. writel(confr, &regs->cr);
  536. priv->freq = speed;
  537. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  538. return 0;
  539. }
  540. static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
  541. {
  542. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  543. struct zynq_qspi_regs *regs = priv->regs;
  544. uint32_t confr;
  545. /* Set the SPI Clock phase and polarities */
  546. confr = readl(&regs->cr);
  547. confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
  548. if (mode & SPI_CPHA)
  549. confr |= ZYNQ_QSPI_CR_CPHA_MASK;
  550. if (mode & SPI_CPOL)
  551. confr |= ZYNQ_QSPI_CR_CPOL_MASK;
  552. writel(confr, &regs->cr);
  553. priv->mode = mode;
  554. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  555. return 0;
  556. }
  557. static const struct dm_spi_ops zynq_qspi_ops = {
  558. .claim_bus = zynq_qspi_claim_bus,
  559. .release_bus = zynq_qspi_release_bus,
  560. .xfer = zynq_qspi_xfer,
  561. .set_speed = zynq_qspi_set_speed,
  562. .set_mode = zynq_qspi_set_mode,
  563. };
  564. static const struct udevice_id zynq_qspi_ids[] = {
  565. { .compatible = "xlnx,zynq-qspi-1.0" },
  566. { }
  567. };
  568. U_BOOT_DRIVER(zynq_qspi) = {
  569. .name = "zynq_qspi",
  570. .id = UCLASS_SPI,
  571. .of_match = zynq_qspi_ids,
  572. .ops = &zynq_qspi_ops,
  573. .of_to_plat = zynq_qspi_of_to_plat,
  574. .plat_auto = sizeof(struct zynq_qspi_plat),
  575. .priv_auto = sizeof(struct zynq_qspi_priv),
  576. .probe = zynq_qspi_probe,
  577. };