uniphier_spi.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * uniphier_spi.c - Socionext UniPhier SPI driver
  4. * Copyright 2019 Socionext, Inc.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <time.h>
  11. #include <asm/global_data.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/bitfield.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <linux/io.h>
  17. #include <spi.h>
  18. #include <wait_bit.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define SSI_CTL 0x00
  21. #define SSI_CTL_EN BIT(0)
  22. #define SSI_CKS 0x04
  23. #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
  24. #define SSI_CKS_CKPHS BIT(14)
  25. #define SSI_CKS_CKINIT BIT(13)
  26. #define SSI_CKS_CKDLY BIT(12)
  27. #define SSI_TXWDS 0x08
  28. #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
  29. #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
  30. #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
  31. #define SSI_RXWDS 0x0c
  32. #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
  33. #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
  34. #define SSI_FPS 0x10
  35. #define SSI_FPS_FSPOL BIT(15)
  36. #define SSI_FPS_FSTRT BIT(14)
  37. #define SSI_SR 0x14
  38. #define SSI_SR_BUSY BIT(7)
  39. #define SSI_SR_TNF BIT(5)
  40. #define SSI_SR_RNE BIT(0)
  41. #define SSI_IE 0x18
  42. #define SSI_IC 0x1c
  43. #define SSI_IC_TCIC BIT(4)
  44. #define SSI_IC_RCIC BIT(3)
  45. #define SSI_IC_RORIC BIT(0)
  46. #define SSI_FC 0x20
  47. #define SSI_FC_TXFFL BIT(12)
  48. #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
  49. #define SSI_FC_RXFFL BIT(4)
  50. #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
  51. #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
  52. #define SSI_FIFO_DEPTH 8U
  53. #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
  54. #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
  55. #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
  56. struct uniphier_spi_plat {
  57. void __iomem *base;
  58. u32 frequency; /* input frequency */
  59. u32 speed_hz;
  60. uint deactivate_delay_us; /* Delay to wait after deactivate */
  61. uint activate_delay_us; /* Delay to wait after activate */
  62. };
  63. struct uniphier_spi_priv {
  64. void __iomem *base;
  65. u8 mode;
  66. u8 fifo_depth;
  67. u8 bits_per_word;
  68. ulong last_transaction_us; /* Time of last transaction end */
  69. };
  70. static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
  71. {
  72. u32 val;
  73. val = readl(priv->base + SSI_CTL);
  74. if (enable)
  75. val |= SSI_CTL_EN;
  76. else
  77. val &= ~SSI_CTL_EN;
  78. writel(val, priv->base + SSI_CTL);
  79. }
  80. static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
  81. {
  82. pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
  83. pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
  84. pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
  85. pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
  86. pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
  87. pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
  88. pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
  89. pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
  90. pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
  91. pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
  92. }
  93. static void spi_cs_activate(struct udevice *dev)
  94. {
  95. struct udevice *bus = dev->parent;
  96. struct uniphier_spi_plat *plat = dev_get_plat(bus);
  97. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  98. ulong delay_us; /* The delay completed so far */
  99. u32 val;
  100. /* If it's too soon to do another transaction, wait */
  101. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  102. delay_us = timer_get_us() - priv->last_transaction_us;
  103. if (delay_us < plat->deactivate_delay_us)
  104. udelay(plat->deactivate_delay_us - delay_us);
  105. }
  106. val = readl(priv->base + SSI_FPS);
  107. if (priv->mode & SPI_CS_HIGH)
  108. val |= SSI_FPS_FSPOL;
  109. else
  110. val &= ~SSI_FPS_FSPOL;
  111. writel(val, priv->base + SSI_FPS);
  112. if (plat->activate_delay_us)
  113. udelay(plat->activate_delay_us);
  114. }
  115. static void spi_cs_deactivate(struct udevice *dev)
  116. {
  117. struct udevice *bus = dev->parent;
  118. struct uniphier_spi_plat *plat = dev_get_plat(bus);
  119. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  120. u32 val;
  121. val = readl(priv->base + SSI_FPS);
  122. if (priv->mode & SPI_CS_HIGH)
  123. val &= ~SSI_FPS_FSPOL;
  124. else
  125. val |= SSI_FPS_FSPOL;
  126. writel(val, priv->base + SSI_FPS);
  127. /* Remember time of this transaction so we can honour the bus delay */
  128. if (plat->deactivate_delay_us)
  129. priv->last_transaction_us = timer_get_us();
  130. }
  131. static int uniphier_spi_claim_bus(struct udevice *dev)
  132. {
  133. struct udevice *bus = dev->parent;
  134. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  135. u32 val, size;
  136. uniphier_spi_enable(priv, false);
  137. /* disable interrupts */
  138. writel(0, priv->base + SSI_IE);
  139. /* bits_per_word */
  140. size = priv->bits_per_word;
  141. val = readl(priv->base + SSI_TXWDS);
  142. val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
  143. val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
  144. val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
  145. writel(val, priv->base + SSI_TXWDS);
  146. val = readl(priv->base + SSI_RXWDS);
  147. val &= ~SSI_RXWDS_DTLEN_MASK;
  148. val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
  149. writel(val, priv->base + SSI_RXWDS);
  150. /* reset FIFOs */
  151. val = SSI_FC_TXFFL | SSI_FC_RXFFL;
  152. writel(val, priv->base + SSI_FC);
  153. /* FIFO threthold */
  154. val = readl(priv->base + SSI_FC);
  155. val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
  156. val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
  157. val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
  158. writel(val, priv->base + SSI_FC);
  159. /* clear interrupts */
  160. writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
  161. priv->base + SSI_IC);
  162. uniphier_spi_enable(priv, true);
  163. return 0;
  164. }
  165. static int uniphier_spi_release_bus(struct udevice *dev)
  166. {
  167. struct udevice *bus = dev->parent;
  168. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  169. uniphier_spi_enable(priv, false);
  170. return 0;
  171. }
  172. static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
  173. const void *dout, void *din, unsigned long flags)
  174. {
  175. struct udevice *bus = dev->parent;
  176. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  177. const u8 *tx_buf = dout;
  178. u8 *rx_buf = din, buf;
  179. u32 len = bitlen / 8;
  180. u32 tx_len, rx_len;
  181. u32 ts, status;
  182. int ret = 0;
  183. if (bitlen % 8) {
  184. dev_err(dev, "Non byte aligned SPI transfer\n");
  185. return -EINVAL;
  186. }
  187. if (flags & SPI_XFER_BEGIN)
  188. spi_cs_activate(dev);
  189. uniphier_spi_enable(priv, true);
  190. ts = get_timer(0);
  191. tx_len = len;
  192. rx_len = len;
  193. uniphier_spi_regdump(priv);
  194. while (tx_len || rx_len) {
  195. ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
  196. SSI_REG_TIMEOUT * 1000, false);
  197. if (ret) {
  198. if (ret == -ETIMEDOUT)
  199. dev_err(dev, "access timeout\n");
  200. break;
  201. }
  202. status = readl(priv->base + SSI_SR);
  203. /* write the data into TX */
  204. if (tx_len && (status & SSI_SR_TNF)) {
  205. buf = tx_buf ? *tx_buf++ : 0;
  206. writel(buf, priv->base + SSI_XDR);
  207. tx_len--;
  208. }
  209. /* read the data from RX */
  210. if (rx_len && (status & SSI_SR_RNE)) {
  211. buf = readl(priv->base + SSI_XDR);
  212. if (rx_buf)
  213. *rx_buf++ = buf;
  214. rx_len--;
  215. }
  216. if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
  217. dev_err(dev, "transfer timeout\n");
  218. ret = -ETIMEDOUT;
  219. break;
  220. }
  221. }
  222. if (flags & SPI_XFER_END)
  223. spi_cs_deactivate(dev);
  224. uniphier_spi_enable(priv, false);
  225. return ret;
  226. }
  227. static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
  228. {
  229. struct uniphier_spi_plat *plat = dev_get_plat(bus);
  230. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  231. u32 val, ckdiv;
  232. if (speed > plat->frequency)
  233. speed = plat->frequency;
  234. /* baudrate */
  235. ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
  236. ckdiv = round_up(ckdiv, 2);
  237. val = readl(priv->base + SSI_CKS);
  238. val &= ~SSI_CKS_CKRAT_MASK;
  239. val |= ckdiv & SSI_CKS_CKRAT_MASK;
  240. writel(val, priv->base + SSI_CKS);
  241. return 0;
  242. }
  243. static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
  244. {
  245. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  246. u32 val1, val2;
  247. /*
  248. * clock setting
  249. * CKPHS capture timing. 0:rising edge, 1:falling edge
  250. * CKINIT clock initial level. 0:low, 1:high
  251. * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
  252. * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
  253. *
  254. * frame setting
  255. * FSPOL frame signal porarity. 0: low, 1: high
  256. * FSTRT start frame timing
  257. * 0: rising edge of clock, 1: falling edge of clock
  258. */
  259. val1 = readl(priv->base + SSI_CKS);
  260. val2 = readl(priv->base + SSI_FPS);
  261. switch (mode & (SPI_CPOL | SPI_CPHA)) {
  262. case SPI_MODE_0:
  263. /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
  264. val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
  265. val1 &= ~SSI_CKS_CKINIT;
  266. val2 &= ~SSI_FPS_FSTRT;
  267. break;
  268. case SPI_MODE_1:
  269. /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
  270. val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
  271. val2 |= SSI_FPS_FSTRT;
  272. break;
  273. case SPI_MODE_2:
  274. /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
  275. val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
  276. val1 &= ~SSI_CKS_CKPHS;
  277. val2 |= SSI_FPS_FSTRT;
  278. break;
  279. case SPI_MODE_3:
  280. /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
  281. val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
  282. val1 &= ~SSI_CKS_CKDLY;
  283. val2 &= ~SSI_FPS_FSTRT;
  284. break;
  285. }
  286. writel(val1, priv->base + SSI_CKS);
  287. writel(val2, priv->base + SSI_FPS);
  288. /* format */
  289. val1 = readl(priv->base + SSI_TXWDS);
  290. val2 = readl(priv->base + SSI_RXWDS);
  291. if (mode & SPI_LSB_FIRST) {
  292. val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
  293. val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
  294. }
  295. writel(val1, priv->base + SSI_TXWDS);
  296. writel(val2, priv->base + SSI_RXWDS);
  297. priv->mode = mode;
  298. return 0;
  299. }
  300. static int uniphier_spi_of_to_plat(struct udevice *bus)
  301. {
  302. struct uniphier_spi_plat *plat = dev_get_plat(bus);
  303. const void *blob = gd->fdt_blob;
  304. int node = dev_of_offset(bus);
  305. plat->base = dev_read_addr_ptr(bus);
  306. plat->frequency =
  307. fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
  308. plat->deactivate_delay_us =
  309. fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
  310. plat->activate_delay_us =
  311. fdtdec_get_int(blob, node, "spi-activate-delay", 0);
  312. plat->speed_hz = plat->frequency / 2;
  313. return 0;
  314. }
  315. static int uniphier_spi_probe(struct udevice *bus)
  316. {
  317. struct uniphier_spi_plat *plat = dev_get_plat(bus);
  318. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  319. priv->base = plat->base;
  320. priv->fifo_depth = SSI_FIFO_DEPTH;
  321. priv->bits_per_word = 8;
  322. return 0;
  323. }
  324. static const struct dm_spi_ops uniphier_spi_ops = {
  325. .claim_bus = uniphier_spi_claim_bus,
  326. .release_bus = uniphier_spi_release_bus,
  327. .xfer = uniphier_spi_xfer,
  328. .set_speed = uniphier_spi_set_speed,
  329. .set_mode = uniphier_spi_set_mode,
  330. };
  331. static const struct udevice_id uniphier_spi_ids[] = {
  332. { .compatible = "socionext,uniphier-scssi" },
  333. { /* Sentinel */ }
  334. };
  335. U_BOOT_DRIVER(uniphier_spi) = {
  336. .name = "uniphier_spi",
  337. .id = UCLASS_SPI,
  338. .of_match = uniphier_spi_ids,
  339. .ops = &uniphier_spi_ops,
  340. .of_to_plat = uniphier_spi_of_to_plat,
  341. .plat_auto = sizeof(struct uniphier_spi_plat),
  342. .priv_auto = sizeof(struct uniphier_spi_priv),
  343. .probe = uniphier_spi_probe,
  344. };