tegra114_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NVIDIA Tegra SPI controller (T114 and later)
  4. *
  5. * Copyright (c) 2010-2013 NVIDIA Corporation
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch-tegra/clk_rst.h>
  14. #include <spi.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include "tegra_spi.h"
  18. /* COMMAND1 */
  19. #define SPI_CMD1_GO BIT(31)
  20. #define SPI_CMD1_M_S BIT(30)
  21. #define SPI_CMD1_MODE_MASK GENMASK(1, 0)
  22. #define SPI_CMD1_MODE_SHIFT 28
  23. #define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
  24. #define SPI_CMD1_CS_SEL_SHIFT 26
  25. #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
  26. #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
  27. #define SPI_CMD1_CS_POL_INACTIVE1 BIT(23)
  28. #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
  29. #define SPI_CMD1_CS_SW_HW BIT(21)
  30. #define SPI_CMD1_CS_SW_VAL BIT(20)
  31. #define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
  32. #define SPI_CMD1_IDLE_SDA_SHIFT 18
  33. #define SPI_CMD1_BIDIR BIT(17)
  34. #define SPI_CMD1_LSBI_FE BIT(16)
  35. #define SPI_CMD1_LSBY_FE BIT(15)
  36. #define SPI_CMD1_BOTH_EN_BIT BIT(14)
  37. #define SPI_CMD1_BOTH_EN_BYTE BIT(13)
  38. #define SPI_CMD1_RX_EN BIT(12)
  39. #define SPI_CMD1_TX_EN BIT(11)
  40. #define SPI_CMD1_PACKED BIT(5)
  41. #define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
  42. #define SPI_CMD1_BIT_LEN_SHIFT 0
  43. /* COMMAND2 */
  44. #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
  45. #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
  46. #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
  47. #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
  48. /* TRANSFER STATUS */
  49. #define SPI_XFER_STS_RDY BIT(30)
  50. /* FIFO STATUS */
  51. #define SPI_FIFO_STS_CS_INACTIVE BIT(31)
  52. #define SPI_FIFO_STS_FRAME_END BIT(30)
  53. #define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
  54. #define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
  55. #define SPI_FIFO_STS_ERR BIT(8)
  56. #define SPI_FIFO_STS_TX_FIFO_OVF BIT(7)
  57. #define SPI_FIFO_STS_TX_FIFO_UNR BIT(6)
  58. #define SPI_FIFO_STS_RX_FIFO_OVF BIT(5)
  59. #define SPI_FIFO_STS_RX_FIFO_UNR BIT(4)
  60. #define SPI_FIFO_STS_TX_FIFO_FULL BIT(3)
  61. #define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
  62. #define SPI_FIFO_STS_RX_FIFO_FULL BIT(1)
  63. #define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
  64. #define SPI_TIMEOUT 1000
  65. #define TEGRA_SPI_MAX_FREQ 52000000
  66. struct spi_regs {
  67. u32 command1; /* 000:SPI_COMMAND1 register */
  68. u32 command2; /* 004:SPI_COMMAND2 register */
  69. u32 timing1; /* 008:SPI_CS_TIM1 register */
  70. u32 timing2; /* 00c:SPI_CS_TIM2 register */
  71. u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
  72. u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
  73. u32 tx_data; /* 018:SPI_TX_DATA register */
  74. u32 rx_data; /* 01c:SPI_RX_DATA register */
  75. u32 dma_ctl; /* 020:SPI_DMA_CTL register */
  76. u32 dma_blk; /* 024:SPI_DMA_BLK register */
  77. u32 rsvd[56]; /* 028-107 reserved */
  78. u32 tx_fifo; /* 108:SPI_FIFO1 register */
  79. u32 rsvd2[31]; /* 10c-187 reserved */
  80. u32 rx_fifo; /* 188:SPI_FIFO2 register */
  81. u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
  82. };
  83. struct tegra114_spi_priv {
  84. struct spi_regs *regs;
  85. unsigned int freq;
  86. unsigned int mode;
  87. int periph_id;
  88. int valid;
  89. int last_transaction_us;
  90. };
  91. static int tegra114_spi_of_to_plat(struct udevice *bus)
  92. {
  93. struct tegra_spi_plat *plat = dev_get_plat(bus);
  94. plat->base = dev_read_addr(bus);
  95. plat->periph_id = clock_decode_periph_id(bus);
  96. if (plat->periph_id == PERIPH_ID_NONE) {
  97. debug("%s: could not decode periph id %d\n", __func__,
  98. plat->periph_id);
  99. return -FDT_ERR_NOTFOUND;
  100. }
  101. /* Use 500KHz as a suitable default */
  102. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  103. 500000);
  104. plat->deactivate_delay_us = dev_read_u32_default(bus,
  105. "spi-deactivate-delay", 0);
  106. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  107. __func__, plat->base, plat->periph_id, plat->frequency,
  108. plat->deactivate_delay_us);
  109. return 0;
  110. }
  111. static int tegra114_spi_probe(struct udevice *bus)
  112. {
  113. struct tegra_spi_plat *plat = dev_get_plat(bus);
  114. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  115. struct spi_regs *regs;
  116. ulong rate;
  117. priv->regs = (struct spi_regs *)plat->base;
  118. regs = priv->regs;
  119. priv->last_transaction_us = timer_get_us();
  120. priv->freq = plat->frequency;
  121. priv->periph_id = plat->periph_id;
  122. /*
  123. * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
  124. * back to the oscillator if that is too fast.
  125. */
  126. rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  127. priv->freq);
  128. if (rate > priv->freq + 100000) {
  129. rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
  130. priv->freq);
  131. if (rate != priv->freq) {
  132. printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
  133. bus->name, priv->freq, rate);
  134. }
  135. }
  136. udelay(plat->deactivate_delay_us);
  137. /* Clear stale status here */
  138. setbits_le32(&regs->fifo_status,
  139. SPI_FIFO_STS_ERR |
  140. SPI_FIFO_STS_TX_FIFO_OVF |
  141. SPI_FIFO_STS_TX_FIFO_UNR |
  142. SPI_FIFO_STS_RX_FIFO_OVF |
  143. SPI_FIFO_STS_RX_FIFO_UNR |
  144. SPI_FIFO_STS_TX_FIFO_FULL |
  145. SPI_FIFO_STS_TX_FIFO_EMPTY |
  146. SPI_FIFO_STS_RX_FIFO_FULL |
  147. SPI_FIFO_STS_RX_FIFO_EMPTY);
  148. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  149. setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
  150. (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
  151. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  152. return 0;
  153. }
  154. /**
  155. * Activate the CS by driving it LOW
  156. *
  157. * @param slave Pointer to spi_slave to which controller has to
  158. * communicate with
  159. */
  160. static void spi_cs_activate(struct udevice *dev)
  161. {
  162. struct udevice *bus = dev->parent;
  163. struct tegra_spi_plat *pdata = dev_get_plat(bus);
  164. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  165. /* If it's too soon to do another transaction, wait */
  166. if (pdata->deactivate_delay_us &&
  167. priv->last_transaction_us) {
  168. ulong delay_us; /* The delay completed so far */
  169. delay_us = timer_get_us() - priv->last_transaction_us;
  170. if (delay_us < pdata->deactivate_delay_us)
  171. udelay(pdata->deactivate_delay_us - delay_us);
  172. }
  173. clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
  174. }
  175. /**
  176. * Deactivate the CS by driving it HIGH
  177. *
  178. * @param slave Pointer to spi_slave to which controller has to
  179. * communicate with
  180. */
  181. static void spi_cs_deactivate(struct udevice *dev)
  182. {
  183. struct udevice *bus = dev->parent;
  184. struct tegra_spi_plat *pdata = dev_get_plat(bus);
  185. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  186. setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
  187. /* Remember time of this transaction so we can honour the bus delay */
  188. if (pdata->deactivate_delay_us)
  189. priv->last_transaction_us = timer_get_us();
  190. debug("Deactivate CS, bus '%s'\n", bus->name);
  191. }
  192. static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
  193. const void *data_out, void *data_in,
  194. unsigned long flags)
  195. {
  196. struct udevice *bus = dev->parent;
  197. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  198. struct spi_regs *regs = priv->regs;
  199. u32 reg, tmpdout, tmpdin = 0;
  200. const u8 *dout = data_out;
  201. u8 *din = data_in;
  202. int num_bytes;
  203. int ret;
  204. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  205. __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
  206. if (bitlen % 8)
  207. return -1;
  208. num_bytes = bitlen / 8;
  209. ret = 0;
  210. if (flags & SPI_XFER_BEGIN)
  211. spi_cs_activate(dev);
  212. /* clear all error status bits */
  213. reg = readl(&regs->fifo_status);
  214. writel(reg, &regs->fifo_status);
  215. clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
  216. SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
  217. (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
  218. /* set xfer size to 1 block (32 bits) */
  219. writel(0, &regs->dma_blk);
  220. /* handle data in 32-bit chunks */
  221. while (num_bytes > 0) {
  222. int bytes;
  223. int tm, i;
  224. tmpdout = 0;
  225. bytes = (num_bytes > 4) ? 4 : num_bytes;
  226. if (dout != NULL) {
  227. for (i = 0; i < bytes; ++i)
  228. tmpdout = (tmpdout << 8) | dout[i];
  229. dout += bytes;
  230. }
  231. num_bytes -= bytes;
  232. /* clear ready bit */
  233. setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
  234. clrsetbits_le32(&regs->command1,
  235. SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
  236. (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
  237. writel(tmpdout, &regs->tx_fifo);
  238. setbits_le32(&regs->command1, SPI_CMD1_GO);
  239. /*
  240. * Wait for SPI transmit FIFO to empty, or to time out.
  241. * The RX FIFO status will be read and cleared last
  242. */
  243. for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
  244. u32 fifo_status, xfer_status;
  245. xfer_status = readl(&regs->xfer_status);
  246. if (!(xfer_status & SPI_XFER_STS_RDY))
  247. continue;
  248. fifo_status = readl(&regs->fifo_status);
  249. if (fifo_status & SPI_FIFO_STS_ERR) {
  250. debug("%s: got a fifo error: ", __func__);
  251. if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
  252. debug("tx FIFO overflow ");
  253. if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
  254. debug("tx FIFO underrun ");
  255. if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
  256. debug("rx FIFO overflow ");
  257. if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
  258. debug("rx FIFO underrun ");
  259. if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
  260. debug("tx FIFO full ");
  261. if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
  262. debug("tx FIFO empty ");
  263. if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
  264. debug("rx FIFO full ");
  265. if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
  266. debug("rx FIFO empty ");
  267. debug("\n");
  268. break;
  269. }
  270. if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
  271. tmpdin = readl(&regs->rx_fifo);
  272. /* swap bytes read in */
  273. if (din != NULL) {
  274. for (i = bytes - 1; i >= 0; --i) {
  275. din[i] = tmpdin & 0xff;
  276. tmpdin >>= 8;
  277. }
  278. din += bytes;
  279. }
  280. /* We can exit when we've had both RX and TX */
  281. break;
  282. }
  283. }
  284. if (tm >= SPI_TIMEOUT)
  285. ret = tm;
  286. /* clear ACK RDY, etc. bits */
  287. writel(readl(&regs->fifo_status), &regs->fifo_status);
  288. }
  289. if (flags & SPI_XFER_END)
  290. spi_cs_deactivate(dev);
  291. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  292. __func__, tmpdin, readl(&regs->fifo_status));
  293. if (ret) {
  294. printf("%s: timeout during SPI transfer, tm %d\n",
  295. __func__, ret);
  296. return -1;
  297. }
  298. return ret;
  299. }
  300. static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
  301. {
  302. struct tegra_spi_plat *plat = dev_get_plat(bus);
  303. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  304. if (speed > plat->frequency)
  305. speed = plat->frequency;
  306. priv->freq = speed;
  307. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  308. return 0;
  309. }
  310. static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
  311. {
  312. struct tegra114_spi_priv *priv = dev_get_priv(bus);
  313. priv->mode = mode;
  314. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  315. return 0;
  316. }
  317. static const struct dm_spi_ops tegra114_spi_ops = {
  318. .xfer = tegra114_spi_xfer,
  319. .set_speed = tegra114_spi_set_speed,
  320. .set_mode = tegra114_spi_set_mode,
  321. /*
  322. * cs_info is not needed, since we require all chip selects to be
  323. * in the device tree explicitly
  324. */
  325. };
  326. static const struct udevice_id tegra114_spi_ids[] = {
  327. { .compatible = "nvidia,tegra114-spi" },
  328. { }
  329. };
  330. U_BOOT_DRIVER(tegra114_spi) = {
  331. .name = "tegra114_spi",
  332. .id = UCLASS_SPI,
  333. .of_match = tegra114_spi_ids,
  334. .ops = &tegra114_spi_ops,
  335. .of_to_plat = tegra114_spi_of_to_plat,
  336. .plat_auto = sizeof(struct tegra_spi_plat),
  337. .priv_auto = sizeof(struct tegra114_spi_priv),
  338. .probe = tegra114_spi_probe,
  339. };