stm32_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. *
  5. * Driver for STMicroelectronics Serial peripheral interface (SPI)
  6. */
  7. #define LOG_CATEGORY UCLASS_SPI
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <reset.h>
  15. #include <spi.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <asm/io.h>
  20. #include <asm/gpio.h>
  21. #include <linux/bitfield.h>
  22. #include <linux/iopoll.h>
  23. /* STM32 SPI registers */
  24. #define STM32_SPI_CR1 0x00
  25. #define STM32_SPI_CR2 0x04
  26. #define STM32_SPI_CFG1 0x08
  27. #define STM32_SPI_CFG2 0x0C
  28. #define STM32_SPI_SR 0x14
  29. #define STM32_SPI_IFCR 0x18
  30. #define STM32_SPI_TXDR 0x20
  31. #define STM32_SPI_RXDR 0x30
  32. #define STM32_SPI_I2SCFGR 0x50
  33. /* STM32_SPI_CR1 bit fields */
  34. #define SPI_CR1_SPE BIT(0)
  35. #define SPI_CR1_MASRX BIT(8)
  36. #define SPI_CR1_CSTART BIT(9)
  37. #define SPI_CR1_CSUSP BIT(10)
  38. #define SPI_CR1_HDDIR BIT(11)
  39. #define SPI_CR1_SSI BIT(12)
  40. /* STM32_SPI_CR2 bit fields */
  41. #define SPI_CR2_TSIZE GENMASK(15, 0)
  42. /* STM32_SPI_CFG1 bit fields */
  43. #define SPI_CFG1_DSIZE GENMASK(4, 0)
  44. #define SPI_CFG1_DSIZE_MIN 3
  45. #define SPI_CFG1_FTHLV_SHIFT 5
  46. #define SPI_CFG1_FTHLV GENMASK(8, 5)
  47. #define SPI_CFG1_MBR_SHIFT 28
  48. #define SPI_CFG1_MBR GENMASK(30, 28)
  49. #define SPI_CFG1_MBR_MIN 0
  50. #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
  51. /* STM32_SPI_CFG2 bit fields */
  52. #define SPI_CFG2_COMM_SHIFT 17
  53. #define SPI_CFG2_COMM GENMASK(18, 17)
  54. #define SPI_CFG2_MASTER BIT(22)
  55. #define SPI_CFG2_LSBFRST BIT(23)
  56. #define SPI_CFG2_CPHA BIT(24)
  57. #define SPI_CFG2_CPOL BIT(25)
  58. #define SPI_CFG2_SSM BIT(26)
  59. #define SPI_CFG2_AFCNTR BIT(31)
  60. /* STM32_SPI_SR bit fields */
  61. #define SPI_SR_RXP BIT(0)
  62. #define SPI_SR_TXP BIT(1)
  63. #define SPI_SR_EOT BIT(3)
  64. #define SPI_SR_TXTF BIT(4)
  65. #define SPI_SR_OVR BIT(6)
  66. #define SPI_SR_SUSP BIT(11)
  67. #define SPI_SR_RXPLVL_SHIFT 13
  68. #define SPI_SR_RXPLVL GENMASK(14, 13)
  69. #define SPI_SR_RXWNE BIT(15)
  70. /* STM32_SPI_IFCR bit fields */
  71. #define SPI_IFCR_ALL GENMASK(11, 3)
  72. /* STM32_SPI_I2SCFGR bit fields */
  73. #define SPI_I2SCFGR_I2SMOD BIT(0)
  74. #define MAX_CS_COUNT 4
  75. /* SPI Master Baud Rate min/max divisor */
  76. #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
  77. #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
  78. #define STM32_SPI_TIMEOUT_US 100000
  79. /* SPI Communication mode */
  80. #define SPI_FULL_DUPLEX 0
  81. #define SPI_SIMPLEX_TX 1
  82. #define SPI_SIMPLEX_RX 2
  83. #define SPI_HALF_DUPLEX 3
  84. struct stm32_spi_priv {
  85. void __iomem *base;
  86. struct clk clk;
  87. struct reset_ctl rst_ctl;
  88. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  89. ulong bus_clk_rate;
  90. unsigned int fifo_size;
  91. unsigned int cur_bpw;
  92. unsigned int cur_hz;
  93. unsigned int cur_xferlen; /* current transfer length in bytes */
  94. unsigned int tx_len; /* number of data to be written in bytes */
  95. unsigned int rx_len; /* number of data to be read in bytes */
  96. const void *tx_buf; /* data to be written, or NULL */
  97. void *rx_buf; /* data to be read, or NULL */
  98. u32 cur_mode;
  99. bool cs_high;
  100. };
  101. static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
  102. {
  103. while ((priv->tx_len > 0) &&
  104. (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
  105. u32 offs = priv->cur_xferlen - priv->tx_len;
  106. if (priv->tx_len >= sizeof(u32) &&
  107. IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
  108. const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
  109. writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
  110. priv->tx_len -= sizeof(u32);
  111. } else if (priv->tx_len >= sizeof(u16) &&
  112. IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
  113. const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
  114. writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
  115. priv->tx_len -= sizeof(u16);
  116. } else {
  117. const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
  118. writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
  119. priv->tx_len -= sizeof(u8);
  120. }
  121. }
  122. log_debug("%d bytes left\n", priv->tx_len);
  123. }
  124. static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
  125. {
  126. u32 sr = readl(priv->base + STM32_SPI_SR);
  127. u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
  128. while ((priv->rx_len > 0) &&
  129. ((sr & SPI_SR_RXP) ||
  130. ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
  131. u32 offs = priv->cur_xferlen - priv->rx_len;
  132. if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
  133. (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
  134. u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
  135. *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
  136. priv->rx_len -= sizeof(u32);
  137. } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
  138. (priv->rx_len >= sizeof(u16) ||
  139. (!(sr & SPI_SR_RXWNE) &&
  140. (rxplvl >= 2 || priv->cur_bpw > 8)))) {
  141. u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
  142. *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
  143. priv->rx_len -= sizeof(u16);
  144. } else {
  145. u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
  146. *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
  147. priv->rx_len -= sizeof(u8);
  148. }
  149. sr = readl(priv->base + STM32_SPI_SR);
  150. rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
  151. }
  152. log_debug("%d bytes left\n", priv->rx_len);
  153. }
  154. static int stm32_spi_enable(struct stm32_spi_priv *priv)
  155. {
  156. log_debug("\n");
  157. /* Enable the SPI hardware */
  158. setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
  159. return 0;
  160. }
  161. static int stm32_spi_disable(struct stm32_spi_priv *priv)
  162. {
  163. log_debug("\n");
  164. /* Disable the SPI hardware */
  165. clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
  166. return 0;
  167. }
  168. static int stm32_spi_claim_bus(struct udevice *slave)
  169. {
  170. struct udevice *bus = dev_get_parent(slave);
  171. struct stm32_spi_priv *priv = dev_get_priv(bus);
  172. dev_dbg(slave, "\n");
  173. /* Enable the SPI hardware */
  174. return stm32_spi_enable(priv);
  175. }
  176. static int stm32_spi_release_bus(struct udevice *slave)
  177. {
  178. struct udevice *bus = dev_get_parent(slave);
  179. struct stm32_spi_priv *priv = dev_get_priv(bus);
  180. dev_dbg(slave, "\n");
  181. /* Disable the SPI hardware */
  182. return stm32_spi_disable(priv);
  183. }
  184. static void stm32_spi_stopxfer(struct udevice *dev)
  185. {
  186. struct stm32_spi_priv *priv = dev_get_priv(dev);
  187. u32 cr1, sr;
  188. int ret;
  189. dev_dbg(dev, "\n");
  190. cr1 = readl(priv->base + STM32_SPI_CR1);
  191. if (!(cr1 & SPI_CR1_SPE))
  192. return;
  193. /* Wait on EOT or suspend the flow */
  194. ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
  195. !(sr & SPI_SR_EOT), 100000);
  196. if (ret < 0) {
  197. if (cr1 & SPI_CR1_CSTART) {
  198. writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
  199. if (readl_poll_timeout(priv->base + STM32_SPI_SR,
  200. sr, !(sr & SPI_SR_SUSP),
  201. 100000) < 0)
  202. dev_err(dev, "Suspend request timeout\n");
  203. }
  204. }
  205. /* clear status flags */
  206. setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
  207. }
  208. static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
  209. {
  210. struct stm32_spi_priv *priv = dev_get_priv(dev);
  211. dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
  212. if (cs >= MAX_CS_COUNT)
  213. return -ENODEV;
  214. if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
  215. return -EINVAL;
  216. if (priv->cs_high)
  217. enable = !enable;
  218. return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
  219. }
  220. static int stm32_spi_set_mode(struct udevice *bus, uint mode)
  221. {
  222. struct stm32_spi_priv *priv = dev_get_priv(bus);
  223. u32 cfg2_clrb = 0, cfg2_setb = 0;
  224. dev_dbg(bus, "mode=%d\n", mode);
  225. if (mode & SPI_CPOL)
  226. cfg2_setb |= SPI_CFG2_CPOL;
  227. else
  228. cfg2_clrb |= SPI_CFG2_CPOL;
  229. if (mode & SPI_CPHA)
  230. cfg2_setb |= SPI_CFG2_CPHA;
  231. else
  232. cfg2_clrb |= SPI_CFG2_CPHA;
  233. if (mode & SPI_LSB_FIRST)
  234. cfg2_setb |= SPI_CFG2_LSBFRST;
  235. else
  236. cfg2_clrb |= SPI_CFG2_LSBFRST;
  237. if (cfg2_clrb || cfg2_setb)
  238. clrsetbits_le32(priv->base + STM32_SPI_CFG2,
  239. cfg2_clrb, cfg2_setb);
  240. if (mode & SPI_CS_HIGH)
  241. priv->cs_high = true;
  242. else
  243. priv->cs_high = false;
  244. return 0;
  245. }
  246. static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
  247. {
  248. struct stm32_spi_priv *priv = dev_get_priv(dev);
  249. u32 fthlv, half_fifo;
  250. /* data packet should not exceed 1/2 of fifo space */
  251. half_fifo = (priv->fifo_size / 2);
  252. /* data_packet should not exceed transfer length */
  253. fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
  254. /* align packet size with data registers access */
  255. fthlv -= (fthlv % 4);
  256. if (!fthlv)
  257. fthlv = 1;
  258. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
  259. (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
  260. return 0;
  261. }
  262. static int stm32_spi_set_speed(struct udevice *bus, uint hz)
  263. {
  264. struct stm32_spi_priv *priv = dev_get_priv(bus);
  265. u32 mbrdiv;
  266. long div;
  267. dev_dbg(bus, "hz=%d\n", hz);
  268. if (priv->cur_hz == hz)
  269. return 0;
  270. div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
  271. if (div < STM32_MBR_DIV_MIN ||
  272. div > STM32_MBR_DIV_MAX)
  273. return -EINVAL;
  274. /* Determine the first power of 2 greater than or equal to div */
  275. if (div & (div - 1))
  276. mbrdiv = fls(div);
  277. else
  278. mbrdiv = fls(div) - 1;
  279. if (!mbrdiv)
  280. return -EINVAL;
  281. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
  282. (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
  283. priv->cur_hz = hz;
  284. return 0;
  285. }
  286. static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
  287. const void *dout, void *din, unsigned long flags)
  288. {
  289. struct udevice *bus = dev_get_parent(slave);
  290. struct dm_spi_slave_plat *slave_plat;
  291. struct stm32_spi_priv *priv = dev_get_priv(bus);
  292. u32 sr;
  293. u32 ifcr = 0;
  294. u32 xferlen;
  295. u32 mode;
  296. int xfer_status = 0;
  297. xferlen = bitlen / 8;
  298. if (xferlen <= SPI_CR2_TSIZE)
  299. writel(xferlen, priv->base + STM32_SPI_CR2);
  300. else
  301. return -EMSGSIZE;
  302. priv->tx_buf = dout;
  303. priv->rx_buf = din;
  304. priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
  305. priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
  306. mode = SPI_FULL_DUPLEX;
  307. if (!priv->tx_buf)
  308. mode = SPI_SIMPLEX_RX;
  309. else if (!priv->rx_buf)
  310. mode = SPI_SIMPLEX_TX;
  311. if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
  312. priv->cur_mode = mode;
  313. priv->cur_xferlen = xferlen;
  314. /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
  315. stm32_spi_disable(priv);
  316. clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
  317. mode << SPI_CFG2_COMM_SHIFT);
  318. stm32_spi_set_fthlv(bus, xferlen);
  319. /* Enable the SPI hardware */
  320. stm32_spi_enable(priv);
  321. }
  322. dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
  323. priv->tx_len, priv->rx_len);
  324. slave_plat = dev_get_parent_plat(slave);
  325. if (flags & SPI_XFER_BEGIN)
  326. stm32_spi_set_cs(bus, slave_plat->cs, false);
  327. /* Be sure to have data in fifo before starting data transfer */
  328. if (priv->tx_buf)
  329. stm32_spi_write_txfifo(priv);
  330. setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
  331. while (1) {
  332. sr = readl(priv->base + STM32_SPI_SR);
  333. if (sr & SPI_SR_OVR) {
  334. dev_err(bus, "Overrun: RX data lost\n");
  335. xfer_status = -EIO;
  336. break;
  337. }
  338. if (sr & SPI_SR_SUSP) {
  339. dev_warn(bus, "System too slow is limiting data throughput\n");
  340. if (priv->rx_buf && priv->rx_len > 0)
  341. stm32_spi_read_rxfifo(priv);
  342. ifcr |= SPI_SR_SUSP;
  343. }
  344. if (sr & SPI_SR_TXTF)
  345. ifcr |= SPI_SR_TXTF;
  346. if (sr & SPI_SR_TXP)
  347. if (priv->tx_buf && priv->tx_len > 0)
  348. stm32_spi_write_txfifo(priv);
  349. if (sr & SPI_SR_RXP)
  350. if (priv->rx_buf && priv->rx_len > 0)
  351. stm32_spi_read_rxfifo(priv);
  352. if (sr & SPI_SR_EOT) {
  353. if (priv->rx_buf && priv->rx_len > 0)
  354. stm32_spi_read_rxfifo(priv);
  355. break;
  356. }
  357. writel(ifcr, priv->base + STM32_SPI_IFCR);
  358. }
  359. /* clear status flags */
  360. setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
  361. stm32_spi_stopxfer(bus);
  362. if (flags & SPI_XFER_END)
  363. stm32_spi_set_cs(bus, slave_plat->cs, true);
  364. return xfer_status;
  365. }
  366. static int stm32_spi_get_fifo_size(struct udevice *dev)
  367. {
  368. struct stm32_spi_priv *priv = dev_get_priv(dev);
  369. u32 count = 0;
  370. stm32_spi_enable(priv);
  371. while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
  372. writeb(++count, priv->base + STM32_SPI_TXDR);
  373. stm32_spi_disable(priv);
  374. dev_dbg(dev, "%d x 8-bit fifo size\n", count);
  375. return count;
  376. }
  377. static int stm32_spi_probe(struct udevice *dev)
  378. {
  379. struct stm32_spi_priv *priv = dev_get_priv(dev);
  380. unsigned long clk_rate;
  381. int ret;
  382. unsigned int i;
  383. priv->base = dev_remap_addr(dev);
  384. if (!priv->base)
  385. return -EINVAL;
  386. /* enable clock */
  387. ret = clk_get_by_index(dev, 0, &priv->clk);
  388. if (ret < 0)
  389. return ret;
  390. ret = clk_enable(&priv->clk);
  391. if (ret < 0)
  392. return ret;
  393. clk_rate = clk_get_rate(&priv->clk);
  394. if (!clk_rate) {
  395. ret = -EINVAL;
  396. goto clk_err;
  397. }
  398. priv->bus_clk_rate = clk_rate;
  399. /* perform reset */
  400. ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
  401. if (ret < 0)
  402. goto clk_err;
  403. reset_assert(&priv->rst_ctl);
  404. udelay(2);
  405. reset_deassert(&priv->rst_ctl);
  406. ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
  407. ARRAY_SIZE(priv->cs_gpios), 0);
  408. if (ret < 0) {
  409. dev_err(dev, "Can't get cs gpios: %d", ret);
  410. goto reset_err;
  411. }
  412. priv->fifo_size = stm32_spi_get_fifo_size(dev);
  413. priv->cur_mode = SPI_FULL_DUPLEX;
  414. priv->cur_xferlen = 0;
  415. priv->cur_bpw = SPI_DEFAULT_WORDLEN;
  416. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
  417. priv->cur_bpw - 1);
  418. for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
  419. if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
  420. continue;
  421. dm_gpio_set_dir_flags(&priv->cs_gpios[i],
  422. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  423. }
  424. /* Ensure I2SMOD bit is kept cleared */
  425. clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
  426. /*
  427. * - SS input value high
  428. * - transmitter half duplex direction
  429. * - automatic communication suspend when RX-Fifo is full
  430. */
  431. setbits_le32(priv->base + STM32_SPI_CR1,
  432. SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
  433. /*
  434. * - Set the master mode (default Motorola mode)
  435. * - Consider 1 master/n slaves configuration and
  436. * SS input value is determined by the SSI bit
  437. * - keep control of all associated GPIOs
  438. */
  439. setbits_le32(priv->base + STM32_SPI_CFG2,
  440. SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
  441. return 0;
  442. reset_err:
  443. reset_free(&priv->rst_ctl);
  444. clk_err:
  445. clk_disable(&priv->clk);
  446. clk_free(&priv->clk);
  447. return ret;
  448. };
  449. static int stm32_spi_remove(struct udevice *dev)
  450. {
  451. struct stm32_spi_priv *priv = dev_get_priv(dev);
  452. int ret;
  453. stm32_spi_stopxfer(dev);
  454. stm32_spi_disable(priv);
  455. ret = reset_assert(&priv->rst_ctl);
  456. if (ret < 0)
  457. return ret;
  458. reset_free(&priv->rst_ctl);
  459. ret = clk_disable(&priv->clk);
  460. if (ret < 0)
  461. return ret;
  462. clk_free(&priv->clk);
  463. return ret;
  464. };
  465. static const struct dm_spi_ops stm32_spi_ops = {
  466. .claim_bus = stm32_spi_claim_bus,
  467. .release_bus = stm32_spi_release_bus,
  468. .set_mode = stm32_spi_set_mode,
  469. .set_speed = stm32_spi_set_speed,
  470. .xfer = stm32_spi_xfer,
  471. };
  472. static const struct udevice_id stm32_spi_ids[] = {
  473. { .compatible = "st,stm32h7-spi", },
  474. { }
  475. };
  476. U_BOOT_DRIVER(stm32_spi) = {
  477. .name = "stm32_spi",
  478. .id = UCLASS_SPI,
  479. .of_match = stm32_spi_ids,
  480. .ops = &stm32_spi_ops,
  481. .priv_auto = sizeof(struct stm32_spi_priv),
  482. .probe = stm32_spi_probe,
  483. .remove = stm32_spi_remove,
  484. };