stm32_qspi.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. *
  5. * Michael Kurz, <michi.kurz@gmail.com>
  6. *
  7. * STM32 QSPI driver
  8. */
  9. #define LOG_CATEGORY UCLASS_SPI
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <reset.h>
  15. #include <spi.h>
  16. #include <spi-mem.h>
  17. #include <watchdog.h>
  18. #include <dm/device_compat.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/ioport.h>
  23. #include <linux/sizes.h>
  24. struct stm32_qspi_regs {
  25. u32 cr; /* 0x00 */
  26. u32 dcr; /* 0x04 */
  27. u32 sr; /* 0x08 */
  28. u32 fcr; /* 0x0C */
  29. u32 dlr; /* 0x10 */
  30. u32 ccr; /* 0x14 */
  31. u32 ar; /* 0x18 */
  32. u32 abr; /* 0x1C */
  33. u32 dr; /* 0x20 */
  34. u32 psmkr; /* 0x24 */
  35. u32 psmar; /* 0x28 */
  36. u32 pir; /* 0x2C */
  37. u32 lptr; /* 0x30 */
  38. };
  39. /*
  40. * QUADSPI control register
  41. */
  42. #define STM32_QSPI_CR_EN BIT(0)
  43. #define STM32_QSPI_CR_ABORT BIT(1)
  44. #define STM32_QSPI_CR_DMAEN BIT(2)
  45. #define STM32_QSPI_CR_TCEN BIT(3)
  46. #define STM32_QSPI_CR_SSHIFT BIT(4)
  47. #define STM32_QSPI_CR_DFM BIT(6)
  48. #define STM32_QSPI_CR_FSEL BIT(7)
  49. #define STM32_QSPI_CR_FTHRES_SHIFT 8
  50. #define STM32_QSPI_CR_TEIE BIT(16)
  51. #define STM32_QSPI_CR_TCIE BIT(17)
  52. #define STM32_QSPI_CR_FTIE BIT(18)
  53. #define STM32_QSPI_CR_SMIE BIT(19)
  54. #define STM32_QSPI_CR_TOIE BIT(20)
  55. #define STM32_QSPI_CR_APMS BIT(22)
  56. #define STM32_QSPI_CR_PMM BIT(23)
  57. #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
  58. #define STM32_QSPI_CR_PRESCALER_SHIFT 24
  59. /*
  60. * QUADSPI device configuration register
  61. */
  62. #define STM32_QSPI_DCR_CKMODE BIT(0)
  63. #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
  64. #define STM32_QSPI_DCR_CSHT_SHIFT 8
  65. #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
  66. #define STM32_QSPI_DCR_FSIZE_SHIFT 16
  67. /*
  68. * QUADSPI status register
  69. */
  70. #define STM32_QSPI_SR_TEF BIT(0)
  71. #define STM32_QSPI_SR_TCF BIT(1)
  72. #define STM32_QSPI_SR_FTF BIT(2)
  73. #define STM32_QSPI_SR_SMF BIT(3)
  74. #define STM32_QSPI_SR_TOF BIT(4)
  75. #define STM32_QSPI_SR_BUSY BIT(5)
  76. /*
  77. * QUADSPI flag clear register
  78. */
  79. #define STM32_QSPI_FCR_CTEF BIT(0)
  80. #define STM32_QSPI_FCR_CTCF BIT(1)
  81. #define STM32_QSPI_FCR_CSMF BIT(3)
  82. #define STM32_QSPI_FCR_CTOF BIT(4)
  83. /*
  84. * QUADSPI communication configuration register
  85. */
  86. #define STM32_QSPI_CCR_DDRM BIT(31)
  87. #define STM32_QSPI_CCR_DHHC BIT(30)
  88. #define STM32_QSPI_CCR_SIOO BIT(28)
  89. #define STM32_QSPI_CCR_FMODE_SHIFT 26
  90. #define STM32_QSPI_CCR_DMODE_SHIFT 24
  91. #define STM32_QSPI_CCR_DCYC_SHIFT 18
  92. #define STM32_QSPI_CCR_ABSIZE_SHIFT 16
  93. #define STM32_QSPI_CCR_ABMODE_SHIFT 14
  94. #define STM32_QSPI_CCR_ADSIZE_SHIFT 12
  95. #define STM32_QSPI_CCR_ADMODE_SHIFT 10
  96. #define STM32_QSPI_CCR_IMODE_SHIFT 8
  97. #define STM32_QSPI_CCR_IND_WRITE 0
  98. #define STM32_QSPI_CCR_IND_READ 1
  99. #define STM32_QSPI_CCR_MEM_MAP 3
  100. #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
  101. #define STM32_QSPI_MAX_CHIP 2
  102. #define STM32_QSPI_FIFO_TIMEOUT_US 30000
  103. #define STM32_QSPI_CMD_TIMEOUT_US 1000000
  104. #define STM32_BUSY_TIMEOUT_US 100000
  105. #define STM32_ABT_TIMEOUT_US 100000
  106. struct stm32_qspi_flash {
  107. u32 cr;
  108. u32 dcr;
  109. bool initialized;
  110. };
  111. struct stm32_qspi_priv {
  112. struct stm32_qspi_regs *regs;
  113. struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
  114. void __iomem *mm_base;
  115. resource_size_t mm_size;
  116. ulong clock_rate;
  117. int cs_used;
  118. };
  119. static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
  120. {
  121. u32 sr;
  122. int ret;
  123. ret = readl_poll_timeout(&priv->regs->sr, sr,
  124. !(sr & STM32_QSPI_SR_BUSY),
  125. STM32_BUSY_TIMEOUT_US);
  126. if (ret)
  127. log_err("busy timeout (stat:%#x)\n", sr);
  128. return ret;
  129. }
  130. static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
  131. const struct spi_mem_op *op)
  132. {
  133. u32 sr;
  134. int ret = 0;
  135. if (op->data.nbytes) {
  136. ret = readl_poll_timeout(&priv->regs->sr, sr,
  137. sr & STM32_QSPI_SR_TCF,
  138. STM32_QSPI_CMD_TIMEOUT_US);
  139. if (ret) {
  140. log_err("cmd timeout (stat:%#x)\n", sr);
  141. } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
  142. log_err("transfer error (stat:%#x)\n", sr);
  143. ret = -EIO;
  144. }
  145. /* clear flags */
  146. writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
  147. }
  148. if (!ret)
  149. ret = _stm32_qspi_wait_for_not_busy(priv);
  150. return ret;
  151. }
  152. static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
  153. {
  154. *val = readb(addr);
  155. WATCHDOG_RESET();
  156. }
  157. static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
  158. {
  159. writeb(*val, addr);
  160. }
  161. static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
  162. const struct spi_mem_op *op)
  163. {
  164. void (*fifo)(u8 *val, void __iomem *addr);
  165. u32 len = op->data.nbytes, sr;
  166. u8 *buf;
  167. int ret;
  168. if (op->data.dir == SPI_MEM_DATA_IN) {
  169. fifo = _stm32_qspi_read_fifo;
  170. buf = op->data.buf.in;
  171. } else {
  172. fifo = _stm32_qspi_write_fifo;
  173. buf = (u8 *)op->data.buf.out;
  174. }
  175. while (len--) {
  176. ret = readl_poll_timeout(&priv->regs->sr, sr,
  177. sr & STM32_QSPI_SR_FTF,
  178. STM32_QSPI_FIFO_TIMEOUT_US);
  179. if (ret) {
  180. log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
  181. return ret;
  182. }
  183. fifo(buf++, &priv->regs->dr);
  184. }
  185. return 0;
  186. }
  187. static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
  188. const struct spi_mem_op *op)
  189. {
  190. memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
  191. op->data.nbytes);
  192. return 0;
  193. }
  194. static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
  195. const struct spi_mem_op *op,
  196. u8 mode)
  197. {
  198. if (!op->data.nbytes)
  199. return 0;
  200. if (mode == STM32_QSPI_CCR_MEM_MAP)
  201. return stm32_qspi_mm(priv, op);
  202. return _stm32_qspi_poll(priv, op);
  203. }
  204. static int _stm32_qspi_get_mode(u8 buswidth)
  205. {
  206. if (buswidth == 4)
  207. return 3;
  208. return buswidth;
  209. }
  210. static int stm32_qspi_exec_op(struct spi_slave *slave,
  211. const struct spi_mem_op *op)
  212. {
  213. struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
  214. u32 cr, ccr, addr_max;
  215. u8 mode = STM32_QSPI_CCR_IND_WRITE;
  216. int timeout, ret;
  217. dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
  218. op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  219. op->dummy.buswidth, op->data.buswidth,
  220. op->addr.val, op->data.nbytes);
  221. ret = _stm32_qspi_wait_for_not_busy(priv);
  222. if (ret)
  223. return ret;
  224. addr_max = op->addr.val + op->data.nbytes + 1;
  225. if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
  226. if (addr_max < priv->mm_size && op->addr.buswidth)
  227. mode = STM32_QSPI_CCR_MEM_MAP;
  228. else
  229. mode = STM32_QSPI_CCR_IND_READ;
  230. }
  231. if (op->data.nbytes)
  232. writel(op->data.nbytes - 1, &priv->regs->dlr);
  233. ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
  234. ccr |= op->cmd.opcode;
  235. ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
  236. << STM32_QSPI_CCR_IMODE_SHIFT);
  237. if (op->addr.nbytes) {
  238. ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
  239. ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
  240. << STM32_QSPI_CCR_ADMODE_SHIFT);
  241. }
  242. if (op->dummy.buswidth && op->dummy.nbytes)
  243. ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
  244. << STM32_QSPI_CCR_DCYC_SHIFT);
  245. if (op->data.nbytes)
  246. ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
  247. << STM32_QSPI_CCR_DMODE_SHIFT);
  248. writel(ccr, &priv->regs->ccr);
  249. if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
  250. writel(op->addr.val, &priv->regs->ar);
  251. ret = _stm32_qspi_tx(priv, op, mode);
  252. /*
  253. * Abort in:
  254. * -error case
  255. * -read memory map: prefetching must be stopped if we read the last
  256. * byte of device (device size - fifo size). like device size is not
  257. * knows, the prefetching is always stop.
  258. */
  259. if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
  260. goto abort;
  261. /* Wait end of tx in indirect mode */
  262. ret = _stm32_qspi_wait_cmd(priv, op);
  263. if (ret)
  264. goto abort;
  265. return 0;
  266. abort:
  267. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
  268. /* Wait clear of abort bit by hw */
  269. timeout = readl_poll_timeout(&priv->regs->cr, cr,
  270. !(cr & STM32_QSPI_CR_ABORT),
  271. STM32_ABT_TIMEOUT_US);
  272. writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
  273. if (ret || timeout)
  274. dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
  275. return ret;
  276. }
  277. static int stm32_qspi_probe(struct udevice *bus)
  278. {
  279. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  280. struct resource res;
  281. struct clk clk;
  282. struct reset_ctl reset_ctl;
  283. int ret;
  284. ret = dev_read_resource_byname(bus, "qspi", &res);
  285. if (ret) {
  286. dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
  287. return ret;
  288. }
  289. priv->regs = (struct stm32_qspi_regs *)res.start;
  290. ret = dev_read_resource_byname(bus, "qspi_mm", &res);
  291. if (ret) {
  292. dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
  293. return ret;
  294. }
  295. priv->mm_base = (void __iomem *)res.start;
  296. priv->mm_size = resource_size(&res);
  297. if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
  298. return -EINVAL;
  299. dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
  300. priv->regs, priv->mm_base, priv->mm_size);
  301. ret = clk_get_by_index(bus, 0, &clk);
  302. if (ret < 0)
  303. return ret;
  304. ret = clk_enable(&clk);
  305. if (ret) {
  306. dev_err(bus, "failed to enable clock\n");
  307. return ret;
  308. }
  309. priv->clock_rate = clk_get_rate(&clk);
  310. if (!priv->clock_rate) {
  311. clk_disable(&clk);
  312. return -EINVAL;
  313. }
  314. ret = reset_get_by_index(bus, 0, &reset_ctl);
  315. if (ret) {
  316. if (ret != -ENOENT) {
  317. dev_err(bus, "failed to get reset\n");
  318. clk_disable(&clk);
  319. return ret;
  320. }
  321. } else {
  322. /* Reset QSPI controller */
  323. reset_assert(&reset_ctl);
  324. udelay(2);
  325. reset_deassert(&reset_ctl);
  326. }
  327. priv->cs_used = -1;
  328. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
  329. /* Set dcr fsize to max address */
  330. setbits_le32(&priv->regs->dcr,
  331. STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
  332. return 0;
  333. }
  334. static int stm32_qspi_claim_bus(struct udevice *dev)
  335. {
  336. struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
  337. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  338. int slave_cs = slave_plat->cs;
  339. if (slave_cs >= STM32_QSPI_MAX_CHIP)
  340. return -ENODEV;
  341. if (priv->cs_used != slave_cs) {
  342. struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
  343. priv->cs_used = slave_cs;
  344. if (flash->initialized) {
  345. /* Set the configuration: speed + cs */
  346. writel(flash->cr, &priv->regs->cr);
  347. writel(flash->dcr, &priv->regs->dcr);
  348. } else {
  349. /* Set chip select */
  350. clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
  351. priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
  352. /* Save the configuration: speed + cs */
  353. flash->cr = readl(&priv->regs->cr);
  354. flash->dcr = readl(&priv->regs->dcr);
  355. flash->initialized = true;
  356. }
  357. }
  358. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  359. return 0;
  360. }
  361. static int stm32_qspi_release_bus(struct udevice *dev)
  362. {
  363. struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
  364. clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  365. return 0;
  366. }
  367. static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
  368. {
  369. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  370. u32 qspi_clk = priv->clock_rate;
  371. u32 prescaler = 255;
  372. u32 csht;
  373. int ret;
  374. if (speed > 0) {
  375. prescaler = 0;
  376. if (qspi_clk) {
  377. prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
  378. if (prescaler > 255)
  379. prescaler = 255;
  380. }
  381. }
  382. csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
  383. csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
  384. ret = _stm32_qspi_wait_for_not_busy(priv);
  385. if (ret)
  386. return ret;
  387. clrsetbits_le32(&priv->regs->cr,
  388. STM32_QSPI_CR_PRESCALER_MASK <<
  389. STM32_QSPI_CR_PRESCALER_SHIFT,
  390. prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
  391. clrsetbits_le32(&priv->regs->dcr,
  392. STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
  393. csht << STM32_QSPI_DCR_CSHT_SHIFT);
  394. dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
  395. (qspi_clk / (prescaler + 1)));
  396. return 0;
  397. }
  398. static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
  399. {
  400. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  401. int ret;
  402. const char *str_rx, *str_tx;
  403. ret = _stm32_qspi_wait_for_not_busy(priv);
  404. if (ret)
  405. return ret;
  406. if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
  407. setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  408. else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
  409. clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  410. else
  411. return -ENODEV;
  412. if (mode & SPI_CS_HIGH)
  413. return -ENODEV;
  414. if (mode & SPI_RX_QUAD)
  415. str_rx = "quad";
  416. else if (mode & SPI_RX_DUAL)
  417. str_rx = "dual";
  418. else
  419. str_rx = "single";
  420. if (mode & SPI_TX_QUAD)
  421. str_tx = "quad";
  422. else if (mode & SPI_TX_DUAL)
  423. str_tx = "dual";
  424. else
  425. str_tx = "single";
  426. dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
  427. priv->regs, mode, str_rx, str_tx);
  428. return 0;
  429. }
  430. static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
  431. .exec_op = stm32_qspi_exec_op,
  432. };
  433. static const struct dm_spi_ops stm32_qspi_ops = {
  434. .claim_bus = stm32_qspi_claim_bus,
  435. .release_bus = stm32_qspi_release_bus,
  436. .set_speed = stm32_qspi_set_speed,
  437. .set_mode = stm32_qspi_set_mode,
  438. .mem_ops = &stm32_qspi_mem_ops,
  439. };
  440. static const struct udevice_id stm32_qspi_ids[] = {
  441. { .compatible = "st,stm32f469-qspi" },
  442. { }
  443. };
  444. U_BOOT_DRIVER(stm32_qspi) = {
  445. .name = "stm32_qspi",
  446. .id = UCLASS_SPI,
  447. .of_match = stm32_qspi_ids,
  448. .ops = &stm32_qspi_ops,
  449. .priv_auto = sizeof(struct stm32_qspi_priv),
  450. .probe = stm32_qspi_probe,
  451. };