spi-synquacer.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * spi-synquacer.c - Socionext Synquacer SPI driver
  4. * Copyright 2021 Linaro Ltd.
  5. * Copyright 2021 Socionext, Inc.
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <time.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/bitfield.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <linux/io.h>
  17. #include <spi.h>
  18. #include <wait_bit.h>
  19. #define MCTRL 0x0
  20. #define MEN 0
  21. #define CSEN 1
  22. #define IPCLK 3
  23. #define MES 4
  24. #define SYNCON 5
  25. #define PCC0 0x4
  26. #define PCC(n) (PCC0 + (n) * 4)
  27. #define RTM 3
  28. #define ACES 2
  29. #define SAFESYNC 16
  30. #define CPHA 0
  31. #define CPOL 1
  32. #define SSPOL 4
  33. #define SDIR 7
  34. #define SS2CD 5
  35. #define SENDIAN 8
  36. #define CDRS_SHIFT 9
  37. #define CDRS_MASK 0x7f
  38. #define TXF 0x14
  39. #define TXE 0x18
  40. #define TXC 0x1c
  41. #define RXF 0x20
  42. #define RXE 0x24
  43. #define RXC 0x28
  44. #define TFLETE 4
  45. #define RFMTE 5
  46. #define FAULTF 0x2c
  47. #define FAULTC 0x30
  48. #define DMCFG 0x34
  49. #define SSDC 1
  50. #define MSTARTEN 2
  51. #define DMSTART 0x38
  52. #define TRIGGER 0
  53. #define DMSTOP 8
  54. #define CS_MASK 3
  55. #define CS_SHIFT 16
  56. #define DATA_TXRX 0
  57. #define DATA_RX 1
  58. #define DATA_TX 2
  59. #define DATA_MASK 3
  60. #define DATA_SHIFT 26
  61. #define BUS_WIDTH 24
  62. #define DMBCC 0x3c
  63. #define DMSTATUS 0x40
  64. #define RX_DATA_MASK 0x1f
  65. #define RX_DATA_SHIFT 8
  66. #define TX_DATA_MASK 0x1f
  67. #define TX_DATA_SHIFT 16
  68. #define TXBITCNT 0x44
  69. #define FIFOCFG 0x4c
  70. #define BPW_MASK 0x3
  71. #define BPW_SHIFT 8
  72. #define RX_FLUSH 11
  73. #define TX_FLUSH 12
  74. #define RX_TRSHLD_MASK 0xf
  75. #define RX_TRSHLD_SHIFT 0
  76. #define TX_TRSHLD_MASK 0xf
  77. #define TX_TRSHLD_SHIFT 4
  78. #define TXFIFO 0x50
  79. #define RXFIFO 0x90
  80. #define MID 0xfc
  81. #define FIFO_DEPTH 16
  82. #define TX_TRSHLD 4
  83. #define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
  84. #define TXBIT 1
  85. #define RXBIT 2
  86. DECLARE_GLOBAL_DATA_PTR;
  87. struct synquacer_spi_plat {
  88. void __iomem *base;
  89. bool aces, rtm;
  90. };
  91. struct synquacer_spi_priv {
  92. void __iomem *base;
  93. bool aces, rtm;
  94. int speed, cs, mode, rwflag;
  95. void *rx_buf;
  96. const void *tx_buf;
  97. unsigned int tx_words, rx_words;
  98. };
  99. static void read_fifo(struct synquacer_spi_priv *priv)
  100. {
  101. u32 len = readl(priv->base + DMSTATUS);
  102. u8 *buf = priv->rx_buf;
  103. int i;
  104. len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
  105. len = min_t(unsigned int, len, priv->rx_words);
  106. for (i = 0; i < len; i++)
  107. *buf++ = readb(priv->base + RXFIFO);
  108. priv->rx_buf = buf;
  109. priv->rx_words -= len;
  110. }
  111. static void write_fifo(struct synquacer_spi_priv *priv)
  112. {
  113. u32 len = readl(priv->base + DMSTATUS);
  114. const u8 *buf = priv->tx_buf;
  115. int i;
  116. len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
  117. len = min_t(unsigned int, FIFO_DEPTH - len, priv->tx_words);
  118. for (i = 0; i < len; i++)
  119. writeb(*buf++, priv->base + TXFIFO);
  120. priv->tx_buf = buf;
  121. priv->tx_words -= len;
  122. }
  123. static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active)
  124. {
  125. u32 val;
  126. val = readl(priv->base + DMSTART);
  127. val &= ~(CS_MASK << CS_SHIFT);
  128. val |= priv->cs << CS_SHIFT;
  129. if (active) {
  130. writel(val, priv->base + DMSTART);
  131. val = readl(priv->base + DMSTART);
  132. val &= ~BIT(DMSTOP);
  133. writel(val, priv->base + DMSTART);
  134. } else {
  135. val |= BIT(DMSTOP);
  136. writel(val, priv->base + DMSTART);
  137. if (priv->rx_buf) {
  138. u32 buf[16];
  139. priv->rx_buf = buf;
  140. priv->rx_words = 16;
  141. read_fifo(priv);
  142. }
  143. }
  144. }
  145. static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
  146. {
  147. struct udevice *bus = dev->parent;
  148. struct synquacer_spi_priv *priv = dev_get_priv(bus);
  149. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  150. u32 val, div, bus_width;
  151. int rwflag;
  152. rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
  153. /* if nothing to do */
  154. if (slave_plat->mode == priv->mode &&
  155. rwflag == priv->rwflag &&
  156. slave_plat->cs == priv->cs &&
  157. slave_plat->max_hz == priv->speed)
  158. return;
  159. priv->rwflag = rwflag;
  160. priv->cs = slave_plat->cs;
  161. priv->mode = slave_plat->mode;
  162. priv->speed = slave_plat->max_hz;
  163. if (priv->mode & SPI_TX_BYTE)
  164. bus_width = 1;
  165. else if (priv->mode & SPI_TX_DUAL)
  166. bus_width = 2;
  167. else if (priv->mode & SPI_TX_QUAD)
  168. bus_width = 4;
  169. else if (priv->mode & SPI_TX_OCTAL)
  170. bus_width = 8;
  171. div = DIV_ROUND_UP(125000000, priv->speed);
  172. val = readl(priv->base + PCC(priv->cs));
  173. val &= ~BIT(RTM);
  174. val &= ~BIT(ACES);
  175. val &= ~BIT(SAFESYNC);
  176. if ((priv->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3)
  177. val |= BIT(SAFESYNC);
  178. if ((priv->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6)
  179. val |= BIT(SAFESYNC);
  180. if (priv->mode & SPI_CPHA)
  181. val |= BIT(CPHA);
  182. else
  183. val &= ~BIT(CPHA);
  184. if (priv->mode & SPI_CPOL)
  185. val |= BIT(CPOL);
  186. else
  187. val &= ~BIT(CPOL);
  188. if (priv->mode & SPI_CS_HIGH)
  189. val |= BIT(SSPOL);
  190. else
  191. val &= ~BIT(SSPOL);
  192. if (priv->mode & SPI_LSB_FIRST)
  193. val |= BIT(SDIR);
  194. else
  195. val &= ~BIT(SDIR);
  196. if (priv->aces)
  197. val |= BIT(ACES);
  198. if (priv->rtm)
  199. val |= BIT(RTM);
  200. val |= (3 << SS2CD);
  201. val |= BIT(SENDIAN);
  202. val &= ~(CDRS_MASK << CDRS_SHIFT);
  203. val |= ((div >> 1) << CDRS_SHIFT);
  204. writel(val, priv->base + PCC(priv->cs));
  205. val = readl(priv->base + FIFOCFG);
  206. val &= ~(BPW_MASK << BPW_SHIFT);
  207. val |= (0 << BPW_SHIFT);
  208. writel(val, priv->base + FIFOCFG);
  209. val = readl(priv->base + DMSTART);
  210. val &= ~(DATA_MASK << DATA_SHIFT);
  211. if (tx && rx)
  212. val |= (DATA_TXRX << DATA_SHIFT);
  213. else if (rx)
  214. val |= (DATA_RX << DATA_SHIFT);
  215. else
  216. val |= (DATA_TX << DATA_SHIFT);
  217. val &= ~(3 << BUS_WIDTH);
  218. val |= ((bus_width >> 1) << BUS_WIDTH);
  219. writel(val, priv->base + DMSTART);
  220. }
  221. static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
  222. const void *tx_buf, void *rx_buf,
  223. unsigned long flags)
  224. {
  225. struct udevice *bus = dev->parent;
  226. struct synquacer_spi_priv *priv = dev_get_priv(bus);
  227. u32 val, words, busy;
  228. val = readl(priv->base + FIFOCFG);
  229. val |= (1 << RX_FLUSH);
  230. val |= (1 << TX_FLUSH);
  231. writel(val, priv->base + FIFOCFG);
  232. synquacer_spi_config(dev, rx_buf, tx_buf);
  233. priv->tx_buf = tx_buf;
  234. priv->rx_buf = rx_buf;
  235. words = bitlen / 8;
  236. if (tx_buf) {
  237. busy |= BIT(TXBIT);
  238. priv->tx_words = words;
  239. } else {
  240. busy &= ~BIT(TXBIT);
  241. priv->tx_words = 0;
  242. }
  243. if (rx_buf) {
  244. busy |= BIT(RXBIT);
  245. priv->rx_words = words;
  246. } else {
  247. busy &= ~BIT(RXBIT);
  248. priv->rx_words = 0;
  249. }
  250. if (flags & SPI_XFER_BEGIN)
  251. synquacer_cs_set(priv, true);
  252. if (tx_buf)
  253. write_fifo(priv);
  254. if (rx_buf) {
  255. val = readl(priv->base + FIFOCFG);
  256. val &= ~(RX_TRSHLD_MASK << RX_TRSHLD_SHIFT);
  257. val |= ((priv->rx_words > FIFO_DEPTH ?
  258. RX_TRSHLD : priv->rx_words) << RX_TRSHLD_SHIFT);
  259. writel(val, priv->base + FIFOCFG);
  260. }
  261. writel(~0, priv->base + TXC);
  262. writel(~0, priv->base + RXC);
  263. /* Trigger */
  264. val = readl(priv->base + DMSTART);
  265. val |= BIT(TRIGGER);
  266. writel(val, priv->base + DMSTART);
  267. while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
  268. if (priv->rx_words)
  269. read_fifo(priv);
  270. else
  271. busy &= ~BIT(RXBIT);
  272. if (priv->tx_words) {
  273. write_fifo(priv);
  274. } else {
  275. u32 len;
  276. do { /* wait for shifter to empty out */
  277. cpu_relax();
  278. len = readl(priv->base + DMSTATUS);
  279. len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
  280. } while (tx_buf && len);
  281. busy &= ~BIT(TXBIT);
  282. }
  283. }
  284. if (flags & SPI_XFER_END)
  285. synquacer_cs_set(priv, false);
  286. return 0;
  287. }
  288. static int synquacer_spi_set_speed(struct udevice *bus, uint speed)
  289. {
  290. return 0;
  291. }
  292. static int synquacer_spi_set_mode(struct udevice *bus, uint mode)
  293. {
  294. return 0;
  295. }
  296. static int synquacer_spi_claim_bus(struct udevice *dev)
  297. {
  298. return 0;
  299. }
  300. static int synquacer_spi_release_bus(struct udevice *dev)
  301. {
  302. return 0;
  303. }
  304. static void synquacer_spi_disable_module(struct synquacer_spi_priv *priv)
  305. {
  306. writel(0, priv->base + MCTRL);
  307. while (readl(priv->base + MCTRL) & BIT(MES))
  308. cpu_relax();
  309. }
  310. static void synquacer_spi_init(struct synquacer_spi_priv *priv)
  311. {
  312. u32 val;
  313. synquacer_spi_disable_module(priv);
  314. writel(0, priv->base + TXE);
  315. writel(0, priv->base + RXE);
  316. val = readl(priv->base + TXF);
  317. writel(val, priv->base + TXC);
  318. val = readl(priv->base + RXF);
  319. writel(val, priv->base + RXC);
  320. val = readl(priv->base + FAULTF);
  321. writel(val, priv->base + FAULTC);
  322. val = readl(priv->base + DMCFG);
  323. val &= ~BIT(SSDC);
  324. val &= ~BIT(MSTARTEN);
  325. writel(val, priv->base + DMCFG);
  326. /* Enable module with direct mode */
  327. val = readl(priv->base + MCTRL);
  328. val &= ~BIT(IPCLK);
  329. val &= ~BIT(CSEN);
  330. val |= BIT(MEN);
  331. val |= BIT(SYNCON);
  332. writel(val, priv->base + MCTRL);
  333. }
  334. static void synquacer_spi_exit(struct synquacer_spi_priv *priv)
  335. {
  336. u32 val;
  337. synquacer_spi_disable_module(priv);
  338. /* Enable module with command sequence mode */
  339. val = readl(priv->base + MCTRL);
  340. val &= ~BIT(IPCLK);
  341. val |= BIT(CSEN);
  342. val |= BIT(MEN);
  343. val |= BIT(SYNCON);
  344. writel(val, priv->base + MCTRL);
  345. while (!(readl(priv->base + MCTRL) & BIT(MES)))
  346. cpu_relax();
  347. }
  348. static int synquacer_spi_probe(struct udevice *bus)
  349. {
  350. struct synquacer_spi_plat *plat = dev_get_plat(bus);
  351. struct synquacer_spi_priv *priv = dev_get_priv(bus);
  352. priv->base = plat->base;
  353. priv->aces = plat->aces;
  354. priv->rtm = plat->rtm;
  355. synquacer_spi_init(priv);
  356. return 0;
  357. }
  358. static int synquacer_spi_remove(struct udevice *bus)
  359. {
  360. struct synquacer_spi_priv *priv = dev_get_priv(bus);
  361. synquacer_spi_exit(priv);
  362. return 0;
  363. }
  364. static int synquacer_spi_of_to_plat(struct udevice *bus)
  365. {
  366. struct synquacer_spi_plat *plat = dev_get_plat(bus);
  367. struct clk clk;
  368. plat->base = dev_read_addr_ptr(bus);
  369. plat->aces = dev_read_bool(bus, "socionext,set-aces");
  370. plat->rtm = dev_read_bool(bus, "socionext,use-rtm");
  371. clk_get_by_name(bus, "iHCLK", &clk);
  372. clk_enable(&clk);
  373. return 0;
  374. }
  375. static const struct dm_spi_ops synquacer_spi_ops = {
  376. .claim_bus = synquacer_spi_claim_bus,
  377. .release_bus = synquacer_spi_release_bus,
  378. .xfer = synquacer_spi_xfer,
  379. .set_speed = synquacer_spi_set_speed,
  380. .set_mode = synquacer_spi_set_mode,
  381. };
  382. static const struct udevice_id synquacer_spi_ids[] = {
  383. { .compatible = "socionext,synquacer-spi" },
  384. { /* Sentinel */ }
  385. };
  386. U_BOOT_DRIVER(synquacer_spi) = {
  387. .name = "synquacer_spi",
  388. .id = UCLASS_SPI,
  389. .of_match = synquacer_spi_ids,
  390. .ops = &synquacer_spi_ops,
  391. .of_to_plat = synquacer_spi_of_to_plat,
  392. .plat_auto = sizeof(struct synquacer_spi_plat),
  393. .priv_auto = sizeof(struct synquacer_spi_priv),
  394. .probe = synquacer_spi_probe,
  395. .flags = DM_FLAG_OS_PREPARE,
  396. .remove = synquacer_spi_remove,
  397. };