spi-sunxi.c 15 KB

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  1. /*
  2. * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
  3. * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
  4. * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
  5. *
  6. * (C) Copyright 2017 Olimex Ltd..
  7. * Stefan Mavrodiev <stefan@olimex.com>
  8. *
  9. * Based on linux spi driver. Original copyright follows:
  10. * linux/drivers/spi/spi-sun4i.c
  11. *
  12. * Copyright (C) 2012 - 2014 Allwinner Tech
  13. * Pan Nan <pannan@allwinnertech.com>
  14. *
  15. * Copyright (C) 2014 Maxime Ripard
  16. * Maxime Ripard <maxime.ripard@free-electrons.com>
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. */
  20. #include <common.h>
  21. #include <clk.h>
  22. #include <dm.h>
  23. #include <log.h>
  24. #include <spi.h>
  25. #include <errno.h>
  26. #include <fdt_support.h>
  27. #include <reset.h>
  28. #include <wait_bit.h>
  29. #include <asm/global_data.h>
  30. #include <dm/device_compat.h>
  31. #include <linux/bitops.h>
  32. #include <asm/bitops.h>
  33. #include <asm/gpio.h>
  34. #include <asm/io.h>
  35. #include <linux/iopoll.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. /* sun4i spi registers */
  38. #define SUN4I_RXDATA_REG 0x00
  39. #define SUN4I_TXDATA_REG 0x04
  40. #define SUN4I_CTL_REG 0x08
  41. #define SUN4I_CLK_CTL_REG 0x1c
  42. #define SUN4I_BURST_CNT_REG 0x20
  43. #define SUN4I_XMIT_CNT_REG 0x24
  44. #define SUN4I_FIFO_STA_REG 0x28
  45. /* sun6i spi registers */
  46. #define SUN6I_GBL_CTL_REG 0x04
  47. #define SUN6I_TFR_CTL_REG 0x08
  48. #define SUN6I_FIFO_CTL_REG 0x18
  49. #define SUN6I_FIFO_STA_REG 0x1c
  50. #define SUN6I_CLK_CTL_REG 0x24
  51. #define SUN6I_BURST_CNT_REG 0x30
  52. #define SUN6I_XMIT_CNT_REG 0x34
  53. #define SUN6I_BURST_CTL_REG 0x38
  54. #define SUN6I_TXDATA_REG 0x200
  55. #define SUN6I_RXDATA_REG 0x300
  56. /* sun spi bits */
  57. #define SUN4I_CTL_ENABLE BIT(0)
  58. #define SUN4I_CTL_MASTER BIT(1)
  59. #define SUN4I_CLK_CTL_CDR2_MASK 0xff
  60. #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  61. #define SUN4I_CLK_CTL_CDR1_MASK 0xf
  62. #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  63. #define SUN4I_CLK_CTL_DRS BIT(12)
  64. #define SUN4I_MAX_XFER_SIZE 0xffffff
  65. #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  66. #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  67. #define SUN4I_FIFO_STA_RF_CNT_BITS 0
  68. #define SUN4I_SPI_MAX_RATE 24000000
  69. #define SUN4I_SPI_MIN_RATE 3000
  70. #define SUN4I_SPI_DEFAULT_RATE 1000000
  71. #define SUN4I_SPI_TIMEOUT_US 1000000
  72. #define SPI_REG(priv, reg) ((priv)->base + \
  73. (priv)->variant->regs[reg])
  74. #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
  75. #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
  76. SPI_BIT(priv, SPI_TCR_CS_MASK))
  77. /* sun spi register set */
  78. enum sun4i_spi_regs {
  79. SPI_GCR,
  80. SPI_TCR,
  81. SPI_FCR,
  82. SPI_FSR,
  83. SPI_CCR,
  84. SPI_BC,
  85. SPI_TC,
  86. SPI_BCTL,
  87. SPI_TXD,
  88. SPI_RXD,
  89. };
  90. /* sun spi register bits */
  91. enum sun4i_spi_bits {
  92. SPI_GCR_TP,
  93. SPI_GCR_SRST,
  94. SPI_TCR_CPHA,
  95. SPI_TCR_CPOL,
  96. SPI_TCR_CS_ACTIVE_LOW,
  97. SPI_TCR_CS_SEL,
  98. SPI_TCR_CS_MASK,
  99. SPI_TCR_XCH,
  100. SPI_TCR_CS_MANUAL,
  101. SPI_TCR_CS_LEVEL,
  102. SPI_FCR_TF_RST,
  103. SPI_FCR_RF_RST,
  104. SPI_FSR_RF_CNT_MASK,
  105. };
  106. struct sun4i_spi_variant {
  107. const unsigned long *regs;
  108. const u32 *bits;
  109. u32 fifo_depth;
  110. bool has_soft_reset;
  111. bool has_burst_ctl;
  112. };
  113. struct sun4i_spi_plat {
  114. struct sun4i_spi_variant *variant;
  115. u32 base;
  116. u32 max_hz;
  117. };
  118. struct sun4i_spi_priv {
  119. struct sun4i_spi_variant *variant;
  120. struct clk clk_ahb, clk_mod;
  121. struct reset_ctl reset;
  122. u32 base;
  123. u32 freq;
  124. u32 mode;
  125. const u8 *tx_buf;
  126. u8 *rx_buf;
  127. };
  128. static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
  129. {
  130. u8 byte;
  131. while (len--) {
  132. byte = readb(SPI_REG(priv, SPI_RXD));
  133. if (priv->rx_buf)
  134. *priv->rx_buf++ = byte;
  135. }
  136. }
  137. static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
  138. {
  139. u8 byte;
  140. while (len--) {
  141. byte = priv->tx_buf ? *priv->tx_buf++ : 0;
  142. writeb(byte, SPI_REG(priv, SPI_TXD));
  143. }
  144. }
  145. static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
  146. {
  147. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  148. u32 reg;
  149. reg = readl(SPI_REG(priv, SPI_TCR));
  150. reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
  151. reg |= SPI_CS(priv, cs);
  152. if (enable)
  153. reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
  154. else
  155. reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
  156. writel(reg, SPI_REG(priv, SPI_TCR));
  157. }
  158. static int sun4i_spi_parse_pins(struct udevice *dev)
  159. {
  160. const void *fdt = gd->fdt_blob;
  161. const char *pin_name;
  162. const fdt32_t *list;
  163. u32 phandle;
  164. int drive, pull = 0, pin, i;
  165. int offset;
  166. int size;
  167. list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
  168. if (!list) {
  169. printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
  170. return -EINVAL;
  171. }
  172. while (size) {
  173. phandle = fdt32_to_cpu(*list++);
  174. size -= sizeof(*list);
  175. offset = fdt_node_offset_by_phandle(fdt, phandle);
  176. if (offset < 0)
  177. return offset;
  178. drive = fdt_getprop_u32_default_node(fdt, offset, 0,
  179. "drive-strength", 0);
  180. if (drive) {
  181. if (drive <= 10)
  182. drive = 0;
  183. else if (drive <= 20)
  184. drive = 1;
  185. else if (drive <= 30)
  186. drive = 2;
  187. else
  188. drive = 3;
  189. } else {
  190. drive = fdt_getprop_u32_default_node(fdt, offset, 0,
  191. "allwinner,drive",
  192. 0);
  193. drive = min(drive, 3);
  194. }
  195. if (fdt_get_property(fdt, offset, "bias-disable", NULL))
  196. pull = 0;
  197. else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
  198. pull = 1;
  199. else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
  200. pull = 2;
  201. else
  202. pull = fdt_getprop_u32_default_node(fdt, offset, 0,
  203. "allwinner,pull",
  204. 0);
  205. pull = min(pull, 2);
  206. for (i = 0; ; i++) {
  207. pin_name = fdt_stringlist_get(fdt, offset,
  208. "pins", i, NULL);
  209. if (!pin_name) {
  210. pin_name = fdt_stringlist_get(fdt, offset,
  211. "allwinner,pins",
  212. i, NULL);
  213. if (!pin_name)
  214. break;
  215. }
  216. pin = name_to_gpio(pin_name);
  217. if (pin < 0)
  218. break;
  219. if (IS_ENABLED(CONFIG_MACH_SUN50I))
  220. sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
  221. else
  222. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
  223. sunxi_gpio_set_drv(pin, drive);
  224. sunxi_gpio_set_pull(pin, pull);
  225. }
  226. }
  227. return 0;
  228. }
  229. static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
  230. {
  231. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  232. int ret;
  233. if (!enable) {
  234. clk_disable(&priv->clk_ahb);
  235. clk_disable(&priv->clk_mod);
  236. if (reset_valid(&priv->reset))
  237. reset_assert(&priv->reset);
  238. return 0;
  239. }
  240. ret = clk_enable(&priv->clk_ahb);
  241. if (ret) {
  242. dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
  243. return ret;
  244. }
  245. ret = clk_enable(&priv->clk_mod);
  246. if (ret) {
  247. dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
  248. goto err_ahb;
  249. }
  250. if (reset_valid(&priv->reset)) {
  251. ret = reset_deassert(&priv->reset);
  252. if (ret) {
  253. dev_err(dev, "failed to deassert reset\n");
  254. goto err_mod;
  255. }
  256. }
  257. return 0;
  258. err_mod:
  259. clk_disable(&priv->clk_mod);
  260. err_ahb:
  261. clk_disable(&priv->clk_ahb);
  262. return ret;
  263. }
  264. static int sun4i_spi_claim_bus(struct udevice *dev)
  265. {
  266. struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
  267. int ret;
  268. ret = sun4i_spi_set_clock(dev->parent, true);
  269. if (ret)
  270. return ret;
  271. setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
  272. SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
  273. if (priv->variant->has_soft_reset)
  274. setbits_le32(SPI_REG(priv, SPI_GCR),
  275. SPI_BIT(priv, SPI_GCR_SRST));
  276. setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
  277. SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
  278. return 0;
  279. }
  280. static int sun4i_spi_release_bus(struct udevice *dev)
  281. {
  282. struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
  283. clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
  284. sun4i_spi_set_clock(dev->parent, false);
  285. return 0;
  286. }
  287. static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
  288. const void *dout, void *din, unsigned long flags)
  289. {
  290. struct udevice *bus = dev->parent;
  291. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  292. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  293. u32 len = bitlen / 8;
  294. u32 rx_fifocnt;
  295. u8 nbytes;
  296. int ret;
  297. priv->tx_buf = dout;
  298. priv->rx_buf = din;
  299. if (bitlen % 8) {
  300. debug("%s: non byte-aligned SPI transfer.\n", __func__);
  301. return -ENAVAIL;
  302. }
  303. if (flags & SPI_XFER_BEGIN)
  304. sun4i_spi_set_cs(bus, slave_plat->cs, true);
  305. /* Reset FIFOs */
  306. setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
  307. SPI_BIT(priv, SPI_FCR_TF_RST));
  308. while (len) {
  309. /* Setup the transfer now... */
  310. nbytes = min(len, (priv->variant->fifo_depth - 1));
  311. /* Setup the counters */
  312. writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
  313. writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
  314. if (priv->variant->has_burst_ctl)
  315. writel(SUN4I_BURST_CNT(nbytes),
  316. SPI_REG(priv, SPI_BCTL));
  317. /* Fill the TX FIFO */
  318. sun4i_spi_fill_fifo(priv, nbytes);
  319. /* Start the transfer */
  320. setbits_le32(SPI_REG(priv, SPI_TCR),
  321. SPI_BIT(priv, SPI_TCR_XCH));
  322. /* Wait till RX FIFO to be empty */
  323. ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
  324. rx_fifocnt,
  325. (((rx_fifocnt &
  326. SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
  327. SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
  328. SUN4I_SPI_TIMEOUT_US);
  329. if (ret < 0) {
  330. printf("ERROR: sun4i_spi: Timeout transferring data\n");
  331. sun4i_spi_set_cs(bus, slave_plat->cs, false);
  332. return ret;
  333. }
  334. /* Drain the RX FIFO */
  335. sun4i_spi_drain_fifo(priv, nbytes);
  336. len -= nbytes;
  337. }
  338. if (flags & SPI_XFER_END)
  339. sun4i_spi_set_cs(bus, slave_plat->cs, false);
  340. return 0;
  341. }
  342. static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
  343. {
  344. struct sun4i_spi_plat *plat = dev_get_plat(dev);
  345. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  346. unsigned int div;
  347. u32 reg;
  348. if (speed > plat->max_hz)
  349. speed = plat->max_hz;
  350. if (speed < SUN4I_SPI_MIN_RATE)
  351. speed = SUN4I_SPI_MIN_RATE;
  352. /*
  353. * Setup clock divider.
  354. *
  355. * We have two choices there. Either we can use the clock
  356. * divide rate 1, which is calculated thanks to this formula:
  357. * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
  358. * Or we can use CDR2, which is calculated with the formula:
  359. * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
  360. * Whether we use the former or the latter is set through the
  361. * DRS bit.
  362. *
  363. * First try CDR2, and if we can't reach the expected
  364. * frequency, fall back to CDR1.
  365. */
  366. div = SUN4I_SPI_MAX_RATE / (2 * speed);
  367. reg = readl(SPI_REG(priv, SPI_CCR));
  368. if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
  369. if (div > 0)
  370. div--;
  371. reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
  372. reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
  373. } else {
  374. div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
  375. reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
  376. reg |= SUN4I_CLK_CTL_CDR1(div);
  377. }
  378. priv->freq = speed;
  379. writel(reg, SPI_REG(priv, SPI_CCR));
  380. return 0;
  381. }
  382. static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
  383. {
  384. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  385. u32 reg;
  386. reg = readl(SPI_REG(priv, SPI_TCR));
  387. reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
  388. if (mode & SPI_CPOL)
  389. reg |= SPI_BIT(priv, SPI_TCR_CPOL);
  390. if (mode & SPI_CPHA)
  391. reg |= SPI_BIT(priv, SPI_TCR_CPHA);
  392. priv->mode = mode;
  393. writel(reg, SPI_REG(priv, SPI_TCR));
  394. return 0;
  395. }
  396. static const struct dm_spi_ops sun4i_spi_ops = {
  397. .claim_bus = sun4i_spi_claim_bus,
  398. .release_bus = sun4i_spi_release_bus,
  399. .xfer = sun4i_spi_xfer,
  400. .set_speed = sun4i_spi_set_speed,
  401. .set_mode = sun4i_spi_set_mode,
  402. };
  403. static int sun4i_spi_probe(struct udevice *bus)
  404. {
  405. struct sun4i_spi_plat *plat = dev_get_plat(bus);
  406. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  407. int ret;
  408. ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
  409. if (ret) {
  410. dev_err(bus, "failed to get ahb clock\n");
  411. return ret;
  412. }
  413. ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
  414. if (ret) {
  415. dev_err(bus, "failed to get mod clock\n");
  416. return ret;
  417. }
  418. ret = reset_get_by_index(bus, 0, &priv->reset);
  419. if (ret && ret != -ENOENT) {
  420. dev_err(bus, "failed to get reset\n");
  421. return ret;
  422. }
  423. sun4i_spi_parse_pins(bus);
  424. priv->variant = plat->variant;
  425. priv->base = plat->base;
  426. priv->freq = plat->max_hz;
  427. return 0;
  428. }
  429. static int sun4i_spi_of_to_plat(struct udevice *bus)
  430. {
  431. struct sun4i_spi_plat *plat = dev_get_plat(bus);
  432. int node = dev_of_offset(bus);
  433. plat->base = dev_read_addr(bus);
  434. plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
  435. plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
  436. "spi-max-frequency",
  437. SUN4I_SPI_DEFAULT_RATE);
  438. if (plat->max_hz > SUN4I_SPI_MAX_RATE)
  439. plat->max_hz = SUN4I_SPI_MAX_RATE;
  440. return 0;
  441. }
  442. static const unsigned long sun4i_spi_regs[] = {
  443. [SPI_GCR] = SUN4I_CTL_REG,
  444. [SPI_TCR] = SUN4I_CTL_REG,
  445. [SPI_FCR] = SUN4I_CTL_REG,
  446. [SPI_FSR] = SUN4I_FIFO_STA_REG,
  447. [SPI_CCR] = SUN4I_CLK_CTL_REG,
  448. [SPI_BC] = SUN4I_BURST_CNT_REG,
  449. [SPI_TC] = SUN4I_XMIT_CNT_REG,
  450. [SPI_TXD] = SUN4I_TXDATA_REG,
  451. [SPI_RXD] = SUN4I_RXDATA_REG,
  452. };
  453. static const u32 sun4i_spi_bits[] = {
  454. [SPI_GCR_TP] = BIT(18),
  455. [SPI_TCR_CPHA] = BIT(2),
  456. [SPI_TCR_CPOL] = BIT(3),
  457. [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
  458. [SPI_TCR_XCH] = BIT(10),
  459. [SPI_TCR_CS_SEL] = 12,
  460. [SPI_TCR_CS_MASK] = 0x3000,
  461. [SPI_TCR_CS_MANUAL] = BIT(16),
  462. [SPI_TCR_CS_LEVEL] = BIT(17),
  463. [SPI_FCR_TF_RST] = BIT(8),
  464. [SPI_FCR_RF_RST] = BIT(9),
  465. [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
  466. };
  467. static const unsigned long sun6i_spi_regs[] = {
  468. [SPI_GCR] = SUN6I_GBL_CTL_REG,
  469. [SPI_TCR] = SUN6I_TFR_CTL_REG,
  470. [SPI_FCR] = SUN6I_FIFO_CTL_REG,
  471. [SPI_FSR] = SUN6I_FIFO_STA_REG,
  472. [SPI_CCR] = SUN6I_CLK_CTL_REG,
  473. [SPI_BC] = SUN6I_BURST_CNT_REG,
  474. [SPI_TC] = SUN6I_XMIT_CNT_REG,
  475. [SPI_BCTL] = SUN6I_BURST_CTL_REG,
  476. [SPI_TXD] = SUN6I_TXDATA_REG,
  477. [SPI_RXD] = SUN6I_RXDATA_REG,
  478. };
  479. static const u32 sun6i_spi_bits[] = {
  480. [SPI_GCR_TP] = BIT(7),
  481. [SPI_GCR_SRST] = BIT(31),
  482. [SPI_TCR_CPHA] = BIT(0),
  483. [SPI_TCR_CPOL] = BIT(1),
  484. [SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
  485. [SPI_TCR_CS_SEL] = 4,
  486. [SPI_TCR_CS_MASK] = 0x30,
  487. [SPI_TCR_CS_MANUAL] = BIT(6),
  488. [SPI_TCR_CS_LEVEL] = BIT(7),
  489. [SPI_TCR_XCH] = BIT(31),
  490. [SPI_FCR_RF_RST] = BIT(15),
  491. [SPI_FCR_TF_RST] = BIT(31),
  492. [SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0),
  493. };
  494. static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
  495. .regs = sun4i_spi_regs,
  496. .bits = sun4i_spi_bits,
  497. .fifo_depth = 64,
  498. };
  499. static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
  500. .regs = sun6i_spi_regs,
  501. .bits = sun6i_spi_bits,
  502. .fifo_depth = 128,
  503. .has_soft_reset = true,
  504. .has_burst_ctl = true,
  505. };
  506. static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
  507. .regs = sun6i_spi_regs,
  508. .bits = sun6i_spi_bits,
  509. .fifo_depth = 64,
  510. .has_soft_reset = true,
  511. .has_burst_ctl = true,
  512. };
  513. static const struct udevice_id sun4i_spi_ids[] = {
  514. {
  515. .compatible = "allwinner,sun4i-a10-spi",
  516. .data = (ulong)&sun4i_a10_spi_variant,
  517. },
  518. {
  519. .compatible = "allwinner,sun6i-a31-spi",
  520. .data = (ulong)&sun6i_a31_spi_variant,
  521. },
  522. {
  523. .compatible = "allwinner,sun8i-h3-spi",
  524. .data = (ulong)&sun8i_h3_spi_variant,
  525. },
  526. { /* sentinel */ }
  527. };
  528. U_BOOT_DRIVER(sun4i_spi) = {
  529. .name = "sun4i_spi",
  530. .id = UCLASS_SPI,
  531. .of_match = sun4i_spi_ids,
  532. .ops = &sun4i_spi_ops,
  533. .of_to_plat = sun4i_spi_of_to_plat,
  534. .plat_auto = sizeof(struct sun4i_spi_plat),
  535. .priv_auto = sizeof(struct sun4i_spi_priv),
  536. .probe = sun4i_spi_probe,
  537. };