spi-mxic.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2021 Macronix International Co., Ltd.
  4. *
  5. * Authors:
  6. * zhengxunli <zhengxunli@mxic.com.tw>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <asm/io.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <spi-mem.h>
  16. #include <linux/bug.h>
  17. #include <linux/iopoll.h>
  18. #define HC_CFG 0x0
  19. #define HC_CFG_IF_CFG(x) ((x) << 27)
  20. #define HC_CFG_DUAL_SLAVE BIT(31)
  21. #define HC_CFG_INDIVIDUAL BIT(30)
  22. #define HC_CFG_NIO(x) (((x) / 4) << 27)
  23. #define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
  24. #define HC_CFG_TYPE_SPI_NOR 0
  25. #define HC_CFG_TYPE_SPI_NAND 1
  26. #define HC_CFG_TYPE_SPI_RAM 2
  27. #define HC_CFG_TYPE_RAW_NAND 3
  28. #define HC_CFG_SLV_ACT(x) ((x) << 21)
  29. #define HC_CFG_CLK_PH_EN BIT(20)
  30. #define HC_CFG_CLK_POL_INV BIT(19)
  31. #define HC_CFG_BIG_ENDIAN BIT(18)
  32. #define HC_CFG_DATA_PASS BIT(17)
  33. #define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
  34. #define HC_CFG_MAN_START_EN BIT(3)
  35. #define HC_CFG_MAN_START BIT(2)
  36. #define HC_CFG_MAN_CS_EN BIT(1)
  37. #define HC_CFG_MAN_CS_ASSERT BIT(0)
  38. #define INT_STS 0x4
  39. #define INT_STS_EN 0x8
  40. #define INT_SIG_EN 0xc
  41. #define INT_STS_ALL GENMASK(31, 0)
  42. #define INT_RDY_PIN BIT(26)
  43. #define INT_RDY_SR BIT(25)
  44. #define INT_LNR_SUSP BIT(24)
  45. #define INT_ECC_ERR BIT(17)
  46. #define INT_CRC_ERR BIT(16)
  47. #define INT_LWR_DIS BIT(12)
  48. #define INT_LRD_DIS BIT(11)
  49. #define INT_SDMA_INT BIT(10)
  50. #define INT_DMA_FINISH BIT(9)
  51. #define INT_RX_NOT_FULL BIT(3)
  52. #define INT_RX_NOT_EMPTY BIT(2)
  53. #define INT_TX_NOT_FULL BIT(1)
  54. #define INT_TX_EMPTY BIT(0)
  55. #define HC_EN 0x10
  56. #define HC_EN_BIT BIT(0)
  57. #define TXD(x) (0x14 + ((x) * 4))
  58. #define RXD 0x24
  59. #define SS_CTRL(s) (0x30 + ((s) * 4))
  60. #define LRD_CFG 0x44
  61. #define LWR_CFG 0x80
  62. #define RWW_CFG 0x70
  63. #define OP_READ BIT(23)
  64. #define OP_DUMMY_CYC(x) ((x) << 17)
  65. #define OP_ADDR_BYTES(x) ((x) << 14)
  66. #define OP_CMD_BYTES(x) (((x) - 1) << 13)
  67. #define OP_OCTA_CRC_EN BIT(12)
  68. #define OP_DQS_EN BIT(11)
  69. #define OP_ENHC_EN BIT(10)
  70. #define OP_PREAMBLE_EN BIT(9)
  71. #define OP_DATA_DDR BIT(8)
  72. #define OP_DATA_BUSW(x) ((x) << 6)
  73. #define OP_ADDR_DDR BIT(5)
  74. #define OP_ADDR_BUSW(x) ((x) << 3)
  75. #define OP_CMD_DDR BIT(2)
  76. #define OP_CMD_BUSW(x) (x)
  77. #define OP_BUSW_1 0
  78. #define OP_BUSW_2 1
  79. #define OP_BUSW_4 2
  80. #define OP_BUSW_8 3
  81. #define OCTA_CRC 0x38
  82. #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
  83. #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
  84. #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
  85. #define ONFI_DIN_CNT(s) (0x3c + (s))
  86. #define LRD_CTRL 0x48
  87. #define RWW_CTRL 0x74
  88. #define LWR_CTRL 0x84
  89. #define LMODE_EN BIT(31)
  90. #define LMODE_SLV_ACT(x) ((x) << 21)
  91. #define LMODE_CMD1(x) ((x) << 8)
  92. #define LMODE_CMD0(x) (x)
  93. #define LRD_ADDR 0x4c
  94. #define LWR_ADDR 0x88
  95. #define LRD_RANGE 0x50
  96. #define LWR_RANGE 0x8c
  97. #define AXI_SLV_ADDR 0x54
  98. #define DMAC_RD_CFG 0x58
  99. #define DMAC_WR_CFG 0x94
  100. #define DMAC_CFG_PERIPH_EN BIT(31)
  101. #define DMAC_CFG_ALLFLUSH_EN BIT(30)
  102. #define DMAC_CFG_LASTFLUSH_EN BIT(29)
  103. #define DMAC_CFG_QE(x) (((x) + 1) << 16)
  104. #define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
  105. #define DMAC_CFG_BURST_SZ(x) ((x) << 8)
  106. #define DMAC_CFG_DIR_READ BIT(1)
  107. #define DMAC_CFG_START BIT(0)
  108. #define DMAC_RD_CNT 0x5c
  109. #define DMAC_WR_CNT 0x98
  110. #define SDMA_ADDR 0x60
  111. #define DMAM_CFG 0x64
  112. #define DMAM_CFG_START BIT(31)
  113. #define DMAM_CFG_CONT BIT(30)
  114. #define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
  115. #define DMAM_CFG_DIR_READ BIT(1)
  116. #define DMAM_CFG_EN BIT(0)
  117. #define DMAM_CNT 0x68
  118. #define LNR_TIMER_TH 0x6c
  119. #define RDM_CFG0 0x78
  120. #define RDM_CFG0_POLY(x) (x)
  121. #define RDM_CFG1 0x7c
  122. #define RDM_CFG1_RDM_EN BIT(31)
  123. #define RDM_CFG1_SEED(x) (x)
  124. #define LWR_SUSP_CTRL 0x90
  125. #define LWR_SUSP_CTRL_EN BIT(31)
  126. #define DMAS_CTRL 0x9c
  127. #define DMAS_CTRL_EN BIT(31)
  128. #define DMAS_CTRL_DIR_READ BIT(30)
  129. #define DATA_STROB 0xa0
  130. #define DATA_STROB_EDO_EN BIT(2)
  131. #define DATA_STROB_INV_POL BIT(1)
  132. #define DATA_STROB_DELAY_2CYC BIT(0)
  133. #define IDLY_CODE(x) (0xa4 + ((x) * 4))
  134. #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
  135. #define GPIO 0xc4
  136. #define GPIO_PT(x) BIT(3 + ((x) * 16))
  137. #define GPIO_RESET(x) BIT(2 + ((x) * 16))
  138. #define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
  139. #define GPIO_WPB(x) BIT((x) * 16)
  140. #define HC_VER 0xd0
  141. #define HW_TEST(x) (0xe0 + ((x) * 4))
  142. struct mxic_spi_priv {
  143. struct clk *send_clk;
  144. struct clk *send_dly_clk;
  145. void __iomem *regs;
  146. u32 cur_speed_hz;
  147. };
  148. static int mxic_spi_clk_enable(struct mxic_spi_priv *priv)
  149. {
  150. int ret;
  151. ret = clk_prepare_enable(priv->send_clk);
  152. if (ret)
  153. return ret;
  154. ret = clk_prepare_enable(priv->send_dly_clk);
  155. if (ret)
  156. goto err_send_dly_clk;
  157. return ret;
  158. err_send_dly_clk:
  159. clk_disable_unprepare(priv->send_clk);
  160. return ret;
  161. }
  162. static void mxic_spi_clk_disable(struct mxic_spi_priv *priv)
  163. {
  164. clk_disable_unprepare(priv->send_clk);
  165. clk_disable_unprepare(priv->send_dly_clk);
  166. }
  167. static void mxic_spi_set_input_delay_dqs(struct mxic_spi_priv *priv,
  168. u8 idly_code)
  169. {
  170. writel(IDLY_CODE_VAL(0, idly_code) |
  171. IDLY_CODE_VAL(1, idly_code) |
  172. IDLY_CODE_VAL(2, idly_code) |
  173. IDLY_CODE_VAL(3, idly_code),
  174. priv->regs + IDLY_CODE(0));
  175. writel(IDLY_CODE_VAL(4, idly_code) |
  176. IDLY_CODE_VAL(5, idly_code) |
  177. IDLY_CODE_VAL(6, idly_code) |
  178. IDLY_CODE_VAL(7, idly_code),
  179. priv->regs + IDLY_CODE(1));
  180. }
  181. static int mxic_spi_clk_setup(struct mxic_spi_priv *priv, uint freq)
  182. {
  183. int ret;
  184. ret = clk_set_rate(priv->send_clk, freq);
  185. if (ret)
  186. return ret;
  187. ret = clk_set_rate(priv->send_dly_clk, freq);
  188. if (ret)
  189. return ret;
  190. /*
  191. * A constant delay range from 0x0 ~ 0x1F for input delay,
  192. * the unit is 78 ps, the max input delay is 2.418 ns.
  193. */
  194. mxic_spi_set_input_delay_dqs(priv, 0xf);
  195. return 0;
  196. }
  197. static int mxic_spi_set_speed(struct udevice *bus, uint freq)
  198. {
  199. struct mxic_spi_priv *priv = dev_get_priv(bus);
  200. int ret;
  201. if (priv->cur_speed_hz == freq)
  202. return 0;
  203. mxic_spi_clk_disable(priv);
  204. ret = mxic_spi_clk_setup(priv, freq);
  205. if (ret)
  206. return ret;
  207. ret = mxic_spi_clk_enable(priv);
  208. if (ret)
  209. return ret;
  210. priv->cur_speed_hz = freq;
  211. return 0;
  212. }
  213. static int mxic_spi_set_mode(struct udevice *bus, uint mode)
  214. {
  215. struct mxic_spi_priv *priv = dev_get_priv(bus);
  216. u32 hc_config = 0;
  217. if (mode & SPI_CPHA)
  218. hc_config |= HC_CFG_CLK_PH_EN;
  219. if (mode & SPI_CPOL)
  220. hc_config |= HC_CFG_CLK_POL_INV;
  221. writel(hc_config, priv->regs + HC_CFG);
  222. return 0;
  223. }
  224. static void mxic_spi_hw_init(struct mxic_spi_priv *priv)
  225. {
  226. writel(0, priv->regs + DATA_STROB);
  227. writel(INT_STS_ALL, priv->regs + INT_STS_EN);
  228. writel(0, priv->regs + HC_EN);
  229. writel(0, priv->regs + LRD_CFG);
  230. writel(0, priv->regs + LRD_CTRL);
  231. writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
  232. HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
  233. priv->regs + HC_CFG);
  234. }
  235. static int mxic_spi_data_xfer(struct mxic_spi_priv *priv, const void *txbuf,
  236. void *rxbuf, unsigned int len)
  237. {
  238. unsigned int pos = 0;
  239. while (pos < len) {
  240. unsigned int nbytes = len - pos;
  241. u32 data = 0xffffffff;
  242. u32 sts;
  243. int ret;
  244. if (nbytes > 4)
  245. nbytes = 4;
  246. if (txbuf)
  247. memcpy(&data, txbuf + pos, nbytes);
  248. ret = readl_poll_timeout(priv->regs + INT_STS, sts,
  249. sts & INT_TX_EMPTY, 1000000);
  250. if (ret)
  251. return ret;
  252. writel(data, priv->regs + TXD(nbytes % 4));
  253. if (rxbuf) {
  254. ret = readl_poll_timeout(priv->regs + INT_STS, sts,
  255. sts & INT_TX_EMPTY,
  256. 1000000);
  257. if (ret)
  258. return ret;
  259. ret = readl_poll_timeout(priv->regs + INT_STS, sts,
  260. sts & INT_RX_NOT_EMPTY,
  261. 1000000);
  262. if (ret)
  263. return ret;
  264. data = readl(priv->regs + RXD);
  265. data >>= (8 * (4 - nbytes));
  266. memcpy(rxbuf + pos, &data, nbytes);
  267. WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY);
  268. } else {
  269. readl(priv->regs + RXD);
  270. }
  271. WARN_ON(readl(priv->regs + INT_STS) & INT_RX_NOT_EMPTY);
  272. pos += nbytes;
  273. }
  274. return 0;
  275. }
  276. static bool mxic_spi_mem_supports_op(struct spi_slave *slave,
  277. const struct spi_mem_op *op)
  278. {
  279. if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
  280. op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
  281. return false;
  282. if (op->addr.nbytes > 7)
  283. return false;
  284. return spi_mem_default_supports_op(slave, op);
  285. }
  286. static int mxic_spi_mem_exec_op(struct spi_slave *slave,
  287. const struct spi_mem_op *op)
  288. {
  289. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
  290. struct udevice *bus = slave->dev->parent;
  291. struct mxic_spi_priv *priv = dev_get_priv(bus);
  292. int nio = 1, i, ret;
  293. u32 ss_ctrl;
  294. u8 addr[8], dummy_bytes = 0;
  295. if (slave->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
  296. nio = 8;
  297. else if (slave->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
  298. nio = 4;
  299. else if (slave->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
  300. nio = 2;
  301. writel(HC_CFG_NIO(nio) |
  302. HC_CFG_TYPE(slave_plat->cs, HC_CFG_TYPE_SPI_NOR) |
  303. HC_CFG_SLV_ACT(slave_plat->cs) | HC_CFG_IDLE_SIO_LVL(1) |
  304. HC_CFG_MAN_CS_EN,
  305. priv->regs + HC_CFG);
  306. writel(HC_EN_BIT, priv->regs + HC_EN);
  307. ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
  308. if (op->addr.nbytes)
  309. ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
  310. OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
  311. /*
  312. * Since the SPI MXIC dummy buswidth is aligned with the data buswidth,
  313. * the dummy byte needs to be recalculated to send out the correct
  314. * dummy cycle.
  315. */
  316. if (op->dummy.nbytes) {
  317. dummy_bytes = op->dummy.nbytes /
  318. op->addr.buswidth *
  319. op->data.buswidth;
  320. ss_ctrl |= OP_DUMMY_CYC(dummy_bytes);
  321. }
  322. if (op->data.nbytes) {
  323. ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
  324. if (op->data.dir == SPI_MEM_DATA_IN)
  325. ss_ctrl |= OP_READ;
  326. }
  327. writel(ss_ctrl, priv->regs + SS_CTRL(slave_plat->cs));
  328. writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
  329. priv->regs + HC_CFG);
  330. ret = mxic_spi_data_xfer(priv, &op->cmd.opcode, NULL, 1);
  331. if (ret)
  332. goto out;
  333. for (i = 0; i < op->addr.nbytes; i++)
  334. addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  335. ret = mxic_spi_data_xfer(priv, addr, NULL, op->addr.nbytes);
  336. if (ret)
  337. goto out;
  338. ret = mxic_spi_data_xfer(priv, NULL, NULL, dummy_bytes);
  339. if (ret)
  340. goto out;
  341. ret = mxic_spi_data_xfer(priv,
  342. op->data.dir == SPI_MEM_DATA_OUT ?
  343. op->data.buf.out : NULL,
  344. op->data.dir == SPI_MEM_DATA_IN ?
  345. op->data.buf.in : NULL,
  346. op->data.nbytes);
  347. out:
  348. writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
  349. priv->regs + HC_CFG);
  350. writel(0, priv->regs + HC_EN);
  351. return ret;
  352. }
  353. static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
  354. .supports_op = mxic_spi_mem_supports_op,
  355. .exec_op = mxic_spi_mem_exec_op,
  356. };
  357. static int mxic_spi_claim_bus(struct udevice *dev)
  358. {
  359. struct udevice *bus = dev_get_parent(dev);
  360. struct mxic_spi_priv *priv = dev_get_priv(bus);
  361. writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
  362. priv->regs + HC_CFG);
  363. writel(HC_EN_BIT, priv->regs + HC_EN);
  364. writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
  365. priv->regs + HC_CFG);
  366. return 0;
  367. }
  368. static int mxic_spi_release_bus(struct udevice *dev)
  369. {
  370. struct udevice *bus = dev_get_parent(dev);
  371. struct mxic_spi_priv *priv = dev_get_priv(bus);
  372. writel(readl(priv->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
  373. priv->regs + HC_CFG);
  374. writel(0, priv->regs + HC_EN);
  375. return 0;
  376. }
  377. static int mxic_spi_xfer(struct udevice *dev, unsigned int bitlen,
  378. const void *dout, void *din, unsigned long flags)
  379. {
  380. struct udevice *bus = dev_get_parent(dev);
  381. struct mxic_spi_priv *priv = dev_get_priv(bus);
  382. struct spi_slave *slave = dev_get_parent_priv(dev);
  383. unsigned int busw = OP_BUSW_1;
  384. unsigned int len = bitlen / 8;
  385. int ret;
  386. if (dout && din) {
  387. if (((slave->mode & SPI_TX_QUAD) &&
  388. !(slave->mode & SPI_RX_QUAD)) ||
  389. ((slave->mode & SPI_TX_DUAL) &&
  390. !(slave->mode & SPI_RX_DUAL)))
  391. return -ENOTSUPP;
  392. }
  393. if (din) {
  394. if (slave->mode & SPI_TX_QUAD)
  395. busw = OP_BUSW_4;
  396. else if (slave->mode & SPI_TX_DUAL)
  397. busw = OP_BUSW_2;
  398. } else if (dout) {
  399. if (slave->mode & SPI_RX_QUAD)
  400. busw = OP_BUSW_4;
  401. else if (slave->mode & SPI_RX_DUAL)
  402. busw = OP_BUSW_2;
  403. }
  404. writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
  405. OP_DATA_BUSW(busw) | (din ? OP_READ : 0),
  406. priv->regs + SS_CTRL(0));
  407. ret = mxic_spi_data_xfer(priv, dout, din, len);
  408. if (ret)
  409. return ret;
  410. return 0;
  411. }
  412. static int mxic_spi_probe(struct udevice *bus)
  413. {
  414. struct mxic_spi_priv *priv = dev_get_priv(bus);
  415. priv->regs = (void *)dev_read_addr(bus);
  416. priv->send_clk = devm_clk_get(bus, "send_clk");
  417. if (IS_ERR(priv->send_clk))
  418. return PTR_ERR(priv->send_clk);
  419. priv->send_dly_clk = devm_clk_get(bus, "send_dly_clk");
  420. if (IS_ERR(priv->send_dly_clk))
  421. return PTR_ERR(priv->send_dly_clk);
  422. mxic_spi_hw_init(priv);
  423. return 0;
  424. }
  425. static const struct dm_spi_ops mxic_spi_ops = {
  426. .claim_bus = mxic_spi_claim_bus,
  427. .release_bus = mxic_spi_release_bus,
  428. .xfer = mxic_spi_xfer,
  429. .set_speed = mxic_spi_set_speed,
  430. .set_mode = mxic_spi_set_mode,
  431. .mem_ops = &mxic_spi_mem_ops,
  432. };
  433. static const struct udevice_id mxic_spi_ids[] = {
  434. { .compatible = "mxicy,mx25f0a-spi", },
  435. { }
  436. };
  437. U_BOOT_DRIVER(mxic_spi) = {
  438. .name = "mxic_spi",
  439. .id = UCLASS_SPI,
  440. .of_match = mxic_spi_ids,
  441. .ops = &mxic_spi_ops,
  442. .priv_auto = sizeof(struct mxic_spi_priv),
  443. .probe = mxic_spi_probe,
  444. };