soft_spi.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. *
  5. * (C) Copyright 2002
  6. * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  7. *
  8. * Influenced by code from:
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <fdtdec.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <spi.h>
  18. #include <asm/global_data.h>
  19. #include <asm/gpio.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. struct soft_spi_plat {
  24. struct gpio_desc cs;
  25. struct gpio_desc sclk;
  26. struct gpio_desc mosi;
  27. struct gpio_desc miso;
  28. int spi_delay_us;
  29. int flags;
  30. };
  31. #define SPI_MASTER_NO_RX BIT(0)
  32. #define SPI_MASTER_NO_TX BIT(1)
  33. struct soft_spi_priv {
  34. unsigned int mode;
  35. };
  36. static int soft_spi_scl(struct udevice *dev, int bit)
  37. {
  38. struct udevice *bus = dev_get_parent(dev);
  39. struct soft_spi_plat *plat = dev_get_plat(bus);
  40. dm_gpio_set_value(&plat->sclk, bit);
  41. return 0;
  42. }
  43. static int soft_spi_sda(struct udevice *dev, int bit)
  44. {
  45. struct udevice *bus = dev_get_parent(dev);
  46. struct soft_spi_plat *plat = dev_get_plat(bus);
  47. dm_gpio_set_value(&plat->mosi, bit);
  48. return 0;
  49. }
  50. static int soft_spi_cs_activate(struct udevice *dev)
  51. {
  52. struct udevice *bus = dev_get_parent(dev);
  53. struct soft_spi_priv *priv = dev_get_priv(bus);
  54. struct soft_spi_plat *plat = dev_get_plat(bus);
  55. int cidle = !!(priv->mode & SPI_CPOL);
  56. dm_gpio_set_value(&plat->cs, 0);
  57. dm_gpio_set_value(&plat->sclk, cidle); /* to idle */
  58. dm_gpio_set_value(&plat->cs, 1);
  59. return 0;
  60. }
  61. static int soft_spi_cs_deactivate(struct udevice *dev)
  62. {
  63. struct udevice *bus = dev_get_parent(dev);
  64. struct soft_spi_plat *plat = dev_get_plat(bus);
  65. dm_gpio_set_value(&plat->cs, 0);
  66. return 0;
  67. }
  68. static int soft_spi_claim_bus(struct udevice *dev)
  69. {
  70. struct udevice *bus = dev_get_parent(dev);
  71. struct soft_spi_priv *priv = dev_get_priv(bus);
  72. int cidle = !!(priv->mode & SPI_CPOL);
  73. /*
  74. * Make sure the SPI clock is in idle state as defined for
  75. * this slave.
  76. */
  77. return soft_spi_scl(dev, cidle);
  78. }
  79. static int soft_spi_release_bus(struct udevice *dev)
  80. {
  81. /* Nothing to do */
  82. return 0;
  83. }
  84. /*-----------------------------------------------------------------------
  85. * SPI transfer
  86. *
  87. * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
  88. * "bitlen" bits in the SPI MISO port. That's just the way SPI works.
  89. *
  90. * The source of the outgoing bits is the "dout" parameter and the
  91. * destination of the input bits is the "din" parameter. Note that "dout"
  92. * and "din" can point to the same memory location, in which case the
  93. * input data overwrites the output data (since both are buffered by
  94. * temporary variables, this is OK).
  95. */
  96. static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
  97. const void *dout, void *din, unsigned long flags)
  98. {
  99. struct udevice *bus = dev_get_parent(dev);
  100. struct soft_spi_priv *priv = dev_get_priv(bus);
  101. struct soft_spi_plat *plat = dev_get_plat(bus);
  102. uchar tmpdin = 0;
  103. uchar tmpdout = 0;
  104. const u8 *txd = dout;
  105. u8 *rxd = din;
  106. int cpha = !!(priv->mode & SPI_CPHA);
  107. int cidle = !!(priv->mode & SPI_CPOL);
  108. unsigned int j;
  109. debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
  110. dev->parent->name, dev->name, *(uint *)txd, *(uint *)rxd,
  111. bitlen);
  112. if (flags & SPI_XFER_BEGIN)
  113. soft_spi_cs_activate(dev);
  114. for (j = 0; j < bitlen; j++) {
  115. /*
  116. * Check if it is time to work on a new byte.
  117. */
  118. if ((j % 8) == 0) {
  119. if (txd)
  120. tmpdout = *txd++;
  121. else
  122. tmpdout = 0;
  123. if (j != 0) {
  124. if (rxd)
  125. *rxd++ = tmpdin;
  126. }
  127. tmpdin = 0;
  128. }
  129. /*
  130. * CPOL 0: idle is low (0), active is high (1)
  131. * CPOL 1: idle is high (1), active is low (0)
  132. */
  133. /*
  134. * drive bit
  135. * CPHA 1: CLK from idle to active
  136. */
  137. if (cpha)
  138. soft_spi_scl(dev, !cidle);
  139. if ((plat->flags & SPI_MASTER_NO_TX) == 0)
  140. soft_spi_sda(dev, !!(tmpdout & 0x80));
  141. udelay(plat->spi_delay_us);
  142. /*
  143. * sample bit
  144. * CPHA 0: CLK from idle to active
  145. * CPHA 1: CLK from active to idle
  146. */
  147. if (!cpha)
  148. soft_spi_scl(dev, !cidle);
  149. else
  150. soft_spi_scl(dev, cidle);
  151. tmpdin <<= 1;
  152. if ((plat->flags & SPI_MASTER_NO_RX) == 0)
  153. tmpdin |= dm_gpio_get_value(&plat->miso);
  154. tmpdout <<= 1;
  155. udelay(plat->spi_delay_us);
  156. /*
  157. * drive bit
  158. * CPHA 0: CLK from active to idle
  159. */
  160. if (!cpha)
  161. soft_spi_scl(dev, cidle);
  162. }
  163. /*
  164. * If the number of bits isn't a multiple of 8, shift the last
  165. * bits over to left-justify them. Then store the last byte
  166. * read in.
  167. */
  168. if (rxd) {
  169. if ((bitlen % 8) != 0)
  170. tmpdin <<= 8 - (bitlen % 8);
  171. *rxd++ = tmpdin;
  172. }
  173. if (flags & SPI_XFER_END)
  174. soft_spi_cs_deactivate(dev);
  175. return 0;
  176. }
  177. static int soft_spi_set_speed(struct udevice *dev, unsigned int speed)
  178. {
  179. /* Ignore any speed settings. Speed is implemented via "spi-delay-us" */
  180. return 0;
  181. }
  182. static int soft_spi_set_mode(struct udevice *dev, unsigned int mode)
  183. {
  184. struct soft_spi_priv *priv = dev_get_priv(dev);
  185. priv->mode = mode;
  186. return 0;
  187. }
  188. static const struct dm_spi_ops soft_spi_ops = {
  189. .claim_bus = soft_spi_claim_bus,
  190. .release_bus = soft_spi_release_bus,
  191. .xfer = soft_spi_xfer,
  192. .set_speed = soft_spi_set_speed,
  193. .set_mode = soft_spi_set_mode,
  194. };
  195. static int soft_spi_of_to_plat(struct udevice *dev)
  196. {
  197. struct soft_spi_plat *plat = dev_get_plat(dev);
  198. const void *blob = gd->fdt_blob;
  199. int node = dev_of_offset(dev);
  200. plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
  201. return 0;
  202. }
  203. static int soft_spi_probe(struct udevice *dev)
  204. {
  205. struct spi_slave *slave = dev_get_parent_priv(dev);
  206. struct soft_spi_plat *plat = dev_get_plat(dev);
  207. int cs_flags, clk_flags;
  208. int ret;
  209. cs_flags = (slave && slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
  210. clk_flags = (slave && slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
  211. if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
  212. GPIOD_IS_OUT | cs_flags) ||
  213. gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
  214. GPIOD_IS_OUT | clk_flags))
  215. return -EINVAL;
  216. ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
  217. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  218. if (ret)
  219. plat->flags |= SPI_MASTER_NO_TX;
  220. ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
  221. GPIOD_IS_IN);
  222. if (ret)
  223. plat->flags |= SPI_MASTER_NO_RX;
  224. if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
  225. (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX))
  226. return -EINVAL;
  227. return 0;
  228. }
  229. static const struct udevice_id soft_spi_ids[] = {
  230. { .compatible = "spi-gpio" },
  231. { }
  232. };
  233. U_BOOT_DRIVER(soft_spi) = {
  234. .name = "soft_spi",
  235. .id = UCLASS_SPI,
  236. .of_match = soft_spi_ids,
  237. .ops = &soft_spi_ops,
  238. .of_to_plat = soft_spi_of_to_plat,
  239. .plat_auto = sizeof(struct soft_spi_plat),
  240. .priv_auto = sizeof(struct soft_spi_priv),
  241. .probe = soft_spi_probe,
  242. };