sh_qspi.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH QSPI (Quad SPI) driver
  4. *
  5. * Copyright (C) 2013 Renesas Electronics Corporation
  6. * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  7. */
  8. #include <common.h>
  9. #include <console.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <wait_bit.h>
  13. #include <asm/arch/rmobile.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. /* SH QSPI register bit masks <REG>_<BIT> */
  17. #define SPCR_MSTR 0x08
  18. #define SPCR_SPE 0x40
  19. #define SPSR_SPRFF 0x80
  20. #define SPSR_SPTEF 0x20
  21. #define SPPCR_IO3FV 0x04
  22. #define SPPCR_IO2FV 0x02
  23. #define SPPCR_IO1FV 0x01
  24. #define SPBDCR_RXBC0 BIT(0)
  25. #define SPCMD_SCKDEN BIT(15)
  26. #define SPCMD_SLNDEN BIT(14)
  27. #define SPCMD_SPNDEN BIT(13)
  28. #define SPCMD_SSLKP BIT(7)
  29. #define SPCMD_BRDV0 BIT(2)
  30. #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
  31. SPCMD_SPNDEN | SPCMD_SSLKP | \
  32. SPCMD_BRDV0
  33. #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
  34. SPCMD_BRDV0
  35. #define SPBFCR_TXRST BIT(7)
  36. #define SPBFCR_RXRST BIT(6)
  37. #define SPBFCR_TXTRG 0x30
  38. #define SPBFCR_RXTRG 0x07
  39. /* SH QSPI register set */
  40. struct sh_qspi_regs {
  41. u8 spcr;
  42. u8 sslp;
  43. u8 sppcr;
  44. u8 spsr;
  45. u32 spdr;
  46. u8 spscr;
  47. u8 spssr;
  48. u8 spbr;
  49. u8 spdcr;
  50. u8 spckd;
  51. u8 sslnd;
  52. u8 spnd;
  53. u8 dummy0;
  54. u16 spcmd0;
  55. u16 spcmd1;
  56. u16 spcmd2;
  57. u16 spcmd3;
  58. u8 spbfcr;
  59. u8 dummy1;
  60. u16 spbdcr;
  61. u32 spbmul0;
  62. u32 spbmul1;
  63. u32 spbmul2;
  64. u32 spbmul3;
  65. };
  66. struct sh_qspi_slave {
  67. #if !CONFIG_IS_ENABLED(DM_SPI)
  68. struct spi_slave slave;
  69. #endif
  70. struct sh_qspi_regs *regs;
  71. };
  72. static void sh_qspi_init(struct sh_qspi_slave *ss)
  73. {
  74. /* QSPI initialize */
  75. /* Set master mode only */
  76. writeb(SPCR_MSTR, &ss->regs->spcr);
  77. /* Set SSL signal level */
  78. writeb(0x00, &ss->regs->sslp);
  79. /* Set MOSI signal value when transfer is in idle state */
  80. writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
  81. /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
  82. writeb(0x01, &ss->regs->spbr);
  83. /* Disable Dummy Data Transmission */
  84. writeb(0x00, &ss->regs->spdcr);
  85. /* Set clock delay value */
  86. writeb(0x00, &ss->regs->spckd);
  87. /* Set SSL negation delay value */
  88. writeb(0x00, &ss->regs->sslnd);
  89. /* Set next-access delay value */
  90. writeb(0x00, &ss->regs->spnd);
  91. /* Set equence command */
  92. writew(SPCMD_INIT2, &ss->regs->spcmd0);
  93. /* Reset transfer and receive Buffer */
  94. setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  95. /* Clear transfer and receive Buffer control bit */
  96. clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  97. /* Set equence control method. Use equence0 only */
  98. writeb(0x00, &ss->regs->spscr);
  99. /* Enable SPI function */
  100. setbits_8(&ss->regs->spcr, SPCR_SPE);
  101. }
  102. static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
  103. {
  104. /* Set master mode only */
  105. writeb(SPCR_MSTR, &ss->regs->spcr);
  106. /* Set command */
  107. writew(SPCMD_INIT1, &ss->regs->spcmd0);
  108. /* Reset transfer and receive Buffer */
  109. setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  110. /* Clear transfer and receive Buffer control bit */
  111. clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
  112. /* Set equence control method. Use equence0 only */
  113. writeb(0x00, &ss->regs->spscr);
  114. /* Enable SPI function */
  115. setbits_8(&ss->regs->spcr, SPCR_SPE);
  116. }
  117. static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
  118. {
  119. /* Disable SPI Function */
  120. clrbits_8(&ss->regs->spcr, SPCR_SPE);
  121. }
  122. static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
  123. const void *dout, void *din, unsigned long flags)
  124. {
  125. u32 nbyte, chunk;
  126. int i, ret = 0;
  127. u8 dtdata = 0, drdata;
  128. u8 *tdata = &dtdata, *rdata = &drdata;
  129. u32 *spbmul0 = &ss->regs->spbmul0;
  130. if (dout == NULL && din == NULL) {
  131. if (flags & SPI_XFER_END)
  132. sh_qspi_cs_deactivate(ss);
  133. return 0;
  134. }
  135. if (bitlen % 8) {
  136. printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
  137. return 1;
  138. }
  139. nbyte = bitlen / 8;
  140. if (flags & SPI_XFER_BEGIN) {
  141. sh_qspi_cs_activate(ss);
  142. /* Set 1048576 byte */
  143. writel(0x100000, spbmul0);
  144. }
  145. if (flags & SPI_XFER_END)
  146. writel(nbyte, spbmul0);
  147. if (dout != NULL)
  148. tdata = (u8 *)dout;
  149. if (din != NULL)
  150. rdata = din;
  151. while (nbyte > 0) {
  152. /*
  153. * Check if there is 32 Byte chunk and if there is, transfer
  154. * it in one burst, otherwise transfer on byte-by-byte basis.
  155. */
  156. chunk = (nbyte >= 32) ? 32 : 1;
  157. clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
  158. chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
  159. ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
  160. true, 1000, true);
  161. if (ret)
  162. return ret;
  163. for (i = 0; i < chunk; i++) {
  164. writeb(*tdata, &ss->regs->spdr);
  165. if (dout != NULL)
  166. tdata++;
  167. }
  168. ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
  169. true, 1000, true);
  170. if (ret)
  171. return ret;
  172. for (i = 0; i < chunk; i++) {
  173. *rdata = readb(&ss->regs->spdr);
  174. if (din != NULL)
  175. rdata++;
  176. }
  177. nbyte -= chunk;
  178. }
  179. if (flags & SPI_XFER_END)
  180. sh_qspi_cs_deactivate(ss);
  181. return ret;
  182. }
  183. #if !CONFIG_IS_ENABLED(DM_SPI)
  184. static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
  185. {
  186. return container_of(slave, struct sh_qspi_slave, slave);
  187. }
  188. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  189. {
  190. return 1;
  191. }
  192. void spi_cs_activate(struct spi_slave *slave)
  193. {
  194. struct sh_qspi_slave *ss = to_sh_qspi(slave);
  195. sh_qspi_cs_activate(ss);
  196. }
  197. void spi_cs_deactivate(struct spi_slave *slave)
  198. {
  199. struct sh_qspi_slave *ss = to_sh_qspi(slave);
  200. sh_qspi_cs_deactivate(ss);
  201. }
  202. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  203. unsigned int max_hz, unsigned int mode)
  204. {
  205. struct sh_qspi_slave *ss;
  206. if (!spi_cs_is_valid(bus, cs))
  207. return NULL;
  208. ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
  209. if (!ss) {
  210. printf("SPI_error: Fail to allocate sh_qspi_slave\n");
  211. return NULL;
  212. }
  213. ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
  214. /* Init SH QSPI */
  215. sh_qspi_init(ss);
  216. return &ss->slave;
  217. }
  218. void spi_free_slave(struct spi_slave *slave)
  219. {
  220. struct sh_qspi_slave *spi = to_sh_qspi(slave);
  221. free(spi);
  222. }
  223. int spi_claim_bus(struct spi_slave *slave)
  224. {
  225. return 0;
  226. }
  227. void spi_release_bus(struct spi_slave *slave)
  228. {
  229. }
  230. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  231. const void *dout, void *din, unsigned long flags)
  232. {
  233. struct sh_qspi_slave *ss = to_sh_qspi(slave);
  234. return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
  235. }
  236. #else
  237. #include <dm.h>
  238. static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  239. const void *dout, void *din, unsigned long flags)
  240. {
  241. struct udevice *bus = dev->parent;
  242. struct sh_qspi_slave *ss = dev_get_plat(bus);
  243. return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
  244. }
  245. static int sh_qspi_set_speed(struct udevice *dev, uint speed)
  246. {
  247. /* This is a SPI NOR controller, do nothing. */
  248. return 0;
  249. }
  250. static int sh_qspi_set_mode(struct udevice *dev, uint mode)
  251. {
  252. /* This is a SPI NOR controller, do nothing. */
  253. return 0;
  254. }
  255. static int sh_qspi_probe(struct udevice *dev)
  256. {
  257. struct sh_qspi_slave *ss = dev_get_plat(dev);
  258. sh_qspi_init(ss);
  259. return 0;
  260. }
  261. static int sh_qspi_of_to_plat(struct udevice *dev)
  262. {
  263. struct sh_qspi_slave *plat = dev_get_plat(dev);
  264. plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
  265. return 0;
  266. }
  267. static const struct dm_spi_ops sh_qspi_ops = {
  268. .xfer = sh_qspi_xfer,
  269. .set_speed = sh_qspi_set_speed,
  270. .set_mode = sh_qspi_set_mode,
  271. };
  272. static const struct udevice_id sh_qspi_ids[] = {
  273. { .compatible = "renesas,qspi" },
  274. { }
  275. };
  276. U_BOOT_DRIVER(sh_qspi) = {
  277. .name = "sh_qspi",
  278. .id = UCLASS_SPI,
  279. .of_match = sh_qspi_ids,
  280. .ops = &sh_qspi_ops,
  281. .of_to_plat = sh_qspi_of_to_plat,
  282. .plat_auto = sizeof(struct sh_qspi_slave),
  283. .probe = sh_qspi_probe,
  284. };
  285. #endif