rockchip_sfc.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Rockchip Serial Flash Controller Driver
  4. *
  5. * Copyright (c) 2017-2021, Rockchip Inc.
  6. * Author: Shawn Lin <shawn.lin@rock-chips.com>
  7. * Chris Morgan <macromorgan@hotmail.com>
  8. * Jon Lin <Jon.lin@rock-chips.com>
  9. */
  10. #include <asm/io.h>
  11. #include <bouncebuf.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <linux/iopoll.h>
  17. #include <spi.h>
  18. #include <spi-mem.h>
  19. /* System control */
  20. #define SFC_CTRL 0x0
  21. #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
  22. #define SFC_CTRL_CMD_BITS_SHIFT 8
  23. #define SFC_CTRL_ADDR_BITS_SHIFT 10
  24. #define SFC_CTRL_DATA_BITS_SHIFT 12
  25. /* Interrupt mask */
  26. #define SFC_IMR 0x4
  27. #define SFC_IMR_RX_FULL BIT(0)
  28. #define SFC_IMR_RX_UFLOW BIT(1)
  29. #define SFC_IMR_TX_OFLOW BIT(2)
  30. #define SFC_IMR_TX_EMPTY BIT(3)
  31. #define SFC_IMR_TRAN_FINISH BIT(4)
  32. #define SFC_IMR_BUS_ERR BIT(5)
  33. #define SFC_IMR_NSPI_ERR BIT(6)
  34. #define SFC_IMR_DMA BIT(7)
  35. /* Interrupt clear */
  36. #define SFC_ICLR 0x8
  37. #define SFC_ICLR_RX_FULL BIT(0)
  38. #define SFC_ICLR_RX_UFLOW BIT(1)
  39. #define SFC_ICLR_TX_OFLOW BIT(2)
  40. #define SFC_ICLR_TX_EMPTY BIT(3)
  41. #define SFC_ICLR_TRAN_FINISH BIT(4)
  42. #define SFC_ICLR_BUS_ERR BIT(5)
  43. #define SFC_ICLR_NSPI_ERR BIT(6)
  44. #define SFC_ICLR_DMA BIT(7)
  45. /* FIFO threshold level */
  46. #define SFC_FTLR 0xc
  47. #define SFC_FTLR_TX_SHIFT 0
  48. #define SFC_FTLR_TX_MASK 0x1f
  49. #define SFC_FTLR_RX_SHIFT 8
  50. #define SFC_FTLR_RX_MASK 0x1f
  51. /* Reset FSM and FIFO */
  52. #define SFC_RCVR 0x10
  53. #define SFC_RCVR_RESET BIT(0)
  54. /* Enhanced mode */
  55. #define SFC_AX 0x14
  56. /* Address Bit number */
  57. #define SFC_ABIT 0x18
  58. /* Interrupt status */
  59. #define SFC_ISR 0x1c
  60. #define SFC_ISR_RX_FULL_SHIFT BIT(0)
  61. #define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
  62. #define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
  63. #define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
  64. #define SFC_ISR_TX_FINISH_SHIFT BIT(4)
  65. #define SFC_ISR_BUS_ERR_SHIFT BIT(5)
  66. #define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
  67. #define SFC_ISR_DMA_SHIFT BIT(7)
  68. /* FIFO status */
  69. #define SFC_FSR 0x20
  70. #define SFC_FSR_TX_IS_FULL BIT(0)
  71. #define SFC_FSR_TX_IS_EMPTY BIT(1)
  72. #define SFC_FSR_RX_IS_EMPTY BIT(2)
  73. #define SFC_FSR_RX_IS_FULL BIT(3)
  74. #define SFC_FSR_TXLV_MASK GENMASK(12, 8)
  75. #define SFC_FSR_TXLV_SHIFT 8
  76. #define SFC_FSR_RXLV_MASK GENMASK(20, 16)
  77. #define SFC_FSR_RXLV_SHIFT 16
  78. /* FSM status */
  79. #define SFC_SR 0x24
  80. #define SFC_SR_IS_IDLE 0x0
  81. #define SFC_SR_IS_BUSY 0x1
  82. /* Raw interrupt status */
  83. #define SFC_RISR 0x28
  84. #define SFC_RISR_RX_FULL BIT(0)
  85. #define SFC_RISR_RX_UNDERFLOW BIT(1)
  86. #define SFC_RISR_TX_OVERFLOW BIT(2)
  87. #define SFC_RISR_TX_EMPTY BIT(3)
  88. #define SFC_RISR_TRAN_FINISH BIT(4)
  89. #define SFC_RISR_BUS_ERR BIT(5)
  90. #define SFC_RISR_NSPI_ERR BIT(6)
  91. #define SFC_RISR_DMA BIT(7)
  92. /* Version */
  93. #define SFC_VER 0x2C
  94. #define SFC_VER_3 0x3
  95. #define SFC_VER_4 0x4
  96. #define SFC_VER_5 0x5
  97. /* Delay line controller resiter */
  98. #define SFC_DLL_CTRL0 0x3C
  99. #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
  100. #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
  101. #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
  102. /* Master trigger */
  103. #define SFC_DMA_TRIGGER 0x80
  104. /* Src or Dst addr for master */
  105. #define SFC_DMA_ADDR 0x84
  106. /* Length control register extension 32GB */
  107. #define SFC_LEN_CTRL 0x88
  108. #define SFC_LEN_CTRL_TRB_SEL 1
  109. #define SFC_LEN_EXT 0x8C
  110. /* Command */
  111. #define SFC_CMD 0x100
  112. #define SFC_CMD_IDX_SHIFT 0
  113. #define SFC_CMD_DUMMY_SHIFT 8
  114. #define SFC_CMD_DIR_SHIFT 12
  115. #define SFC_CMD_DIR_RD 0
  116. #define SFC_CMD_DIR_WR 1
  117. #define SFC_CMD_ADDR_SHIFT 14
  118. #define SFC_CMD_ADDR_0BITS 0
  119. #define SFC_CMD_ADDR_24BITS 1
  120. #define SFC_CMD_ADDR_32BITS 2
  121. #define SFC_CMD_ADDR_XBITS 3
  122. #define SFC_CMD_TRAN_BYTES_SHIFT 16
  123. #define SFC_CMD_CS_SHIFT 30
  124. /* Address */
  125. #define SFC_ADDR 0x104
  126. /* Data */
  127. #define SFC_DATA 0x108
  128. /* The controller and documentation reports that it supports up to 4 CS
  129. * devices (0-3), however I have only been able to test a single CS (CS 0)
  130. * due to the configuration of my device.
  131. */
  132. #define SFC_MAX_CHIPSELECT_NUM 4
  133. /* The SFC can transfer max 16KB - 1 at one time
  134. * we set it to 15.5KB here for alignment.
  135. */
  136. #define SFC_MAX_IOSIZE_VER3 (512 * 31)
  137. #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
  138. /* DMA is only enabled for large data transmission */
  139. #define SFC_DMA_TRANS_THRETHOLD (0x40)
  140. /* Maximum clock values from datasheet suggest keeping clock value under
  141. * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
  142. * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
  143. */
  144. #define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
  145. #define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
  146. #define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
  147. struct rockchip_sfc {
  148. void __iomem *regbase;
  149. struct clk hclk;
  150. struct clk clk;
  151. u32 max_freq;
  152. u32 speed;
  153. bool use_dma;
  154. u32 max_iosize;
  155. u16 version;
  156. };
  157. static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
  158. {
  159. int err;
  160. u32 status;
  161. writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
  162. err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
  163. !(status & SFC_RCVR_RESET),
  164. 1000000);
  165. if (err)
  166. printf("SFC reset never finished\n");
  167. /* Still need to clear the masked interrupt from RISR */
  168. writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
  169. debug("reset\n");
  170. return err;
  171. }
  172. static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
  173. {
  174. return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
  175. }
  176. static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
  177. {
  178. if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
  179. return SFC_MAX_IOSIZE_VER4;
  180. return SFC_MAX_IOSIZE_VER3;
  181. }
  182. static int rockchip_sfc_init(struct rockchip_sfc *sfc)
  183. {
  184. writel(0, sfc->regbase + SFC_CTRL);
  185. if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
  186. writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
  187. return 0;
  188. }
  189. static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
  190. {
  191. struct rockchip_sfc *sfc = dev_get_plat(bus);
  192. sfc->regbase = dev_read_addr_ptr(bus);
  193. if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
  194. sfc->use_dma = false;
  195. else
  196. sfc->use_dma = true;
  197. #if CONFIG_IS_ENABLED(CLK)
  198. int ret;
  199. ret = clk_get_by_index(bus, 0, &sfc->clk);
  200. if (ret < 0) {
  201. printf("Could not get clock for %s: %d\n", bus->name, ret);
  202. return ret;
  203. }
  204. ret = clk_get_by_index(bus, 1, &sfc->hclk);
  205. if (ret < 0) {
  206. printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
  207. return ret;
  208. }
  209. #endif
  210. return 0;
  211. }
  212. static int rockchip_sfc_probe(struct udevice *bus)
  213. {
  214. struct rockchip_sfc *sfc = dev_get_plat(bus);
  215. int ret;
  216. #if CONFIG_IS_ENABLED(CLK)
  217. ret = clk_enable(&sfc->hclk);
  218. if (ret)
  219. debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
  220. ret = clk_enable(&sfc->clk);
  221. if (ret)
  222. debug("Enable clock fail for %s: %d\n", bus->name, ret);
  223. ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
  224. if (ret)
  225. debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
  226. #endif
  227. ret = rockchip_sfc_init(sfc);
  228. if (ret)
  229. goto err_init;
  230. sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
  231. sfc->version = rockchip_sfc_get_version(sfc);
  232. sfc->speed = SFC_DEFAULT_SPEED_HZ;
  233. return 0;
  234. err_init:
  235. #if CONFIG_IS_ENABLED(CLK)
  236. clk_disable(&sfc->clk);
  237. clk_disable(&sfc->hclk);
  238. #endif
  239. return ret;
  240. }
  241. static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
  242. {
  243. u32 fsr = readl(sfc->regbase + SFC_FSR);
  244. int level;
  245. if (wr)
  246. level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
  247. else
  248. level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
  249. return level;
  250. }
  251. static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
  252. {
  253. unsigned long tbase = get_timer(0);
  254. int level;
  255. while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
  256. if (get_timer(tbase) > timeout) {
  257. debug("%s fifo timeout\n", wr ? "write" : "read");
  258. return -ETIMEDOUT;
  259. }
  260. udelay(1);
  261. }
  262. return level;
  263. }
  264. static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
  265. {
  266. if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
  267. /*
  268. * SFC not support output DUMMY cycles right after CMD cycles, so
  269. * treat it as ADDR cycles.
  270. */
  271. op->addr.nbytes = op->dummy.nbytes;
  272. op->addr.buswidth = op->dummy.buswidth;
  273. op->addr.val = 0xFFFFFFFFF;
  274. op->dummy.nbytes = 0;
  275. }
  276. }
  277. static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
  278. {
  279. unsigned long tbase;
  280. /* Wait for the DMA interrupt status */
  281. tbase = get_timer(0);
  282. while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
  283. if (get_timer(tbase) > timeout) {
  284. printf("dma timeout\n");
  285. rockchip_sfc_reset(sfc);
  286. return -ETIMEDOUT;
  287. }
  288. udelay(1);
  289. }
  290. writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
  291. return 0;
  292. }
  293. static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
  294. struct spi_slave *mem,
  295. const struct spi_mem_op *op,
  296. u32 len)
  297. {
  298. struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
  299. u32 ctrl = 0, cmd = 0;
  300. /* set CMD */
  301. cmd = op->cmd.opcode;
  302. ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
  303. /* set ADDR */
  304. if (op->addr.nbytes) {
  305. if (op->addr.nbytes == 4) {
  306. cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
  307. } else if (op->addr.nbytes == 3) {
  308. cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
  309. } else {
  310. cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
  311. writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
  312. }
  313. ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
  314. }
  315. /* set DUMMY */
  316. if (op->dummy.nbytes) {
  317. if (op->dummy.buswidth == 4)
  318. cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
  319. else if (op->dummy.buswidth == 2)
  320. cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
  321. else
  322. cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
  323. }
  324. /* set DATA */
  325. if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
  326. writel(len, sfc->regbase + SFC_LEN_EXT);
  327. else
  328. cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
  329. if (len) {
  330. if (op->data.dir == SPI_MEM_DATA_OUT)
  331. cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
  332. ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
  333. }
  334. if (!len && op->addr.nbytes)
  335. cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
  336. /* set the Controller */
  337. ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
  338. cmd |= plat->cs << SFC_CMD_CS_SHIFT;
  339. debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
  340. op->addr.nbytes, op->addr.buswidth,
  341. op->dummy.nbytes, op->dummy.buswidth);
  342. debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
  343. ctrl, cmd, op->addr.val, len);
  344. writel(ctrl, sfc->regbase + SFC_CTRL);
  345. writel(cmd, sfc->regbase + SFC_CMD);
  346. if (op->addr.nbytes)
  347. writel(op->addr.val, sfc->regbase + SFC_ADDR);
  348. return 0;
  349. }
  350. static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
  351. {
  352. u8 bytes = len & 0x3;
  353. u32 dwords;
  354. int tx_level;
  355. u32 write_words;
  356. u32 tmp = 0;
  357. dwords = len >> 2;
  358. while (dwords) {
  359. tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
  360. if (tx_level < 0)
  361. return tx_level;
  362. write_words = min_t(u32, tx_level, dwords);
  363. writesl(sfc->regbase + SFC_DATA, buf, write_words);
  364. buf += write_words << 2;
  365. dwords -= write_words;
  366. }
  367. /* write the rest non word aligned bytes */
  368. if (bytes) {
  369. tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
  370. if (tx_level < 0)
  371. return tx_level;
  372. memcpy(&tmp, buf, bytes);
  373. writel(tmp, sfc->regbase + SFC_DATA);
  374. }
  375. return len;
  376. }
  377. static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
  378. {
  379. u8 bytes = len & 0x3;
  380. u32 dwords;
  381. u8 read_words;
  382. int rx_level;
  383. int tmp;
  384. /* word aligned access only */
  385. dwords = len >> 2;
  386. while (dwords) {
  387. rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
  388. if (rx_level < 0)
  389. return rx_level;
  390. read_words = min_t(u32, rx_level, dwords);
  391. readsl(sfc->regbase + SFC_DATA, buf, read_words);
  392. buf += read_words << 2;
  393. dwords -= read_words;
  394. }
  395. /* read the rest non word aligned bytes */
  396. if (bytes) {
  397. rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
  398. if (rx_level < 0)
  399. return rx_level;
  400. tmp = readl(sfc->regbase + SFC_DATA);
  401. memcpy(buf, &tmp, bytes);
  402. }
  403. return len;
  404. }
  405. static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
  406. {
  407. writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
  408. writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
  409. writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
  410. return len;
  411. }
  412. static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
  413. const struct spi_mem_op *op, u32 len)
  414. {
  415. debug("xfer_poll len=%x\n", len);
  416. if (op->data.dir == SPI_MEM_DATA_OUT)
  417. return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
  418. else
  419. return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
  420. }
  421. static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
  422. const struct spi_mem_op *op, u32 len)
  423. {
  424. struct bounce_buffer bb;
  425. unsigned int bb_flags;
  426. void *dma_buf;
  427. int ret;
  428. debug("xfer_dma len=%x\n", len);
  429. if (op->data.dir == SPI_MEM_DATA_OUT) {
  430. dma_buf = (void *)op->data.buf.out;
  431. bb_flags = GEN_BB_READ;
  432. } else {
  433. dma_buf = (void *)op->data.buf.in;
  434. bb_flags = GEN_BB_WRITE;
  435. }
  436. ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
  437. if (ret)
  438. return ret;
  439. ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
  440. rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
  441. bounce_buffer_stop(&bb);
  442. return ret;
  443. }
  444. static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
  445. {
  446. unsigned long tbase = get_timer(0);
  447. int ret = 0;
  448. u32 timeout = timeout_us;
  449. while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
  450. if (get_timer(tbase) > timeout) {
  451. printf("wait sfc idle timeout\n");
  452. rockchip_sfc_reset(sfc);
  453. return -ETIMEDOUT;
  454. }
  455. udelay(1);
  456. }
  457. return ret;
  458. }
  459. static int rockchip_sfc_exec_op(struct spi_slave *mem,
  460. const struct spi_mem_op *op)
  461. {
  462. struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
  463. u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
  464. int ret;
  465. #if CONFIG_IS_ENABLED(CLK)
  466. if (unlikely(mem->max_hz != sfc->speed)) {
  467. ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
  468. (uint)SFC_MAX_SPEED_HZ));
  469. if (ret < 0) {
  470. printf("set_freq=%dHz fail, check if it's the cru support level\n",
  471. mem->max_hz);
  472. return ret;
  473. }
  474. sfc->max_freq = mem->max_hz;
  475. sfc->speed = mem->max_hz;
  476. debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
  477. }
  478. #endif
  479. rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
  480. rockchip_sfc_xfer_setup(sfc, mem, op, len);
  481. if (len) {
  482. if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
  483. ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
  484. else
  485. ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
  486. if (ret != len) {
  487. printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
  488. return -EIO;
  489. }
  490. }
  491. return rockchip_sfc_xfer_done(sfc, 100000);
  492. }
  493. static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
  494. {
  495. struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
  496. op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
  497. return 0;
  498. }
  499. static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
  500. {
  501. /* We set up speed later for each transmission.
  502. */
  503. return 0;
  504. }
  505. static int rockchip_sfc_set_mode(struct udevice *bus, uint mode)
  506. {
  507. return 0;
  508. }
  509. static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
  510. .adjust_op_size = rockchip_sfc_adjust_op_size,
  511. .exec_op = rockchip_sfc_exec_op,
  512. };
  513. static const struct dm_spi_ops rockchip_sfc_ops = {
  514. .mem_ops = &rockchip_sfc_mem_ops,
  515. .set_speed = rockchip_sfc_set_speed,
  516. .set_mode = rockchip_sfc_set_mode,
  517. };
  518. static const struct udevice_id rockchip_sfc_ids[] = {
  519. { .compatible = "rockchip,sfc"},
  520. {},
  521. };
  522. U_BOOT_DRIVER(rockchip_sfc_driver) = {
  523. .name = "rockchip_sfc",
  524. .id = UCLASS_SPI,
  525. .of_match = rockchip_sfc_ids,
  526. .ops = &rockchip_sfc_ops,
  527. .of_to_plat = rockchip_sfc_ofdata_to_platdata,
  528. .plat_auto = sizeof(struct rockchip_sfc),
  529. .probe = rockchip_sfc_probe,
  530. };