renesas_rpc_spi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Renesas RCar Gen3 RPC QSPI driver
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <dm/of_access.h>
  13. #include <dt-structs.h>
  14. #include <errno.h>
  15. #include <linux/bitops.h>
  16. #include <linux/bug.h>
  17. #include <linux/errno.h>
  18. #include <spi.h>
  19. #include <wait_bit.h>
  20. #define RPC_CMNCR 0x0000 /* R/W */
  21. #define RPC_CMNCR_MD BIT(31)
  22. #define RPC_CMNCR_SFDE BIT(24)
  23. #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  24. #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  25. #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  26. #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  27. #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
  28. RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
  29. #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
  30. #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
  31. #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
  32. #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
  33. RPC_CMNCR_IO3FV(3))
  34. #define RPC_CMNCR_CPHAT BIT(6)
  35. #define RPC_CMNCR_CPHAR BIT(5)
  36. #define RPC_CMNCR_SSLP BIT(4)
  37. #define RPC_CMNCR_CPOL BIT(3)
  38. #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
  39. #define RPC_SSLDR 0x0004 /* R/W */
  40. #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
  41. #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
  42. #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
  43. #define RPC_DRCR 0x000C /* R/W */
  44. #define RPC_DRCR_SSLN BIT(24)
  45. #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
  46. #define RPC_DRCR_RCF BIT(9)
  47. #define RPC_DRCR_RBE BIT(8)
  48. #define RPC_DRCR_SSLE BIT(0)
  49. #define RPC_DRCMR 0x0010 /* R/W */
  50. #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
  51. #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
  52. #define RPC_DREAR 0x0014 /* R/W */
  53. #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
  54. #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
  55. #define RPC_DROPR 0x0018 /* R/W */
  56. #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
  57. #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
  58. #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
  59. #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
  60. #define RPC_DRENR 0x001C /* R/W */
  61. #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
  62. #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
  63. #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
  64. #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
  65. #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
  66. #define RPC_DRENR_DME BIT(15)
  67. #define RPC_DRENR_CDE BIT(14)
  68. #define RPC_DRENR_OCDE BIT(12)
  69. #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
  70. #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
  71. #define RPC_SMCR 0x0020 /* R/W */
  72. #define RPC_SMCR_SSLKP BIT(8)
  73. #define RPC_SMCR_SPIRE BIT(2)
  74. #define RPC_SMCR_SPIWE BIT(1)
  75. #define RPC_SMCR_SPIE BIT(0)
  76. #define RPC_SMCMR 0x0024 /* R/W */
  77. #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
  78. #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
  79. #define RPC_SMADR 0x0028 /* R/W */
  80. #define RPC_SMOPR 0x002C /* R/W */
  81. #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
  82. #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
  83. #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
  84. #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
  85. #define RPC_SMENR 0x0030 /* R/W */
  86. #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
  87. #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
  88. #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
  89. #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
  90. #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
  91. #define RPC_SMENR_DME BIT(15)
  92. #define RPC_SMENR_CDE BIT(14)
  93. #define RPC_SMENR_OCDE BIT(12)
  94. #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
  95. #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
  96. #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
  97. #define RPC_SMRDR0 0x0038 /* R */
  98. #define RPC_SMRDR1 0x003C /* R */
  99. #define RPC_SMWDR0 0x0040 /* R/W */
  100. #define RPC_SMWDR1 0x0044 /* R/W */
  101. #define RPC_CMNSR 0x0048 /* R */
  102. #define RPC_CMNSR_SSLF BIT(1)
  103. #define RPC_CMNSR_TEND BIT(0)
  104. #define RPC_DRDMCR 0x0058 /* R/W */
  105. #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
  106. #define RPC_DRDRENR 0x005C /* R/W */
  107. #define RPC_DRDRENR_HYPE (0x5 << 12)
  108. #define RPC_DRDRENR_ADDRE BIT(8)
  109. #define RPC_DRDRENR_OPDRE BIT(4)
  110. #define RPC_DRDRENR_DRDRE BIT(0)
  111. #define RPC_SMDMCR 0x0060 /* R/W */
  112. #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
  113. #define RPC_SMDRENR 0x0064 /* R/W */
  114. #define RPC_SMDRENR_HYPE (0x5 << 12)
  115. #define RPC_SMDRENR_ADDRE BIT(8)
  116. #define RPC_SMDRENR_OPDRE BIT(4)
  117. #define RPC_SMDRENR_SPIDRE BIT(0)
  118. #define RPC_PHYCNT 0x007C /* R/W */
  119. #define RPC_PHYCNT_CAL BIT(31)
  120. #define PRC_PHYCNT_OCTA_AA BIT(22)
  121. #define PRC_PHYCNT_OCTA_SA BIT(23)
  122. #define PRC_PHYCNT_EXDS BIT(21)
  123. #define RPC_PHYCNT_OCT BIT(20)
  124. #define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
  125. #define RPC_PHYCNT_WBUF2 BIT(4)
  126. #define RPC_PHYCNT_WBUF BIT(2)
  127. #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
  128. #define RPC_PHYINT 0x0088 /* R/W */
  129. #define RPC_PHYINT_RSTEN BIT(18)
  130. #define RPC_PHYINT_WPEN BIT(17)
  131. #define RPC_PHYINT_INTEN BIT(16)
  132. #define RPC_PHYINT_RST BIT(2)
  133. #define RPC_PHYINT_WP BIT(1)
  134. #define RPC_PHYINT_INT BIT(0)
  135. #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
  136. #define RPC_WBUF_SIZE 0x100
  137. DECLARE_GLOBAL_DATA_PTR;
  138. struct rpc_spi_plat {
  139. fdt_addr_t regs;
  140. fdt_addr_t extr;
  141. s32 freq; /* Default clock freq, -1 for none */
  142. };
  143. struct rpc_spi_priv {
  144. fdt_addr_t regs;
  145. fdt_addr_t extr;
  146. struct clk clk;
  147. u8 cmdcopy[8];
  148. u32 cmdlen;
  149. bool cmdstarted;
  150. };
  151. static int rpc_spi_wait_sslf(struct udevice *dev)
  152. {
  153. struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
  154. return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF,
  155. false, 1000, false);
  156. }
  157. static int rpc_spi_wait_tend(struct udevice *dev)
  158. {
  159. struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
  160. return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND,
  161. true, 1000, false);
  162. }
  163. static void rpc_spi_flush_read_cache(struct udevice *dev)
  164. {
  165. struct udevice *bus = dev->parent;
  166. struct rpc_spi_priv *priv = dev_get_priv(bus);
  167. /* Flush read cache */
  168. writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) |
  169. RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE,
  170. priv->regs + RPC_DRCR);
  171. readl(priv->regs + RPC_DRCR);
  172. }
  173. static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
  174. {
  175. struct udevice *bus = dev->parent;
  176. struct rpc_spi_priv *priv = dev_get_priv(bus);
  177. /*
  178. * NOTE: The 0x260 are undocumented bits, but they must be set.
  179. * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
  180. * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
  181. * RPC_PHYCNT_STRTIM shall be 6.
  182. */
  183. writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
  184. priv->regs + RPC_PHYCNT);
  185. writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
  186. RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
  187. priv->regs + RPC_CMNCR);
  188. writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) |
  189. RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR);
  190. rpc_spi_flush_read_cache(dev);
  191. return 0;
  192. }
  193. static int rpc_spi_release_bus(struct udevice *dev)
  194. {
  195. struct udevice *bus = dev->parent;
  196. struct rpc_spi_priv *priv = dev_get_priv(bus);
  197. /* NOTE: The 0x260 are undocumented bits, but they must be set. */
  198. writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
  199. rpc_spi_flush_read_cache(dev);
  200. return 0;
  201. }
  202. static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
  203. const void *dout, void *din, unsigned long flags)
  204. {
  205. struct udevice *bus = dev->parent;
  206. struct rpc_spi_priv *priv = dev_get_priv(bus);
  207. u32 wlen = dout ? (bitlen / 8) : 0;
  208. u32 rlen = din ? (bitlen / 8) : 0;
  209. u32 wloop = DIV_ROUND_UP(wlen, 4);
  210. u32 smenr, smcr, offset;
  211. int ret = 0;
  212. if (!priv->cmdstarted) {
  213. if (!wlen || rlen)
  214. BUG();
  215. memcpy(priv->cmdcopy, dout, wlen);
  216. priv->cmdlen = wlen;
  217. /* Command transfer start */
  218. priv->cmdstarted = true;
  219. if (!(flags & SPI_XFER_END))
  220. return 0;
  221. }
  222. offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
  223. (priv->cmdcopy[3] << 0);
  224. smenr = 0;
  225. if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
  226. if (wlen && flags == SPI_XFER_END)
  227. smenr = RPC_SMENR_SPIDE(0xf);
  228. rpc_spi_claim_bus(dev, true);
  229. writel(0, priv->regs + RPC_SMCR);
  230. if (priv->cmdlen >= 1) { /* Command(1) */
  231. writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
  232. priv->regs + RPC_SMCMR);
  233. smenr |= RPC_SMENR_CDE;
  234. } else {
  235. writel(0, priv->regs + RPC_SMCMR);
  236. }
  237. if (priv->cmdlen >= 4) { /* Address(3) */
  238. writel(offset, priv->regs + RPC_SMADR);
  239. smenr |= RPC_SMENR_ADE(7);
  240. } else {
  241. writel(0, priv->regs + RPC_SMADR);
  242. }
  243. if (priv->cmdlen >= 5) { /* Dummy(n) */
  244. writel(8 * (priv->cmdlen - 4) - 1,
  245. priv->regs + RPC_SMDMCR);
  246. smenr |= RPC_SMENR_DME;
  247. } else {
  248. writel(0, priv->regs + RPC_SMDMCR);
  249. }
  250. writel(0, priv->regs + RPC_SMOPR);
  251. writel(0, priv->regs + RPC_SMDRENR);
  252. if (wlen && flags == SPI_XFER_END) {
  253. u32 *datout = (u32 *)dout;
  254. while (wloop--) {
  255. smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
  256. if (wloop >= 1)
  257. smcr |= RPC_SMCR_SSLKP;
  258. writel(smenr, priv->regs + RPC_SMENR);
  259. writel(*datout, priv->regs + RPC_SMWDR0);
  260. writel(smcr, priv->regs + RPC_SMCR);
  261. ret = rpc_spi_wait_tend(dev);
  262. if (ret)
  263. goto err;
  264. datout++;
  265. smenr = RPC_SMENR_SPIDE(0xf);
  266. }
  267. ret = rpc_spi_wait_sslf(dev);
  268. } else {
  269. writel(smenr, priv->regs + RPC_SMENR);
  270. writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
  271. ret = rpc_spi_wait_tend(dev);
  272. }
  273. } else { /* Read data only, using DRx ext access */
  274. rpc_spi_claim_bus(dev, false);
  275. if (priv->cmdlen >= 1) { /* Command(1) */
  276. writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
  277. priv->regs + RPC_DRCMR);
  278. smenr |= RPC_DRENR_CDE;
  279. } else {
  280. writel(0, priv->regs + RPC_DRCMR);
  281. }
  282. if (priv->cmdlen >= 4) /* Address(3) */
  283. smenr |= RPC_DRENR_ADE(7);
  284. if (priv->cmdlen >= 5) { /* Dummy(n) */
  285. writel(8 * (priv->cmdlen - 4) - 1,
  286. priv->regs + RPC_DRDMCR);
  287. smenr |= RPC_DRENR_DME;
  288. } else {
  289. writel(0, priv->regs + RPC_DRDMCR);
  290. }
  291. writel(0, priv->regs + RPC_DROPR);
  292. writel(smenr, priv->regs + RPC_DRENR);
  293. if (rlen)
  294. memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
  295. else
  296. readl(priv->extr); /* Dummy read */
  297. }
  298. err:
  299. priv->cmdstarted = false;
  300. rpc_spi_release_bus(dev);
  301. return ret;
  302. }
  303. static int rpc_spi_set_speed(struct udevice *bus, uint speed)
  304. {
  305. /* This is a SPI NOR controller, do nothing. */
  306. return 0;
  307. }
  308. static int rpc_spi_set_mode(struct udevice *bus, uint mode)
  309. {
  310. /* This is a SPI NOR controller, do nothing. */
  311. return 0;
  312. }
  313. static int rpc_spi_bind(struct udevice *parent)
  314. {
  315. const void *fdt = gd->fdt_blob;
  316. ofnode node;
  317. int ret, off;
  318. /*
  319. * Check if there are any SPI NOR child nodes, if so, bind as
  320. * this controller will be operated in SPI mode.
  321. */
  322. dev_for_each_subnode(node, parent) {
  323. off = ofnode_to_offset(node);
  324. ret = fdt_node_check_compatible(fdt, off, "spi-flash");
  325. if (!ret)
  326. return 0;
  327. ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
  328. if (!ret)
  329. return 0;
  330. }
  331. return -ENODEV;
  332. }
  333. static int rpc_spi_probe(struct udevice *dev)
  334. {
  335. struct rpc_spi_plat *plat = dev_get_plat(dev);
  336. struct rpc_spi_priv *priv = dev_get_priv(dev);
  337. priv->regs = plat->regs;
  338. priv->extr = plat->extr;
  339. #if CONFIG_IS_ENABLED(CLK)
  340. clk_enable(&priv->clk);
  341. #endif
  342. return 0;
  343. }
  344. static int rpc_spi_of_to_plat(struct udevice *bus)
  345. {
  346. struct rpc_spi_plat *plat = dev_get_plat(bus);
  347. plat->regs = dev_read_addr_index(bus, 0);
  348. plat->extr = dev_read_addr_index(bus, 1);
  349. #if CONFIG_IS_ENABLED(CLK)
  350. struct rpc_spi_priv *priv = dev_get_priv(bus);
  351. int ret;
  352. ret = clk_get_by_index(bus, 0, &priv->clk);
  353. if (ret < 0) {
  354. printf("%s: Could not get clock for %s: %d\n",
  355. __func__, bus->name, ret);
  356. return ret;
  357. }
  358. #endif
  359. plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
  360. return 0;
  361. }
  362. static const struct dm_spi_ops rpc_spi_ops = {
  363. .xfer = rpc_spi_xfer,
  364. .set_speed = rpc_spi_set_speed,
  365. .set_mode = rpc_spi_set_mode,
  366. };
  367. static const struct udevice_id rpc_spi_ids[] = {
  368. { .compatible = "renesas,rpc-r7s72100" },
  369. { .compatible = "renesas,rpc-r8a7795" },
  370. { .compatible = "renesas,rpc-r8a7796" },
  371. { .compatible = "renesas,rpc-r8a77965" },
  372. { .compatible = "renesas,rpc-r8a77970" },
  373. { .compatible = "renesas,rpc-r8a77995" },
  374. { .compatible = "renesas,rcar-gen3-rpc" },
  375. { }
  376. };
  377. U_BOOT_DRIVER(rpc_spi) = {
  378. .name = "rpc_spi",
  379. .id = UCLASS_SPI,
  380. .of_match = rpc_spi_ids,
  381. .ops = &rpc_spi_ops,
  382. .of_to_plat = rpc_spi_of_to_plat,
  383. .plat_auto = sizeof(struct rpc_spi_plat),
  384. .priv_auto = sizeof(struct rpc_spi_priv),
  385. .bind = rpc_spi_bind,
  386. .probe = rpc_spi_probe,
  387. };