pl022_spi.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012
  4. * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
  5. *
  6. * (C) Copyright 2018
  7. * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
  8. *
  9. * Driver for ARM PL022 SPI Controller.
  10. */
  11. #include <clk.h>
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <dm/platform_data/spi_pl022.h>
  15. #include <linux/io.h>
  16. #include <asm/global_data.h>
  17. #include <spi.h>
  18. #define SSP_CR0 0x000
  19. #define SSP_CR1 0x004
  20. #define SSP_DR 0x008
  21. #define SSP_SR 0x00C
  22. #define SSP_CPSR 0x010
  23. #define SSP_IMSC 0x014
  24. #define SSP_RIS 0x018
  25. #define SSP_MIS 0x01C
  26. #define SSP_ICR 0x020
  27. #define SSP_DMACR 0x024
  28. #define SSP_CSR 0x030 /* vendor extension */
  29. #define SSP_ITCR 0x080
  30. #define SSP_ITIP 0x084
  31. #define SSP_ITOP 0x088
  32. #define SSP_TDR 0x08C
  33. #define SSP_PID0 0xFE0
  34. #define SSP_PID1 0xFE4
  35. #define SSP_PID2 0xFE8
  36. #define SSP_PID3 0xFEC
  37. #define SSP_CID0 0xFF0
  38. #define SSP_CID1 0xFF4
  39. #define SSP_CID2 0xFF8
  40. #define SSP_CID3 0xFFC
  41. /* SSP Control Register 0 - SSP_CR0 */
  42. #define SSP_CR0_SPO (0x1 << 6)
  43. #define SSP_CR0_SPH (0x1 << 7)
  44. #define SSP_CR0_BIT_MODE(x) ((x) - 1)
  45. #define SSP_SCR_MIN (0x00)
  46. #define SSP_SCR_MAX (0xFF)
  47. #define SSP_SCR_SHFT 8
  48. #define DFLT_CLKRATE 2
  49. /* SSP Control Register 1 - SSP_CR1 */
  50. #define SSP_CR1_MASK_SSE (0x1 << 1)
  51. #define SSP_CPSR_MIN (0x02)
  52. #define SSP_CPSR_MAX (0xFE)
  53. #define DFLT_PRESCALE (0x40)
  54. /* SSP Status Register - SSP_SR */
  55. #define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
  56. #define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
  57. #define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
  58. #define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
  59. #define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
  60. struct pl022_spi_slave {
  61. void *base;
  62. unsigned int freq;
  63. };
  64. /*
  65. * ARM PL022 exists in different 'flavors'.
  66. * This drivers currently support the standard variant (0x00041022), that has a
  67. * 16bit wide and 8 locations deep TX/RX FIFO.
  68. */
  69. static int pl022_is_supported(struct pl022_spi_slave *ps)
  70. {
  71. /* PL022 version is 0x00041022 */
  72. if ((readw(ps->base + SSP_PID0) == 0x22) &&
  73. (readw(ps->base + SSP_PID1) == 0x10) &&
  74. ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
  75. (readw(ps->base + SSP_PID3) == 0x00))
  76. return 1;
  77. return 0;
  78. }
  79. static int pl022_spi_probe(struct udevice *bus)
  80. {
  81. struct pl022_spi_pdata *plat = dev_get_plat(bus);
  82. struct pl022_spi_slave *ps = dev_get_priv(bus);
  83. ps->base = ioremap(plat->addr, plat->size);
  84. ps->freq = plat->freq;
  85. /* Check the PL022 version */
  86. if (!pl022_is_supported(ps))
  87. return -ENOTSUPP;
  88. /* 8 bits per word, high polarity and default clock rate */
  89. writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
  90. writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
  91. return 0;
  92. }
  93. static void flush(struct pl022_spi_slave *ps)
  94. {
  95. do {
  96. while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
  97. readw(ps->base + SSP_DR);
  98. } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
  99. }
  100. static int pl022_spi_claim_bus(struct udevice *dev)
  101. {
  102. struct udevice *bus = dev->parent;
  103. struct pl022_spi_slave *ps = dev_get_priv(bus);
  104. u16 reg;
  105. /* Enable the SPI hardware */
  106. reg = readw(ps->base + SSP_CR1);
  107. reg |= SSP_CR1_MASK_SSE;
  108. writew(reg, ps->base + SSP_CR1);
  109. flush(ps);
  110. return 0;
  111. }
  112. static int pl022_spi_release_bus(struct udevice *dev)
  113. {
  114. struct udevice *bus = dev->parent;
  115. struct pl022_spi_slave *ps = dev_get_priv(bus);
  116. u16 reg;
  117. flush(ps);
  118. /* Disable the SPI hardware */
  119. reg = readw(ps->base + SSP_CR1);
  120. reg &= ~SSP_CR1_MASK_SSE;
  121. writew(reg, ps->base + SSP_CR1);
  122. return 0;
  123. }
  124. static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
  125. const void *dout, void *din, unsigned long flags)
  126. {
  127. struct udevice *bus = dev->parent;
  128. struct pl022_spi_slave *ps = dev_get_priv(bus);
  129. u32 len_tx = 0, len_rx = 0, len;
  130. u32 ret = 0;
  131. const u8 *txp = dout;
  132. u8 *rxp = din, value;
  133. if (bitlen == 0)
  134. /* Finish any previously submitted transfers */
  135. return 0;
  136. /*
  137. * TODO: The controller can do non-multiple-of-8 bit
  138. * transfers, but this driver currently doesn't support it.
  139. *
  140. * It's also not clear how such transfers are supposed to be
  141. * represented as a stream of bytes...this is a limitation of
  142. * the current SPI interface.
  143. */
  144. if (bitlen % 8) {
  145. /* Errors always terminate an ongoing transfer */
  146. flags |= SPI_XFER_END;
  147. return -1;
  148. }
  149. len = bitlen / 8;
  150. while (len_tx < len) {
  151. if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
  152. value = txp ? *txp++ : 0;
  153. writew(value, ps->base + SSP_DR);
  154. len_tx++;
  155. }
  156. if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
  157. value = readw(ps->base + SSP_DR);
  158. if (rxp)
  159. *rxp++ = value;
  160. len_rx++;
  161. }
  162. }
  163. while (len_rx < len_tx) {
  164. if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
  165. value = readw(ps->base + SSP_DR);
  166. if (rxp)
  167. *rxp++ = value;
  168. len_rx++;
  169. }
  170. }
  171. return ret;
  172. }
  173. static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
  174. {
  175. return rate / (cpsdvsr * (1 + scr));
  176. }
  177. static int pl022_spi_set_speed(struct udevice *bus, uint speed)
  178. {
  179. struct pl022_spi_slave *ps = dev_get_priv(bus);
  180. u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
  181. best_cpsr = cpsr;
  182. u32 min, max, best_freq = 0, tmp;
  183. u32 rate = ps->freq;
  184. bool found = false;
  185. max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
  186. min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
  187. if (speed > max || speed < min) {
  188. pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
  189. speed, min, max);
  190. return -EINVAL;
  191. }
  192. while (cpsr <= SSP_CPSR_MAX && !found) {
  193. while (scr <= SSP_SCR_MAX) {
  194. tmp = spi_rate(rate, cpsr, scr);
  195. if (abs(speed - tmp) < abs(speed - best_freq)) {
  196. best_freq = tmp;
  197. best_cpsr = cpsr;
  198. best_scr = scr;
  199. if (tmp == speed) {
  200. found = true;
  201. break;
  202. }
  203. }
  204. scr++;
  205. }
  206. cpsr += 2;
  207. scr = SSP_SCR_MIN;
  208. }
  209. writew(best_cpsr, ps->base + SSP_CPSR);
  210. cr0 = readw(ps->base + SSP_CR0);
  211. writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
  212. return 0;
  213. }
  214. static int pl022_spi_set_mode(struct udevice *bus, uint mode)
  215. {
  216. struct pl022_spi_slave *ps = dev_get_priv(bus);
  217. u16 reg;
  218. reg = readw(ps->base + SSP_CR0);
  219. reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
  220. if (mode & SPI_CPHA)
  221. reg |= SSP_CR0_SPH;
  222. if (mode & SPI_CPOL)
  223. reg |= SSP_CR0_SPO;
  224. writew(reg, ps->base + SSP_CR0);
  225. return 0;
  226. }
  227. static int pl022_cs_info(struct udevice *bus, uint cs,
  228. struct spi_cs_info *info)
  229. {
  230. return 0;
  231. }
  232. static const struct dm_spi_ops pl022_spi_ops = {
  233. .claim_bus = pl022_spi_claim_bus,
  234. .release_bus = pl022_spi_release_bus,
  235. .xfer = pl022_spi_xfer,
  236. .set_speed = pl022_spi_set_speed,
  237. .set_mode = pl022_spi_set_mode,
  238. .cs_info = pl022_cs_info,
  239. };
  240. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  241. static int pl022_spi_of_to_plat(struct udevice *bus)
  242. {
  243. struct pl022_spi_pdata *plat = dev_get_plat(bus);
  244. const void *fdt = gd->fdt_blob;
  245. int node = dev_of_offset(bus);
  246. struct clk clkdev;
  247. int ret;
  248. plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
  249. ret = clk_get_by_index(bus, 0, &clkdev);
  250. if (ret)
  251. return ret;
  252. plat->freq = clk_get_rate(&clkdev);
  253. return 0;
  254. }
  255. static const struct udevice_id pl022_spi_ids[] = {
  256. { .compatible = "arm,pl022-spi" },
  257. { }
  258. };
  259. #endif
  260. U_BOOT_DRIVER(pl022_spi) = {
  261. .name = "pl022_spi",
  262. .id = UCLASS_SPI,
  263. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  264. .of_match = pl022_spi_ids,
  265. .of_to_plat = pl022_spi_of_to_plat,
  266. #endif
  267. .ops = &pl022_spi_ops,
  268. .plat_auto = sizeof(struct pl022_spi_pdata),
  269. .priv_auto = sizeof(struct pl022_spi_slave),
  270. .probe = pl022_spi_probe,
  271. };