pic32_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Microchip PIC32 SPI controller driver.
  4. *
  5. * Copyright (c) 2015, Microchip Technology Inc.
  6. * Purna Chandra Mandal <purna.mandal@microchip.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <asm/global_data.h>
  13. #include <linux/bitops.h>
  14. #include <linux/compat.h>
  15. #include <malloc.h>
  16. #include <spi.h>
  17. #include <asm/types.h>
  18. #include <asm/io.h>
  19. #include <asm/gpio.h>
  20. #include <dt-bindings/clock/microchip,clock.h>
  21. #include <mach/pic32.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* PIC32 SPI controller registers */
  24. struct pic32_reg_spi {
  25. struct pic32_reg_atomic ctrl;
  26. struct pic32_reg_atomic status;
  27. struct pic32_reg_atomic buf;
  28. struct pic32_reg_atomic baud;
  29. struct pic32_reg_atomic ctrl2;
  30. };
  31. /* Bit fields in SPI Control Register */
  32. #define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
  33. #define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
  34. #define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
  35. #define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
  36. #define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
  37. #define PIC32_SPI_CTRL_BPW_8 0x0
  38. #define PIC32_SPI_CTRL_BPW_16 0x1
  39. #define PIC32_SPI_CTRL_BPW_32 0x2
  40. #define PIC32_SPI_CTRL_BPW_SHIFT 10
  41. #define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
  42. #define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
  43. #define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
  44. #define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
  45. #define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
  46. /* Bit fields in SPI Status Register */
  47. #define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
  48. #define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
  49. #define PIC32_SPI_STAT_TF_LVL_SHIFT 16
  50. #define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
  51. #define PIC32_SPI_STAT_RF_LVL_SHIFT 24
  52. /* Bit fields in SPI Baud Register */
  53. #define PIC32_SPI_BAUD_MASK 0x1ff
  54. struct pic32_spi_priv {
  55. struct pic32_reg_spi *regs;
  56. u32 fifo_depth; /* FIFO depth in bytes */
  57. u32 fifo_n_word; /* FIFO depth in words */
  58. struct gpio_desc cs_gpio;
  59. /* Current SPI slave specific */
  60. ulong clk_rate;
  61. u32 speed_hz; /* spi-clk rate */
  62. int mode;
  63. /* Current message/transfer state */
  64. const void *tx;
  65. const void *tx_end;
  66. const void *rx;
  67. const void *rx_end;
  68. u32 len;
  69. /* SPI FiFo accessor */
  70. void (*rx_fifo)(struct pic32_spi_priv *);
  71. void (*tx_fifo)(struct pic32_spi_priv *);
  72. };
  73. static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
  74. {
  75. writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
  76. }
  77. static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
  78. {
  79. writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
  80. }
  81. static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
  82. {
  83. u32 sr = readl(&priv->regs->status.raw);
  84. return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
  85. }
  86. static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
  87. {
  88. u32 sr = readl(&priv->regs->status.raw);
  89. return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
  90. }
  91. /* Return the max entries we can fill into tx fifo */
  92. static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
  93. {
  94. u32 tx_left, tx_room, rxtx_gap;
  95. tx_left = (priv->tx_end - priv->tx) / n_bytes;
  96. tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
  97. rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
  98. rxtx_gap /= n_bytes;
  99. return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
  100. }
  101. /* Return the max entries we should read out of rx fifo */
  102. static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
  103. {
  104. u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
  105. return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
  106. }
  107. #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
  108. static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
  109. { \
  110. __type val; \
  111. u32 mx = pic32_rx_max(priv, sizeof(__type)); \
  112. \
  113. for (; mx; mx--) { \
  114. val = read##__bwl(&priv->regs->buf.raw); \
  115. if (priv->rx_end - priv->len) \
  116. *(__type *)(priv->rx) = val; \
  117. priv->rx += sizeof(__type); \
  118. } \
  119. } \
  120. \
  121. static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
  122. { \
  123. __type val; \
  124. u32 mx = pic32_tx_max(priv, sizeof(__type)); \
  125. \
  126. for (; mx ; mx--) { \
  127. val = (__type) ~0U; \
  128. if (priv->tx_end - priv->len) \
  129. val = *(__type *)(priv->tx); \
  130. write##__bwl(val, &priv->regs->buf.raw); \
  131. priv->tx += sizeof(__type); \
  132. } \
  133. }
  134. BUILD_SPI_FIFO_RW(byte, u8, b);
  135. BUILD_SPI_FIFO_RW(word, u16, w);
  136. BUILD_SPI_FIFO_RW(dword, u32, l);
  137. static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
  138. unsigned int wordlen)
  139. {
  140. u32 bits_per_word;
  141. u32 val;
  142. switch (wordlen) {
  143. case 8:
  144. priv->rx_fifo = pic32_spi_rx_byte;
  145. priv->tx_fifo = pic32_spi_tx_byte;
  146. bits_per_word = PIC32_SPI_CTRL_BPW_8;
  147. break;
  148. case 16:
  149. priv->rx_fifo = pic32_spi_rx_word;
  150. priv->tx_fifo = pic32_spi_tx_word;
  151. bits_per_word = PIC32_SPI_CTRL_BPW_16;
  152. break;
  153. case 32:
  154. priv->rx_fifo = pic32_spi_rx_dword;
  155. priv->tx_fifo = pic32_spi_tx_dword;
  156. bits_per_word = PIC32_SPI_CTRL_BPW_32;
  157. break;
  158. default:
  159. printf("pic32-spi: unsupported wordlen\n");
  160. return -EINVAL;
  161. }
  162. /* set bits-per-word */
  163. val = readl(&priv->regs->ctrl.raw);
  164. val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
  165. val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
  166. writel(val, &priv->regs->ctrl.raw);
  167. /* calculate maximum number of words fifo can hold */
  168. priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
  169. return 0;
  170. }
  171. static int pic32_spi_claim_bus(struct udevice *slave)
  172. {
  173. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  174. /* enable chip */
  175. pic32_spi_enable(priv);
  176. return 0;
  177. }
  178. static int pic32_spi_release_bus(struct udevice *slave)
  179. {
  180. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  181. /* disable chip */
  182. pic32_spi_disable(priv);
  183. return 0;
  184. }
  185. static void spi_cs_activate(struct pic32_spi_priv *priv)
  186. {
  187. if (!dm_gpio_is_valid(&priv->cs_gpio))
  188. return;
  189. dm_gpio_set_value(&priv->cs_gpio, 1);
  190. }
  191. static void spi_cs_deactivate(struct pic32_spi_priv *priv)
  192. {
  193. if (!dm_gpio_is_valid(&priv->cs_gpio))
  194. return;
  195. dm_gpio_set_value(&priv->cs_gpio, 0);
  196. }
  197. static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
  198. const void *tx_buf, void *rx_buf,
  199. unsigned long flags)
  200. {
  201. struct dm_spi_slave_plat *slave_plat;
  202. struct udevice *bus = slave->parent;
  203. struct pic32_spi_priv *priv;
  204. int len = bitlen / 8;
  205. int ret = 0;
  206. ulong tbase;
  207. priv = dev_get_priv(bus);
  208. slave_plat = dev_get_parent_plat(slave);
  209. debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
  210. dev_seq(bus), slave_plat->cs, flags);
  211. debug("msg tx %p, rx %p submitted of %d byte(s)\n",
  212. tx_buf, rx_buf, len);
  213. /* assert cs */
  214. if (flags & SPI_XFER_BEGIN)
  215. spi_cs_activate(priv);
  216. /* set current transfer information */
  217. priv->tx = tx_buf;
  218. priv->rx = rx_buf;
  219. priv->tx_end = priv->tx + len;
  220. priv->rx_end = priv->rx + len;
  221. priv->len = len;
  222. /* transact by polling */
  223. tbase = get_timer(0);
  224. for (;;) {
  225. priv->tx_fifo(priv);
  226. priv->rx_fifo(priv);
  227. /* received sufficient data */
  228. if (priv->rx >= priv->rx_end) {
  229. ret = 0;
  230. break;
  231. }
  232. if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
  233. printf("pic32_spi: error, xfer timedout.\n");
  234. flags |= SPI_XFER_END;
  235. ret = -ETIMEDOUT;
  236. break;
  237. }
  238. }
  239. /* deassert cs */
  240. if (flags & SPI_XFER_END)
  241. spi_cs_deactivate(priv);
  242. return ret;
  243. }
  244. static int pic32_spi_set_speed(struct udevice *bus, uint speed)
  245. {
  246. struct pic32_spi_priv *priv = dev_get_priv(bus);
  247. u32 div;
  248. debug("%s: %s, speed %u\n", __func__, bus->name, speed);
  249. /* div = [clk_in / (2 * spi_clk)] - 1 */
  250. div = (priv->clk_rate / 2 / speed) - 1;
  251. div &= PIC32_SPI_BAUD_MASK;
  252. writel(div, &priv->regs->baud.raw);
  253. priv->speed_hz = speed;
  254. return 0;
  255. }
  256. static int pic32_spi_set_mode(struct udevice *bus, uint mode)
  257. {
  258. struct pic32_spi_priv *priv = dev_get_priv(bus);
  259. u32 val;
  260. debug("%s: %s, mode %d\n", __func__, bus->name, mode);
  261. /* set spi-clk mode */
  262. val = readl(&priv->regs->ctrl.raw);
  263. /* HIGH when idle */
  264. if (mode & SPI_CPOL)
  265. val |= PIC32_SPI_CTRL_CKP;
  266. else
  267. val &= ~PIC32_SPI_CTRL_CKP;
  268. /* TX at idle-to-active clk transition */
  269. if (mode & SPI_CPHA)
  270. val &= ~PIC32_SPI_CTRL_CKE;
  271. else
  272. val |= PIC32_SPI_CTRL_CKE;
  273. /* RX at end of tx */
  274. val |= PIC32_SPI_CTRL_SMP;
  275. writel(val, &priv->regs->ctrl.raw);
  276. priv->mode = mode;
  277. return 0;
  278. }
  279. static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
  280. {
  281. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  282. return pic32_spi_set_word_size(priv, wordlen);
  283. }
  284. static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
  285. {
  286. u32 val;
  287. /* disable module */
  288. pic32_spi_disable(priv);
  289. val = readl(&priv->regs->ctrl);
  290. /* enable enhanced fifo of 128bit deep */
  291. val |= PIC32_SPI_CTRL_ENHBUF;
  292. priv->fifo_depth = 16;
  293. /* disable framing mode */
  294. val &= ~PIC32_SPI_CTRL_FRMEN;
  295. /* enable master mode */
  296. val |= PIC32_SPI_CTRL_MSTEN;
  297. /* select clk source */
  298. val &= ~PIC32_SPI_CTRL_MCLKSEL;
  299. /* set manual /CS mode */
  300. val &= ~PIC32_SPI_CTRL_MSSEN;
  301. writel(val, &priv->regs->ctrl);
  302. /* clear rx overflow indicator */
  303. writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
  304. }
  305. static int pic32_spi_probe(struct udevice *bus)
  306. {
  307. struct pic32_spi_priv *priv = dev_get_priv(bus);
  308. struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
  309. int node = dev_of_offset(bus);
  310. struct udevice *clkdev;
  311. fdt_addr_t addr;
  312. fdt_size_t size;
  313. int ret;
  314. debug("%s: %d, bus: %i\n", __func__, __LINE__, dev_seq(bus));
  315. addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
  316. if (addr == FDT_ADDR_T_NONE)
  317. return -EINVAL;
  318. priv->regs = ioremap(addr, size);
  319. if (!priv->regs)
  320. return -EINVAL;
  321. dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
  322. 250000000);
  323. /* get clock rate */
  324. ret = clk_get_by_index(bus, 0, &clkdev);
  325. if (ret < 0) {
  326. printf("pic32-spi: error, clk not found\n");
  327. return ret;
  328. }
  329. priv->clk_rate = clk_get_periph_rate(clkdev, ret);
  330. /* initialize HW */
  331. pic32_spi_hw_init(priv);
  332. /* set word len */
  333. pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
  334. /* PIC32 SPI controller can automatically drive /CS during transfer
  335. * depending on fifo fill-level. /CS will stay asserted as long as
  336. * TX fifo is non-empty, else will be deasserted confirming completion
  337. * of the ongoing transfer. To avoid this sort of error we will drive
  338. * /CS manually by toggling cs-gpio pins.
  339. */
  340. ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
  341. &priv->cs_gpio, GPIOD_IS_OUT);
  342. if (ret) {
  343. printf("pic32-spi: error, cs-gpios not found\n");
  344. return ret;
  345. }
  346. return 0;
  347. }
  348. static const struct dm_spi_ops pic32_spi_ops = {
  349. .claim_bus = pic32_spi_claim_bus,
  350. .release_bus = pic32_spi_release_bus,
  351. .xfer = pic32_spi_xfer,
  352. .set_speed = pic32_spi_set_speed,
  353. .set_mode = pic32_spi_set_mode,
  354. .set_wordlen = pic32_spi_set_wordlen,
  355. };
  356. static const struct udevice_id pic32_spi_ids[] = {
  357. { .compatible = "microchip,pic32mzda-spi" },
  358. { }
  359. };
  360. U_BOOT_DRIVER(pic32_spi) = {
  361. .name = "pic32_spi",
  362. .id = UCLASS_SPI,
  363. .of_match = pic32_spi_ids,
  364. .ops = &pic32_spi_ops,
  365. .priv_auto = sizeof(struct pic32_spi_priv),
  366. .probe = pic32_spi_probe,
  367. };