mvebu_a3700_spi.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. *
  5. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <clk.h>
  13. #include <wait_bit.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <asm/gpio.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define MVEBU_SPI_A3700_XFER_RDY BIT(1)
  21. #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
  22. #define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
  23. #define MVEBU_SPI_A3700_CLK_PHA BIT(6)
  24. #define MVEBU_SPI_A3700_CLK_POL BIT(7)
  25. #define MVEBU_SPI_A3700_FIFO_EN BIT(17)
  26. #define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
  27. #define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f
  28. #define MAX_CS_COUNT 4
  29. /* SPI registers */
  30. struct spi_reg {
  31. u32 ctrl; /* 0x10600 */
  32. u32 cfg; /* 0x10604 */
  33. u32 dout; /* 0x10608 */
  34. u32 din; /* 0x1060c */
  35. };
  36. struct mvebu_spi_plat {
  37. struct spi_reg *spireg;
  38. struct clk clk;
  39. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  40. };
  41. static void spi_cs_activate(struct mvebu_spi_plat *plat, int cs)
  42. {
  43. if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
  44. dm_gpio_set_value(&plat->cs_gpios[cs], 1);
  45. else
  46. setbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
  47. }
  48. static void spi_cs_deactivate(struct mvebu_spi_plat *plat, int cs)
  49. {
  50. if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
  51. dm_gpio_set_value(&plat->cs_gpios[cs], 0);
  52. else
  53. clrbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
  54. }
  55. /**
  56. * spi_legacy_shift_byte() - triggers the real SPI transfer
  57. * @bytelen: Indicate how many bytes to transfer.
  58. * @dout: Buffer address of what to send.
  59. * @din: Buffer address of where to receive.
  60. *
  61. * This function triggers the real SPI transfer in legacy mode. It
  62. * will shift out char buffer from @dout, and shift in char buffer to
  63. * @din, if necessary.
  64. *
  65. * This function assumes that only one byte is shifted at one time.
  66. * However, it is not its responisbility to set the transfer type to
  67. * one-byte. Also, it does not guarantee that it will work if transfer
  68. * type becomes two-byte. See spi_set_legacy() for details.
  69. *
  70. * In legacy mode, simply write to the SPI_DOUT register will trigger
  71. * the transfer.
  72. *
  73. * If @dout == NULL, which means no actual data needs to be sent out,
  74. * then the function will shift out 0x00 in order to shift in data.
  75. * The XFER_RDY flag is checked every time before accessing SPI_DOUT
  76. * and SPI_DIN register.
  77. *
  78. * The number of transfers to be triggerred is decided by @bytelen.
  79. *
  80. * Return: 0 - cool
  81. * -ETIMEDOUT - XFER_RDY flag timeout
  82. */
  83. static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
  84. const void *dout, void *din)
  85. {
  86. const u8 *dout_8;
  87. u8 *din_8;
  88. int ret;
  89. /* Use 0x00 as dummy dout */
  90. const u8 dummy_dout = 0x0;
  91. u32 pending_dout = 0x0;
  92. /* dout_8: pointer of current dout */
  93. dout_8 = dout;
  94. /* din_8: pointer of current din */
  95. din_8 = din;
  96. while (bytelen) {
  97. ret = wait_for_bit_le32(&reg->ctrl,
  98. MVEBU_SPI_A3700_XFER_RDY,
  99. true,100, false);
  100. if (ret)
  101. return ret;
  102. if (dout)
  103. pending_dout = (u32)*dout_8;
  104. else
  105. pending_dout = (u32)dummy_dout;
  106. /* Trigger the xfer */
  107. writel(pending_dout, &reg->dout);
  108. if (din) {
  109. ret = wait_for_bit_le32(&reg->ctrl,
  110. MVEBU_SPI_A3700_XFER_RDY,
  111. true, 100, false);
  112. if (ret)
  113. return ret;
  114. /* Read what is transferred in */
  115. *din_8 = (u8)readl(&reg->din);
  116. }
  117. /* Don't increment the current pointer if NULL */
  118. if (dout)
  119. dout_8++;
  120. if (din)
  121. din_8++;
  122. bytelen--;
  123. }
  124. return 0;
  125. }
  126. static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
  127. const void *dout, void *din, unsigned long flags)
  128. {
  129. struct udevice *bus = dev->parent;
  130. struct mvebu_spi_plat *plat = dev_get_plat(bus);
  131. struct spi_reg *reg = plat->spireg;
  132. unsigned int bytelen;
  133. int ret;
  134. bytelen = bitlen / 8;
  135. if (dout && din)
  136. debug("This is a duplex transfer.\n");
  137. /* Activate CS */
  138. if (flags & SPI_XFER_BEGIN) {
  139. debug("SPI: activate cs.\n");
  140. spi_cs_activate(plat, spi_chip_select(dev));
  141. }
  142. /* Send and/or receive */
  143. if (dout || din) {
  144. ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
  145. if (ret)
  146. return ret;
  147. }
  148. /* Deactivate CS */
  149. if (flags & SPI_XFER_END) {
  150. ret = wait_for_bit_le32(&reg->ctrl,
  151. MVEBU_SPI_A3700_XFER_RDY,
  152. true, 100, false);
  153. if (ret)
  154. return ret;
  155. debug("SPI: deactivate cs.\n");
  156. spi_cs_deactivate(plat, spi_chip_select(dev));
  157. }
  158. return 0;
  159. }
  160. static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
  161. {
  162. struct mvebu_spi_plat *plat = dev_get_plat(bus);
  163. struct spi_reg *reg = plat->spireg;
  164. u32 data, prescale;
  165. data = readl(&reg->cfg);
  166. prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
  167. if (prescale > 0xf)
  168. prescale = 0x10 + (prescale + 1) / 2;
  169. prescale = min(prescale, 0x1fu);
  170. data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
  171. data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
  172. writel(data, &reg->cfg);
  173. return 0;
  174. }
  175. static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
  176. {
  177. struct mvebu_spi_plat *plat = dev_get_plat(bus);
  178. struct spi_reg *reg = plat->spireg;
  179. /*
  180. * Set SPI polarity
  181. * 0: Serial interface clock is low when inactive
  182. * 1: Serial interface clock is high when inactive
  183. */
  184. if (mode & SPI_CPOL)
  185. setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
  186. else
  187. clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
  188. if (mode & SPI_CPHA)
  189. setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
  190. else
  191. clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
  192. return 0;
  193. }
  194. static int mvebu_spi_probe(struct udevice *bus)
  195. {
  196. struct mvebu_spi_plat *plat = dev_get_plat(bus);
  197. struct spi_reg *reg = plat->spireg;
  198. u32 data;
  199. int ret;
  200. /*
  201. * Settings SPI controller to be working in legacy mode, which
  202. * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
  203. * for Data In.
  204. */
  205. /* Flush read/write FIFO */
  206. data = readl(&reg->cfg);
  207. writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, &reg->cfg);
  208. ret = wait_for_bit_le32(&reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
  209. false, 1000, false);
  210. if (ret)
  211. return ret;
  212. /* Disable FIFO mode */
  213. data &= ~MVEBU_SPI_A3700_FIFO_EN;
  214. /* Always shift 1 byte at a time */
  215. data &= ~MVEBU_SPI_A3700_BYTE_LEN;
  216. writel(data, &reg->cfg);
  217. /* Set up CS GPIOs in device tree, if any */
  218. if (CONFIG_IS_ENABLED(DM_GPIO) && gpio_get_list_count(bus, "cs-gpios") > 0) {
  219. int i;
  220. for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
  221. ret = gpio_request_by_name(bus, "cs-gpios", i, &plat->cs_gpios[i], 0);
  222. if (ret < 0 || !dm_gpio_is_valid(&plat->cs_gpios[i])) {
  223. /* Use the native CS function for this line */
  224. continue;
  225. }
  226. ret = dm_gpio_set_dir_flags(&plat->cs_gpios[i],
  227. GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
  228. if (ret) {
  229. dev_err(bus, "Setting cs %d error\n", i);
  230. return ret;
  231. }
  232. }
  233. }
  234. return 0;
  235. }
  236. static int mvebu_spi_of_to_plat(struct udevice *bus)
  237. {
  238. struct mvebu_spi_plat *plat = dev_get_plat(bus);
  239. int ret;
  240. plat->spireg = dev_read_addr_ptr(bus);
  241. ret = clk_get_by_index(bus, 0, &plat->clk);
  242. if (ret) {
  243. dev_err(bus, "cannot get clock\n");
  244. return ret;
  245. }
  246. return 0;
  247. }
  248. static int mvebu_spi_remove(struct udevice *bus)
  249. {
  250. struct mvebu_spi_plat *plat = dev_get_plat(bus);
  251. clk_free(&plat->clk);
  252. return 0;
  253. }
  254. static const struct dm_spi_ops mvebu_spi_ops = {
  255. .xfer = mvebu_spi_xfer,
  256. .set_speed = mvebu_spi_set_speed,
  257. .set_mode = mvebu_spi_set_mode,
  258. /*
  259. * cs_info is not needed, since we require all chip selects to be
  260. * in the device tree explicitly
  261. */
  262. };
  263. static const struct udevice_id mvebu_spi_ids[] = {
  264. { .compatible = "marvell,armada-3700-spi" },
  265. { }
  266. };
  267. U_BOOT_DRIVER(mvebu_spi) = {
  268. .name = "mvebu_spi",
  269. .id = UCLASS_SPI,
  270. .of_match = mvebu_spi_ids,
  271. .ops = &mvebu_spi_ops,
  272. .of_to_plat = mvebu_spi_of_to_plat,
  273. .plat_auto = sizeof(struct mvebu_spi_plat),
  274. .probe = mvebu_spi_probe,
  275. .remove = mvebu_spi_remove,
  276. };