mscc_bb_spi.c 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi SoCs spi driver
  4. *
  5. * Copyright (c) 2018 Microsemi Corporation
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. struct mscc_bb_priv {
  18. void __iomem *regs;
  19. u32 deactivate_delay_us;
  20. bool cs_active; /* State flag as to whether CS is asserted */
  21. int cs_num;
  22. u32 svalue; /* Value to start transfer with */
  23. u32 clk1; /* Clock value start */
  24. u32 clk2; /* Clock value 2nd phase */
  25. };
  26. /* Delay 24 instructions for this particular application */
  27. #define hold_time_delay() mscc_vcoreiii_nop_delay(3)
  28. static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
  29. {
  30. if (!priv->cs_active) {
  31. int cpha = mode & SPI_CPHA;
  32. u32 cs_value;
  33. priv->cs_num = cs;
  34. if (cpha) {
  35. /* Initial clock starts SCK=1 */
  36. priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
  37. priv->clk2 = 0;
  38. } else {
  39. /* Initial clock starts SCK=0 */
  40. priv->clk1 = 0;
  41. priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
  42. }
  43. /* Enable bitbang, SCK_OE, SDO_OE */
  44. priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
  45. ICPU_SW_MODE_SW_SPI_SCK_OE | /* SCK_OE */
  46. ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
  47. /* Add CS */
  48. if (cs >= 0) {
  49. cs_value =
  50. ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
  51. ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
  52. } else {
  53. cs_value = 0;
  54. }
  55. priv->svalue |= cs_value;
  56. /* Enable the CS in HW, Initial clock value */
  57. writel(priv->svalue | priv->clk2, priv->regs);
  58. priv->cs_active = true;
  59. debug("Activated CS%d\n", priv->cs_num);
  60. }
  61. return 0;
  62. }
  63. static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
  64. {
  65. if (priv->cs_active) {
  66. /* Keep driving the CLK to its current value while
  67. * actively deselecting CS.
  68. */
  69. u32 value = readl(priv->regs);
  70. value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
  71. writel(value, priv->regs);
  72. hold_time_delay();
  73. /* Stop driving the clock, but keep CS with nCS == 1 */
  74. value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
  75. writel(value, priv->regs);
  76. /* Deselect hold time delay */
  77. if (deact_delay)
  78. udelay(deact_delay);
  79. /* Drop everything */
  80. writel(0, priv->regs);
  81. priv->cs_active = false;
  82. debug("Deactivated CS%d\n", priv->cs_num);
  83. }
  84. return 0;
  85. }
  86. int mscc_bb_spi_claim_bus(struct udevice *dev)
  87. {
  88. return 0;
  89. }
  90. int mscc_bb_spi_release_bus(struct udevice *dev)
  91. {
  92. return 0;
  93. }
  94. int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
  95. const void *dout, void *din, unsigned long flags)
  96. {
  97. struct udevice *bus = dev_get_parent(dev);
  98. struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
  99. struct mscc_bb_priv *priv = dev_get_priv(bus);
  100. u32 i, count;
  101. const u8 *txd = dout;
  102. u8 *rxd = din;
  103. debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
  104. dev->parent->name, dev->name, plat->cs, plat->mode, dout,
  105. din, bitlen);
  106. if (flags & SPI_XFER_BEGIN)
  107. mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
  108. count = bitlen / 8;
  109. for (i = 0; i < count; i++) {
  110. u32 rx = 0, mask = 0x80, value;
  111. while (mask) {
  112. /* Initial condition: CLK is low. */
  113. value = priv->svalue;
  114. if (txd && txd[i] & mask)
  115. value |= ICPU_SW_MODE_SW_SPI_SDO;
  116. /* Drive data while taking CLK low. The device
  117. * we're accessing will sample on the
  118. * following rising edge and will output data
  119. * on this edge for us to be sampled at the
  120. * end of this loop.
  121. */
  122. writel(value | priv->clk1, priv->regs);
  123. /* Wait for t_setup. All devices do have a
  124. * setup-time, so we always insert some delay
  125. * here. Some devices have a very long
  126. * setup-time, which can be adjusted by the
  127. * user through vcoreiii_device->delay.
  128. */
  129. hold_time_delay();
  130. /* Drive the clock high. */
  131. writel(value | priv->clk2, priv->regs);
  132. /* Wait for t_hold. See comment about t_setup
  133. * above.
  134. */
  135. hold_time_delay();
  136. /* We sample as close to the next falling edge
  137. * as possible.
  138. */
  139. value = readl(priv->regs);
  140. if (value & ICPU_SW_MODE_SW_SPI_SDI)
  141. rx |= mask;
  142. mask >>= 1;
  143. }
  144. if (rxd) {
  145. debug("Read 0x%02x\n", rx);
  146. rxd[i] = (u8)rx;
  147. }
  148. debug("spi_xfer: byte %d/%d\n", i + 1, count);
  149. }
  150. debug("spi_xfer: done\n");
  151. if (flags & SPI_XFER_END)
  152. mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
  153. return 0;
  154. }
  155. int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
  156. {
  157. /* Accept any speed */
  158. return 0;
  159. }
  160. int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
  161. {
  162. return 0;
  163. }
  164. static const struct dm_spi_ops mscc_bb_ops = {
  165. .claim_bus = mscc_bb_spi_claim_bus,
  166. .release_bus = mscc_bb_spi_release_bus,
  167. .xfer = mscc_bb_spi_xfer,
  168. .set_speed = mscc_bb_spi_set_speed,
  169. .set_mode = mscc_bb_spi_set_mode,
  170. };
  171. static const struct udevice_id mscc_bb_ids[] = {
  172. { .compatible = "mscc,luton-bb-spi" },
  173. { }
  174. };
  175. static int mscc_bb_spi_probe(struct udevice *bus)
  176. {
  177. struct mscc_bb_priv *priv = dev_get_priv(bus);
  178. debug("%s: loaded, priv %p\n", __func__, priv);
  179. priv->regs = (void __iomem *)dev_read_addr(bus);
  180. priv->deactivate_delay_us =
  181. dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  182. priv->cs_active = false;
  183. return 0;
  184. }
  185. U_BOOT_DRIVER(mscc_bb) = {
  186. .name = "mscc_bb",
  187. .id = UCLASS_SPI,
  188. .of_match = mscc_bb_ids,
  189. .ops = &mscc_bb_ops,
  190. .priv_auto = sizeof(struct mscc_bb_priv),
  191. .probe = mscc_bb_spi_probe,
  192. };