fsl_qspi.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale QuadSPI driver.
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2018 Bootlin
  7. * Copyright (C) 2018 exceet electronics GmbH
  8. * Copyright (C) 2018 Kontron Electronics GmbH
  9. * Copyright 2019-2020 NXP
  10. *
  11. * This driver is a ported version of Linux Freescale QSPI driver taken from
  12. * v5.5-rc1 tag having following information.
  13. *
  14. * Transition to SPI MEM interface:
  15. * Authors:
  16. * Boris Brezillon <bbrezillon@kernel.org>
  17. * Frieder Schrempf <frieder.schrempf@kontron.de>
  18. * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  19. * Suresh Gupta <suresh.gupta@nxp.com>
  20. *
  21. * Based on the original fsl-quadspi.c spi-nor driver.
  22. * Transition to spi-mem in spi-fsl-qspi.c
  23. */
  24. #include <common.h>
  25. #include <dm.h>
  26. #include <dm/device_compat.h>
  27. #include <log.h>
  28. #include <spi.h>
  29. #include <spi-mem.h>
  30. #include <asm/global_data.h>
  31. #include <linux/bitops.h>
  32. #include <linux/delay.h>
  33. #include <linux/libfdt.h>
  34. #include <linux/sizes.h>
  35. #include <linux/iopoll.h>
  36. #include <linux/iopoll.h>
  37. #include <linux/sizes.h>
  38. #include <linux/err.h>
  39. #include <asm/io.h>
  40. DECLARE_GLOBAL_DATA_PTR;
  41. /*
  42. * The driver only uses one single LUT entry, that is updated on
  43. * each call of exec_op(). Index 0 is preset at boot with a basic
  44. * read operation, so let's use the last entry (15).
  45. */
  46. #define SEQID_LUT 15
  47. #define SEQID_LUT_AHB 14
  48. /* Registers used by the driver */
  49. #define QUADSPI_MCR 0x00
  50. #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
  51. #define QUADSPI_MCR_MDIS_MASK BIT(14)
  52. #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
  53. #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
  54. #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
  55. #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
  56. #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
  57. #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
  58. #define QUADSPI_IPCR 0x08
  59. #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
  60. #define QUADSPI_FLSHCR 0x0c
  61. #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
  62. #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
  63. #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
  64. #define QUADSPI_BUF3CR 0x1c
  65. #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
  66. #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
  67. #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
  68. #define QUADSPI_BFGENCR 0x20
  69. #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
  70. #define QUADSPI_BUF0IND 0x30
  71. #define QUADSPI_BUF1IND 0x34
  72. #define QUADSPI_BUF2IND 0x38
  73. #define QUADSPI_SFAR 0x100
  74. #define QUADSPI_SMPR 0x108
  75. #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
  76. #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
  77. #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
  78. #define QUADSPI_SMPR_HSENA_MASK BIT(0)
  79. #define QUADSPI_RBCT 0x110
  80. #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
  81. #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
  82. #define QUADSPI_TBDR 0x154
  83. #define QUADSPI_SR 0x15c
  84. #define QUADSPI_SR_IP_ACC_MASK BIT(1)
  85. #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
  86. #define QUADSPI_FR 0x160
  87. #define QUADSPI_FR_TFF_MASK BIT(0)
  88. #define QUADSPI_RSER 0x164
  89. #define QUADSPI_RSER_TFIE BIT(0)
  90. #define QUADSPI_SPTRCLR 0x16c
  91. #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
  92. #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
  93. #define QUADSPI_SFA1AD 0x180
  94. #define QUADSPI_SFA2AD 0x184
  95. #define QUADSPI_SFB1AD 0x188
  96. #define QUADSPI_SFB2AD 0x18c
  97. #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
  98. #define QUADSPI_LUTKEY 0x300
  99. #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
  100. #define QUADSPI_LCKCR 0x304
  101. #define QUADSPI_LCKER_LOCK BIT(0)
  102. #define QUADSPI_LCKER_UNLOCK BIT(1)
  103. #define QUADSPI_LUT_BASE 0x310
  104. #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  105. #define QUADSPI_LUT_REG(idx) \
  106. (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
  107. #define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4)
  108. #define QUADSPI_AHB_LUT_REG(idx) \
  109. (QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4)
  110. /* Instruction set for the LUT register */
  111. #define LUT_STOP 0
  112. #define LUT_CMD 1
  113. #define LUT_ADDR 2
  114. #define LUT_DUMMY 3
  115. #define LUT_MODE 4
  116. #define LUT_MODE2 5
  117. #define LUT_MODE4 6
  118. #define LUT_FSL_READ 7
  119. #define LUT_FSL_WRITE 8
  120. #define LUT_JMP_ON_CS 9
  121. #define LUT_ADDR_DDR 10
  122. #define LUT_MODE_DDR 11
  123. #define LUT_MODE2_DDR 12
  124. #define LUT_MODE4_DDR 13
  125. #define LUT_FSL_READ_DDR 14
  126. #define LUT_FSL_WRITE_DDR 15
  127. #define LUT_DATA_LEARN 16
  128. /*
  129. * The PAD definitions for LUT register.
  130. *
  131. * The pad stands for the number of IO lines [0:3].
  132. * For example, the quad read needs four IO lines,
  133. * so you should use LUT_PAD(4).
  134. */
  135. #define LUT_PAD(x) (fls(x) - 1)
  136. /*
  137. * Macro for constructing the LUT entries with the following
  138. * register layout:
  139. *
  140. * ---------------------------------------------------
  141. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  142. * ---------------------------------------------------
  143. */
  144. #define LUT_DEF(idx, ins, pad, opr) \
  145. ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
  146. /* Controller needs driver to swap endianness */
  147. #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
  148. /* Controller needs 4x internal clock */
  149. #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
  150. /*
  151. * TKT253890, the controller needs the driver to fill the txfifo with
  152. * 16 bytes at least to trigger a data transfer, even though the extra
  153. * data won't be transferred.
  154. */
  155. #define QUADSPI_QUIRK_TKT253890 BIT(2)
  156. /* TKT245618, the controller cannot wake up from wait mode */
  157. #define QUADSPI_QUIRK_TKT245618 BIT(3)
  158. /*
  159. * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
  160. * internally. No need to add it when setting SFXXAD and SFAR registers
  161. */
  162. #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
  163. /*
  164. * Controller uses TDH bits in register QUADSPI_FLSHCR.
  165. * They need to be set in accordance with the DDR/SDR mode.
  166. */
  167. #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
  168. /*
  169. * Controller only has Two CS on flash A, no flash B port
  170. */
  171. #define QUADSPI_QUIRK_SINGLE_BUS BIT(6)
  172. struct fsl_qspi_devtype_data {
  173. unsigned int rxfifo;
  174. unsigned int txfifo;
  175. unsigned int ahb_buf_size;
  176. unsigned int quirks;
  177. bool little_endian;
  178. };
  179. static const struct fsl_qspi_devtype_data vybrid_data = {
  180. .rxfifo = SZ_128,
  181. .txfifo = SZ_64,
  182. .ahb_buf_size = SZ_1K,
  183. .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  184. .little_endian = true,
  185. };
  186. static const struct fsl_qspi_devtype_data imx6sx_data = {
  187. .rxfifo = SZ_128,
  188. .txfifo = SZ_512,
  189. .ahb_buf_size = SZ_1K,
  190. .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  191. .little_endian = true,
  192. };
  193. static const struct fsl_qspi_devtype_data imx7d_data = {
  194. .rxfifo = SZ_128,
  195. .txfifo = SZ_512,
  196. .ahb_buf_size = SZ_1K,
  197. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  198. QUADSPI_QUIRK_USE_TDH_SETTING,
  199. .little_endian = true,
  200. };
  201. static const struct fsl_qspi_devtype_data imx6ul_data = {
  202. .rxfifo = SZ_128,
  203. .txfifo = SZ_512,
  204. .ahb_buf_size = SZ_1K,
  205. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  206. QUADSPI_QUIRK_USE_TDH_SETTING,
  207. .little_endian = true,
  208. };
  209. static const struct fsl_qspi_devtype_data imx7ulp_data = {
  210. .rxfifo = SZ_64,
  211. .txfifo = SZ_64,
  212. .ahb_buf_size = SZ_128,
  213. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  214. QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS,
  215. .little_endian = true,
  216. };
  217. static const struct fsl_qspi_devtype_data ls1021a_data = {
  218. .rxfifo = SZ_128,
  219. .txfifo = SZ_64,
  220. .ahb_buf_size = SZ_1K,
  221. .quirks = 0,
  222. .little_endian = false,
  223. };
  224. static const struct fsl_qspi_devtype_data ls2080a_data = {
  225. .rxfifo = SZ_128,
  226. .txfifo = SZ_64,
  227. .ahb_buf_size = SZ_1K,
  228. .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  229. .little_endian = true,
  230. };
  231. struct fsl_qspi {
  232. struct udevice *dev;
  233. void __iomem *iobase;
  234. void __iomem *ahb_addr;
  235. u32 memmap_phy;
  236. u32 memmap_size;
  237. const struct fsl_qspi_devtype_data *devtype_data;
  238. int selected;
  239. };
  240. static inline int needs_swap_endian(struct fsl_qspi *q)
  241. {
  242. return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
  243. }
  244. static inline int needs_4x_clock(struct fsl_qspi *q)
  245. {
  246. return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
  247. }
  248. static inline int needs_fill_txfifo(struct fsl_qspi *q)
  249. {
  250. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
  251. }
  252. static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
  253. {
  254. return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
  255. }
  256. static inline int needs_amba_base_offset(struct fsl_qspi *q)
  257. {
  258. return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  259. }
  260. static inline int needs_tdh_setting(struct fsl_qspi *q)
  261. {
  262. return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
  263. }
  264. static inline int needs_single_bus(struct fsl_qspi *q)
  265. {
  266. return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS;
  267. }
  268. /*
  269. * An IC bug makes it necessary to rearrange the 32-bit data.
  270. * Later chips, such as IMX6SLX, have fixed this bug.
  271. */
  272. static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
  273. {
  274. return needs_swap_endian(q) ? __swab32(a) : a;
  275. }
  276. /*
  277. * R/W functions for big- or little-endian registers:
  278. * The QSPI controller's endianness is independent of
  279. * the CPU core's endianness. So far, although the CPU
  280. * core is little-endian the QSPI controller can use
  281. * big-endian or little-endian.
  282. */
  283. static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
  284. {
  285. if (q->devtype_data->little_endian)
  286. out_le32(addr, val);
  287. else
  288. out_be32(addr, val);
  289. }
  290. static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
  291. {
  292. if (q->devtype_data->little_endian)
  293. return in_le32(addr);
  294. return in_be32(addr);
  295. }
  296. static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
  297. {
  298. switch (width) {
  299. case 1:
  300. case 2:
  301. case 4:
  302. return 0;
  303. }
  304. return -ENOTSUPP;
  305. }
  306. static bool fsl_qspi_supports_op(struct spi_slave *slave,
  307. const struct spi_mem_op *op)
  308. {
  309. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  310. int ret;
  311. ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
  312. if (op->addr.nbytes)
  313. ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
  314. if (op->dummy.nbytes)
  315. ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
  316. if (op->data.nbytes)
  317. ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
  318. if (ret)
  319. return false;
  320. /*
  321. * The number of instructions needed for the op, needs
  322. * to fit into a single LUT entry.
  323. */
  324. if (op->addr.nbytes +
  325. (op->dummy.nbytes ? 1 : 0) +
  326. (op->data.nbytes ? 1 : 0) > 6)
  327. return false;
  328. /* Max 64 dummy clock cycles supported */
  329. if (op->dummy.nbytes &&
  330. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  331. return false;
  332. /* Max data length, check controller limits and alignment */
  333. if (op->data.dir == SPI_MEM_DATA_IN &&
  334. (op->data.nbytes > q->devtype_data->ahb_buf_size ||
  335. (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
  336. !IS_ALIGNED(op->data.nbytes, 8))))
  337. return false;
  338. if (op->data.dir == SPI_MEM_DATA_OUT &&
  339. op->data.nbytes > q->devtype_data->txfifo)
  340. return false;
  341. return spi_mem_default_supports_op(slave, op);
  342. }
  343. static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
  344. const struct spi_mem_op *op)
  345. {
  346. void __iomem *base = q->iobase;
  347. u32 lutval[4] = {};
  348. int lutidx = 1, i;
  349. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  350. op->cmd.opcode);
  351. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  352. if (op->addr.nbytes) {
  353. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  354. LUT_PAD(op->addr.buswidth),
  355. (op->addr.nbytes == 4) ? 0x20 : 0x18);
  356. lutidx++;
  357. }
  358. } else {
  359. /*
  360. * For some unknown reason, using LUT_ADDR doesn't work in some
  361. * cases (at least with only one byte long addresses), so
  362. * let's use LUT_MODE to write the address bytes one by one
  363. */
  364. for (i = 0; i < op->addr.nbytes; i++) {
  365. u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  366. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
  367. LUT_PAD(op->addr.buswidth),
  368. addrbyte);
  369. lutidx++;
  370. }
  371. }
  372. if (op->dummy.nbytes) {
  373. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  374. LUT_PAD(op->dummy.buswidth),
  375. op->dummy.nbytes * 8 /
  376. op->dummy.buswidth);
  377. lutidx++;
  378. }
  379. if (op->data.nbytes) {
  380. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  381. op->data.dir == SPI_MEM_DATA_IN ?
  382. LUT_FSL_READ : LUT_FSL_WRITE,
  383. LUT_PAD(op->data.buswidth),
  384. 0);
  385. lutidx++;
  386. }
  387. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  388. /* unlock LUT */
  389. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  390. qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
  391. dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  392. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  393. /* fill LUT */
  394. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  395. qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
  396. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  397. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
  398. op->addr.nbytes) {
  399. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  400. qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
  401. }
  402. }
  403. /* lock LUT */
  404. qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
  405. qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
  406. }
  407. /*
  408. * If we have changed the content of the flash by writing or erasing, or if we
  409. * read from flash with a different offset into the page buffer, we need to
  410. * invalidate the AHB buffer. If we do not do so, we may read out the wrong
  411. * data. The spec tells us reset the AHB domain and Serial Flash domain at
  412. * the same time.
  413. */
  414. static void fsl_qspi_invalidate(struct fsl_qspi *q)
  415. {
  416. u32 reg;
  417. reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  418. reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
  419. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  420. /*
  421. * The minimum delay : 1 AHB + 2 SFCK clocks.
  422. * Delay 1 us is enough.
  423. */
  424. udelay(1);
  425. reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
  426. qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  427. }
  428. static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
  429. {
  430. struct dm_spi_slave_plat *plat =
  431. dev_get_parent_plat(slave->dev);
  432. if (q->selected == plat->cs)
  433. return;
  434. q->selected = plat->cs;
  435. fsl_qspi_invalidate(q);
  436. }
  437. static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q)
  438. {
  439. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  440. if (needs_single_bus(q))
  441. return q->memmap_size / 2;
  442. else
  443. return q->memmap_size / 4;
  444. } else {
  445. return ALIGN(q->devtype_data->ahb_buf_size, 0x400);
  446. }
  447. }
  448. static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
  449. {
  450. void __iomem *ahb_read_addr = q->ahb_addr;
  451. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  452. if (op->addr.nbytes)
  453. ahb_read_addr += op->addr.val;
  454. }
  455. memcpy_fromio(op->data.buf.in,
  456. ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q),
  457. op->data.nbytes);
  458. }
  459. static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
  460. const struct spi_mem_op *op)
  461. {
  462. void __iomem *base = q->iobase;
  463. int i;
  464. u32 val;
  465. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  466. memcpy(&val, op->data.buf.out + i, 4);
  467. val = fsl_qspi_endian_xchg(q, val);
  468. qspi_writel(q, val, base + QUADSPI_TBDR);
  469. }
  470. if (i < op->data.nbytes) {
  471. memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
  472. val = fsl_qspi_endian_xchg(q, val);
  473. qspi_writel(q, val, base + QUADSPI_TBDR);
  474. }
  475. if (needs_fill_txfifo(q)) {
  476. for (i = op->data.nbytes; i < 16; i += 4)
  477. qspi_writel(q, 0, base + QUADSPI_TBDR);
  478. }
  479. }
  480. static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
  481. const struct spi_mem_op *op)
  482. {
  483. void __iomem *base = q->iobase;
  484. int i;
  485. u8 *buf = op->data.buf.in;
  486. u32 val;
  487. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
  488. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  489. val = fsl_qspi_endian_xchg(q, val);
  490. memcpy(buf + i, &val, 4);
  491. }
  492. if (i < op->data.nbytes) {
  493. val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
  494. val = fsl_qspi_endian_xchg(q, val);
  495. memcpy(buf + i, &val, op->data.nbytes - i);
  496. }
  497. }
  498. static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
  499. u32 mask, u32 delay_us, u32 timeout_us)
  500. {
  501. u32 reg;
  502. if (!q->devtype_data->little_endian)
  503. mask = (u32)cpu_to_be32(mask);
  504. return readl_poll_timeout(base, reg, !(reg & mask), timeout_us);
  505. }
  506. static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
  507. {
  508. void __iomem *base = q->iobase;
  509. int err = 0;
  510. /*
  511. * Always start the sequence at the same index since we update
  512. * the LUT at each exec_op() call. And also specify the DATA
  513. * length, since it's has not been specified in the LUT.
  514. */
  515. qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
  516. base + QUADSPI_IPCR);
  517. /* wait for the controller being ready */
  518. err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
  519. (QUADSPI_SR_IP_ACC_MASK |
  520. QUADSPI_SR_AHB_ACC_MASK),
  521. 10, 1000);
  522. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  523. fsl_qspi_read_rxfifo(q, op);
  524. return err;
  525. }
  526. static int fsl_qspi_exec_op(struct spi_slave *slave,
  527. const struct spi_mem_op *op)
  528. {
  529. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  530. void __iomem *base = q->iobase;
  531. u32 addr_offset = 0;
  532. int err = 0;
  533. /* wait for the controller being ready */
  534. fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
  535. QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
  536. fsl_qspi_select_mem(q, slave);
  537. if (needs_amba_base_offset(q))
  538. addr_offset = q->memmap_phy;
  539. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
  540. if (op->addr.nbytes)
  541. addr_offset += op->addr.val;
  542. }
  543. qspi_writel(q,
  544. q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset,
  545. base + QUADSPI_SFAR);
  546. qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
  547. QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
  548. base + QUADSPI_MCR);
  549. qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
  550. base + QUADSPI_SPTRCLR);
  551. fsl_qspi_prepare_lut(q, op);
  552. /*
  553. * If we have large chunks of data, we read them through the AHB bus
  554. * by accessing the mapped memory. In all other cases we use
  555. * IP commands to access the flash.
  556. */
  557. if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
  558. op->data.dir == SPI_MEM_DATA_IN) {
  559. fsl_qspi_read_ahb(q, op);
  560. } else {
  561. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
  562. QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
  563. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  564. fsl_qspi_fill_txfifo(q, op);
  565. err = fsl_qspi_do_op(q, op);
  566. }
  567. /* Invalidate the data in the AHB buffer. */
  568. fsl_qspi_invalidate(q);
  569. return err;
  570. }
  571. static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
  572. struct spi_mem_op *op)
  573. {
  574. struct fsl_qspi *q = dev_get_priv(slave->dev->parent);
  575. if (op->data.dir == SPI_MEM_DATA_OUT) {
  576. if (op->data.nbytes > q->devtype_data->txfifo)
  577. op->data.nbytes = q->devtype_data->txfifo;
  578. } else {
  579. if (op->data.nbytes > q->devtype_data->ahb_buf_size)
  580. op->data.nbytes = q->devtype_data->ahb_buf_size;
  581. else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
  582. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  583. }
  584. return 0;
  585. }
  586. static int fsl_qspi_default_setup(struct fsl_qspi *q)
  587. {
  588. void __iomem *base = q->iobase;
  589. u32 reg, addr_offset = 0, memsize_cs;
  590. /* Reset the module */
  591. qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
  592. base + QUADSPI_MCR);
  593. udelay(1);
  594. /* Disable the module */
  595. qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
  596. base + QUADSPI_MCR);
  597. /*
  598. * Previous boot stages (BootROM, bootloader) might have used DDR
  599. * mode and did not clear the TDH bits. As we currently use SDR mode
  600. * only, clear the TDH bits if necessary.
  601. */
  602. if (needs_tdh_setting(q))
  603. qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
  604. ~QUADSPI_FLSHCR_TDH_MASK,
  605. base + QUADSPI_FLSHCR);
  606. reg = qspi_readl(q, base + QUADSPI_SMPR);
  607. qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
  608. | QUADSPI_SMPR_FSPHS_MASK
  609. | QUADSPI_SMPR_HSENA_MASK
  610. | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
  611. /* We only use the buffer3 for AHB read */
  612. qspi_writel(q, 0, base + QUADSPI_BUF0IND);
  613. qspi_writel(q, 0, base + QUADSPI_BUF1IND);
  614. qspi_writel(q, 0, base + QUADSPI_BUF2IND);
  615. if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
  616. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
  617. q->iobase + QUADSPI_BFGENCR);
  618. else
  619. qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
  620. q->iobase + QUADSPI_BFGENCR);
  621. qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
  622. qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
  623. QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
  624. base + QUADSPI_BUF3CR);
  625. if (needs_amba_base_offset(q))
  626. addr_offset = q->memmap_phy;
  627. /*
  628. * In HW there can be a maximum of four chips on two buses with
  629. * two chip selects on each bus. We use four chip selects in SW
  630. * to differentiate between the four chips.
  631. * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
  632. * SFB2AD accordingly.
  633. */
  634. memsize_cs = fsl_qspi_memsize_per_cs(q);
  635. qspi_writel(q, memsize_cs + addr_offset,
  636. base + QUADSPI_SFA1AD);
  637. qspi_writel(q, memsize_cs * 2 + addr_offset,
  638. base + QUADSPI_SFA2AD);
  639. if (!needs_single_bus(q)) {
  640. qspi_writel(q, memsize_cs * 3 + addr_offset,
  641. base + QUADSPI_SFB1AD);
  642. qspi_writel(q, memsize_cs * 4 + addr_offset,
  643. base + QUADSPI_SFB2AD);
  644. }
  645. q->selected = -1;
  646. /* Enable the module */
  647. qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
  648. base + QUADSPI_MCR);
  649. return 0;
  650. }
  651. static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
  652. .adjust_op_size = fsl_qspi_adjust_op_size,
  653. .supports_op = fsl_qspi_supports_op,
  654. .exec_op = fsl_qspi_exec_op,
  655. };
  656. static int fsl_qspi_probe(struct udevice *bus)
  657. {
  658. struct dm_spi_bus *dm_bus = dev_get_uclass_priv(bus);
  659. struct fsl_qspi *q = dev_get_priv(bus);
  660. const void *blob = gd->fdt_blob;
  661. int node = dev_of_offset(bus);
  662. struct fdt_resource res;
  663. int ret;
  664. q->dev = bus;
  665. q->devtype_data = (struct fsl_qspi_devtype_data *)
  666. dev_get_driver_data(bus);
  667. /* find the resources */
  668. ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI",
  669. &res);
  670. if (ret) {
  671. dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret);
  672. return -ENOMEM;
  673. }
  674. q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  675. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  676. "QuadSPI-memory", &res);
  677. if (ret) {
  678. dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret);
  679. return -ENOMEM;
  680. }
  681. q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
  682. q->memmap_phy = res.start;
  683. q->memmap_size = res.end - res.start;
  684. dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  685. 66000000);
  686. fsl_qspi_default_setup(q);
  687. return 0;
  688. }
  689. static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  690. const void *dout, void *din, unsigned long flags)
  691. {
  692. return 0;
  693. }
  694. static int fsl_qspi_claim_bus(struct udevice *dev)
  695. {
  696. return 0;
  697. }
  698. static int fsl_qspi_release_bus(struct udevice *dev)
  699. {
  700. return 0;
  701. }
  702. static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
  703. {
  704. return 0;
  705. }
  706. static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
  707. {
  708. return 0;
  709. }
  710. static const struct dm_spi_ops fsl_qspi_ops = {
  711. .claim_bus = fsl_qspi_claim_bus,
  712. .release_bus = fsl_qspi_release_bus,
  713. .xfer = fsl_qspi_xfer,
  714. .set_speed = fsl_qspi_set_speed,
  715. .set_mode = fsl_qspi_set_mode,
  716. .mem_ops = &fsl_qspi_mem_ops,
  717. };
  718. static const struct udevice_id fsl_qspi_ids[] = {
  719. { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, },
  720. { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
  721. { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
  722. { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
  723. { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
  724. { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
  725. { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, },
  726. { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
  727. { }
  728. };
  729. U_BOOT_DRIVER(fsl_qspi) = {
  730. .name = "fsl_qspi",
  731. .id = UCLASS_SPI,
  732. .of_match = fsl_qspi_ids,
  733. .ops = &fsl_qspi_ops,
  734. .priv_auto = sizeof(struct fsl_qspi),
  735. .probe = fsl_qspi_probe,
  736. };