fsl_dspi.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. * Chao Fu (B44548@freescale.com)
  9. * Haikun Wang (B53464@freescale.com)
  10. */
  11. #include <asm/global_data.h>
  12. #include <linux/math64.h>
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <common.h>
  17. #include <log.h>
  18. #include <spi.h>
  19. #include <malloc.h>
  20. #include <asm/io.h>
  21. #include <fdtdec.h>
  22. #ifndef CONFIG_M68K
  23. #include <asm/arch/clock.h>
  24. #endif
  25. #include <fsl_dspi.h>
  26. #include <linux/bitops.h>
  27. #include <linux/delay.h>
  28. /* linux/include/time.h */
  29. #define NSEC_PER_SEC 1000000000L
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /* fsl_dspi_plat flags */
  32. #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
  33. /* idle data value */
  34. #define DSPI_IDLE_VAL 0x0
  35. /* max chipselect signals number */
  36. #define FSL_DSPI_MAX_CHIPSELECT 6
  37. /* default SCK frequency, unit: HZ */
  38. #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
  39. /* tx/rx data wait timeout value, unit: us */
  40. #define DSPI_TXRX_WAIT_TIMEOUT 1000000
  41. /* CTAR register pre-configure value */
  42. #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
  43. DSPI_CTAR_PCSSCK_1CLK | \
  44. DSPI_CTAR_PASC(0) | \
  45. DSPI_CTAR_PDT(0) | \
  46. DSPI_CTAR_CSSCK(0) | \
  47. DSPI_CTAR_ASC(0) | \
  48. DSPI_CTAR_DT(0))
  49. /* CTAR register pre-configure mask */
  50. #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
  51. DSPI_CTAR_PCSSCK(3) | \
  52. DSPI_CTAR_PASC(3) | \
  53. DSPI_CTAR_PDT(3) | \
  54. DSPI_CTAR_CSSCK(15) | \
  55. DSPI_CTAR_ASC(15) | \
  56. DSPI_CTAR_DT(15))
  57. /**
  58. * struct fsl_dspi_plat - platform data for Freescale DSPI
  59. *
  60. * @flags: Flags for DSPI DSPI_FLAG_...
  61. * @speed_hz: Default SCK frequency
  62. * @num_chipselect: Number of DSPI chipselect signals
  63. * @regs_addr: Base address of DSPI registers
  64. */
  65. struct fsl_dspi_plat {
  66. uint flags;
  67. uint speed_hz;
  68. uint num_chipselect;
  69. fdt_addr_t regs_addr;
  70. };
  71. /**
  72. * struct fsl_dspi_priv - private data for Freescale DSPI
  73. *
  74. * @flags: Flags for DSPI DSPI_FLAG_...
  75. * @mode: SPI mode to use for slave device (see SPI mode flags)
  76. * @mcr_val: MCR register configure value
  77. * @bus_clk: DSPI input clk frequency
  78. * @speed_hz: Default SCK frequency
  79. * @charbit: How many bits in every transfer
  80. * @num_chipselect: Number of DSPI chipselect signals
  81. * @ctar_val: CTAR register configure value of per chipselect slave device
  82. * @regs: Point to DSPI register structure for I/O access
  83. */
  84. struct fsl_dspi_priv {
  85. uint flags;
  86. uint mode;
  87. uint mcr_val;
  88. uint bus_clk;
  89. uint speed_hz;
  90. uint charbit;
  91. uint num_chipselect;
  92. uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
  93. struct dspi *regs;
  94. };
  95. __weak void cpu_dspi_port_conf(void)
  96. {
  97. }
  98. __weak int cpu_dspi_claim_bus(uint bus, uint cs)
  99. {
  100. return 0;
  101. }
  102. __weak void cpu_dspi_release_bus(uint bus, uint cs)
  103. {
  104. }
  105. static uint dspi_read32(uint flags, uint *addr)
  106. {
  107. return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  108. in_be32(addr) : in_le32(addr);
  109. }
  110. static void dspi_write32(uint flags, uint *addr, uint val)
  111. {
  112. flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  113. out_be32(addr, val) : out_le32(addr, val);
  114. }
  115. static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
  116. {
  117. uint mcr_val;
  118. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  119. if (halt)
  120. mcr_val |= DSPI_MCR_HALT;
  121. else
  122. mcr_val &= ~DSPI_MCR_HALT;
  123. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  124. }
  125. static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
  126. {
  127. /* halt DSPI module */
  128. dspi_halt(priv, 1);
  129. dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
  130. /* resume module */
  131. dspi_halt(priv, 0);
  132. priv->mcr_val = cfg_val;
  133. }
  134. static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
  135. uint cs, uint state)
  136. {
  137. uint mcr_val;
  138. dspi_halt(priv, 1);
  139. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  140. if (state & SPI_CS_HIGH)
  141. /* CSx inactive state is low */
  142. mcr_val &= ~DSPI_MCR_PCSIS(cs);
  143. else
  144. /* CSx inactive state is high */
  145. mcr_val |= DSPI_MCR_PCSIS(cs);
  146. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  147. dspi_halt(priv, 0);
  148. }
  149. static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
  150. uint cs, uint mode)
  151. {
  152. uint bus_setup;
  153. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  154. bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
  155. bus_setup |= priv->ctar_val[cs];
  156. bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
  157. if (mode & SPI_CPOL)
  158. bus_setup |= DSPI_CTAR_CPOL;
  159. if (mode & SPI_CPHA)
  160. bus_setup |= DSPI_CTAR_CPHA;
  161. if (mode & SPI_LSB_FIRST)
  162. bus_setup |= DSPI_CTAR_LSBFE;
  163. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  164. priv->charbit =
  165. ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
  166. DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
  167. return 0;
  168. }
  169. static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
  170. {
  171. uint mcr_val;
  172. dspi_halt(priv, 1);
  173. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  174. /* flush RX and TX FIFO */
  175. mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  176. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  177. dspi_halt(priv, 0);
  178. }
  179. static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
  180. {
  181. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  182. /* wait for empty entries in TXFIFO or timeout */
  183. while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
  184. timeout--)
  185. udelay(1);
  186. if (timeout >= 0)
  187. dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
  188. else
  189. debug("dspi_tx: waiting timeout!\n");
  190. }
  191. static u16 dspi_rx(struct fsl_dspi_priv *priv)
  192. {
  193. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  194. /* wait for valid entries in RXFIFO or timeout */
  195. while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
  196. timeout--)
  197. udelay(1);
  198. if (timeout >= 0)
  199. return (u16)DSPI_RFR_RXDATA(
  200. dspi_read32(priv->flags, &priv->regs->rfr));
  201. else {
  202. debug("dspi_rx: waiting timeout!\n");
  203. return (u16)(~0);
  204. }
  205. }
  206. static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
  207. const void *dout, void *din, unsigned long flags)
  208. {
  209. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  210. u8 *spi_rd = NULL, *spi_wr = NULL;
  211. static u32 ctrl;
  212. uint len = bitlen >> 3;
  213. if (priv->charbit == 16) {
  214. bitlen >>= 1;
  215. spi_wr16 = (u16 *)dout;
  216. spi_rd16 = (u16 *)din;
  217. } else {
  218. spi_wr = (u8 *)dout;
  219. spi_rd = (u8 *)din;
  220. }
  221. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  222. ctrl |= DSPI_TFR_CONT;
  223. ctrl = ctrl & DSPI_TFR_CONT;
  224. ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
  225. if (len > 1) {
  226. int tmp_len = len - 1;
  227. while (tmp_len--) {
  228. if ((dout != NULL) && (din != NULL)) {
  229. if (priv->charbit == 16) {
  230. dspi_tx(priv, ctrl, *spi_wr16++);
  231. *spi_rd16++ = dspi_rx(priv);
  232. }
  233. else {
  234. dspi_tx(priv, ctrl, *spi_wr++);
  235. *spi_rd++ = dspi_rx(priv);
  236. }
  237. }
  238. else if (dout != NULL) {
  239. if (priv->charbit == 16)
  240. dspi_tx(priv, ctrl, *spi_wr16++);
  241. else
  242. dspi_tx(priv, ctrl, *spi_wr++);
  243. dspi_rx(priv);
  244. }
  245. else if (din != NULL) {
  246. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  247. if (priv->charbit == 16)
  248. *spi_rd16++ = dspi_rx(priv);
  249. else
  250. *spi_rd++ = dspi_rx(priv);
  251. }
  252. }
  253. len = 1; /* remaining byte */
  254. }
  255. if ((flags & SPI_XFER_END) == SPI_XFER_END)
  256. ctrl &= ~DSPI_TFR_CONT;
  257. if (len) {
  258. if ((dout != NULL) && (din != NULL)) {
  259. if (priv->charbit == 16) {
  260. dspi_tx(priv, ctrl, *spi_wr16++);
  261. *spi_rd16++ = dspi_rx(priv);
  262. }
  263. else {
  264. dspi_tx(priv, ctrl, *spi_wr++);
  265. *spi_rd++ = dspi_rx(priv);
  266. }
  267. }
  268. else if (dout != NULL) {
  269. if (priv->charbit == 16)
  270. dspi_tx(priv, ctrl, *spi_wr16);
  271. else
  272. dspi_tx(priv, ctrl, *spi_wr);
  273. dspi_rx(priv);
  274. }
  275. else if (din != NULL) {
  276. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  277. if (priv->charbit == 16)
  278. *spi_rd16 = dspi_rx(priv);
  279. else
  280. *spi_rd = dspi_rx(priv);
  281. }
  282. } else {
  283. /* dummy read */
  284. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  285. dspi_rx(priv);
  286. }
  287. return 0;
  288. }
  289. /**
  290. * Calculate the divide value between input clk frequency and expected SCK frequency
  291. * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
  292. * Dbr: use default value 0
  293. *
  294. * @pbr: return Baud Rate Prescaler value
  295. * @br: return Baud Rate Scaler value
  296. * @speed_hz: expected SCK frequency
  297. * @clkrate: input clk frequency
  298. */
  299. static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
  300. int speed_hz, uint clkrate)
  301. {
  302. /* Valid baud rate pre-scaler values */
  303. int pbr_tbl[4] = {2, 3, 5, 7};
  304. int brs[16] = {2, 4, 6, 8,
  305. 16, 32, 64, 128,
  306. 256, 512, 1024, 2048,
  307. 4096, 8192, 16384, 32768};
  308. int temp, i = 0, j = 0;
  309. temp = clkrate / speed_hz;
  310. for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
  311. for (j = 0; j < ARRAY_SIZE(brs); j++) {
  312. if (pbr_tbl[i] * brs[j] >= temp) {
  313. *pbr = i;
  314. *br = j;
  315. return 0;
  316. }
  317. }
  318. debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
  319. debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
  320. *pbr = ARRAY_SIZE(pbr_tbl) - 1;
  321. *br = ARRAY_SIZE(brs) - 1;
  322. return -EINVAL;
  323. }
  324. static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
  325. unsigned long clkrate)
  326. {
  327. int scale_needed, scale, minscale = INT_MAX;
  328. int pscale_tbl[4] = {1, 3, 5, 7};
  329. u32 remainder;
  330. int i, j;
  331. scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
  332. &remainder);
  333. if (remainder)
  334. scale_needed++;
  335. for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
  336. for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
  337. scale = pscale_tbl[i] * (2 << j);
  338. if (scale >= scale_needed) {
  339. if (scale < minscale) {
  340. minscale = scale;
  341. *psc = i;
  342. *sc = j;
  343. }
  344. break;
  345. }
  346. }
  347. if (minscale == INT_MAX) {
  348. pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
  349. delay_ns, clkrate);
  350. *psc = ARRAY_SIZE(pscale_tbl) - 1;
  351. *sc = DSPI_CTAR_SCALE_BITS;
  352. }
  353. }
  354. static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
  355. {
  356. int ret;
  357. uint bus_setup;
  358. int best_i, best_j, bus_clk;
  359. bus_clk = priv->bus_clk;
  360. debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
  361. speed, bus_clk);
  362. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  363. bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
  364. ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  365. if (ret) {
  366. speed = priv->speed_hz;
  367. debug("DSPI set_speed use default SCK rate %u.\n", speed);
  368. fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  369. }
  370. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  371. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  372. priv->speed_hz = speed;
  373. return 0;
  374. }
  375. static int fsl_dspi_child_pre_probe(struct udevice *dev)
  376. {
  377. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  378. struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
  379. u32 cs_sck_delay = 0, sck_cs_delay = 0;
  380. unsigned char pcssck = 0, cssck = 0;
  381. unsigned char pasc = 0, asc = 0;
  382. if (slave_plat->cs >= priv->num_chipselect) {
  383. debug("DSPI invalid chipselect number %d(max %d)!\n",
  384. slave_plat->cs, priv->num_chipselect - 1);
  385. return -EINVAL;
  386. }
  387. ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
  388. &cs_sck_delay);
  389. ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
  390. &sck_cs_delay);
  391. /* Set PCS to SCK delay scale values */
  392. ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
  393. /* Set After SCK delay scale values */
  394. ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
  395. priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
  396. DSPI_CTAR_PCSSCK(pcssck) |
  397. DSPI_CTAR_PASC(pasc);
  398. debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
  399. slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
  400. return 0;
  401. }
  402. static int fsl_dspi_probe(struct udevice *bus)
  403. {
  404. struct fsl_dspi_plat *plat = dev_get_plat(bus);
  405. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  406. struct dm_spi_bus *dm_spi_bus;
  407. uint mcr_cfg_val;
  408. dm_spi_bus = dev_get_uclass_priv(bus);
  409. /* cpu speical pin muxing configure */
  410. cpu_dspi_port_conf();
  411. /* get input clk frequency */
  412. priv->regs = (struct dspi *)plat->regs_addr;
  413. priv->flags = plat->flags;
  414. #ifdef CONFIG_M68K
  415. priv->bus_clk = gd->bus_clk;
  416. #else
  417. priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
  418. #endif
  419. priv->num_chipselect = plat->num_chipselect;
  420. priv->speed_hz = plat->speed_hz;
  421. /* frame data length in bits, default 8bits */
  422. priv->charbit = 8;
  423. dm_spi_bus->max_hz = plat->speed_hz;
  424. /* default: all CS signals inactive state is high */
  425. mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  426. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  427. fsl_dspi_init_mcr(priv, mcr_cfg_val);
  428. debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
  429. return 0;
  430. }
  431. static int fsl_dspi_claim_bus(struct udevice *dev)
  432. {
  433. uint sr_val;
  434. struct fsl_dspi_priv *priv;
  435. struct udevice *bus = dev->parent;
  436. struct dm_spi_slave_plat *slave_plat =
  437. dev_get_parent_plat(dev);
  438. priv = dev_get_priv(bus);
  439. /* processor special preparation work */
  440. cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);
  441. /* configure transfer mode */
  442. fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
  443. /* configure active state of CSX */
  444. fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
  445. priv->mode);
  446. fsl_dspi_clr_fifo(priv);
  447. /* check module TX and RX status */
  448. sr_val = dspi_read32(priv->flags, &priv->regs->sr);
  449. if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
  450. debug("DSPI RX/TX not ready!\n");
  451. return -EIO;
  452. }
  453. return 0;
  454. }
  455. static int fsl_dspi_release_bus(struct udevice *dev)
  456. {
  457. struct udevice *bus = dev->parent;
  458. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  459. struct dm_spi_slave_plat *slave_plat =
  460. dev_get_parent_plat(dev);
  461. /* halt module */
  462. dspi_halt(priv, 1);
  463. /* processor special release work */
  464. cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);
  465. return 0;
  466. }
  467. /**
  468. * This function doesn't do anything except help with debugging
  469. */
  470. static int fsl_dspi_bind(struct udevice *bus)
  471. {
  472. debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
  473. return 0;
  474. }
  475. static int fsl_dspi_of_to_plat(struct udevice *bus)
  476. {
  477. fdt_addr_t addr;
  478. struct fsl_dspi_plat *plat = dev_get_plat(bus);
  479. const void *blob = gd->fdt_blob;
  480. int node = dev_of_offset(bus);
  481. if (fdtdec_get_bool(blob, node, "big-endian"))
  482. plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
  483. plat->num_chipselect =
  484. fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
  485. addr = dev_read_addr(bus);
  486. if (addr == FDT_ADDR_T_NONE) {
  487. debug("DSPI: Can't get base address or size\n");
  488. return -ENOMEM;
  489. }
  490. plat->regs_addr = addr;
  491. plat->speed_hz = fdtdec_get_int(blob,
  492. node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
  493. debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
  494. &plat->regs_addr, plat->speed_hz,
  495. plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
  496. plat->num_chipselect);
  497. return 0;
  498. }
  499. static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
  500. const void *dout, void *din, unsigned long flags)
  501. {
  502. struct fsl_dspi_priv *priv;
  503. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  504. struct udevice *bus;
  505. bus = dev->parent;
  506. priv = dev_get_priv(bus);
  507. return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
  508. }
  509. static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
  510. {
  511. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  512. return fsl_dspi_cfg_speed(priv, speed);
  513. }
  514. static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
  515. {
  516. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  517. debug("DSPI set_mode: mode 0x%x.\n", mode);
  518. /*
  519. * We store some chipselect special configure value in priv->ctar_val,
  520. * and we can't get the correct chipselect number here,
  521. * so just store mode value.
  522. * Do really configuration when claim_bus.
  523. */
  524. priv->mode = mode;
  525. return 0;
  526. }
  527. static const struct dm_spi_ops fsl_dspi_ops = {
  528. .claim_bus = fsl_dspi_claim_bus,
  529. .release_bus = fsl_dspi_release_bus,
  530. .xfer = fsl_dspi_xfer,
  531. .set_speed = fsl_dspi_set_speed,
  532. .set_mode = fsl_dspi_set_mode,
  533. };
  534. static const struct udevice_id fsl_dspi_ids[] = {
  535. { .compatible = "fsl,vf610-dspi" },
  536. { }
  537. };
  538. U_BOOT_DRIVER(fsl_dspi) = {
  539. .name = "fsl_dspi",
  540. .id = UCLASS_SPI,
  541. .of_match = fsl_dspi_ids,
  542. .ops = &fsl_dspi_ops,
  543. .of_to_plat = fsl_dspi_of_to_plat,
  544. .plat_auto = sizeof(struct fsl_dspi_plat),
  545. .priv_auto = sizeof(struct fsl_dspi_priv),
  546. .probe = fsl_dspi_probe,
  547. .child_pre_probe = fsl_dspi_child_pre_probe,
  548. .bind = fsl_dspi_bind,
  549. };