cf_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. *
  10. * Support for DM and DT, non-DM code removed.
  11. * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
  12. *
  13. * TODO: fsl_dspi.c should work as a driver for the DSPI module.
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <asm/global_data.h>
  19. #include <dm/platform_data/spi_coldfire.h>
  20. #include <spi.h>
  21. #include <malloc.h>
  22. #include <asm/coldfire/dspi.h>
  23. #include <asm/io.h>
  24. struct coldfire_spi_priv {
  25. struct dspi *regs;
  26. uint baudrate;
  27. int mode;
  28. int charbit;
  29. };
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #ifndef CONFIG_SPI_IDLE_VAL
  32. #if defined(CONFIG_SPI_MMC)
  33. #define CONFIG_SPI_IDLE_VAL 0xFFFF
  34. #else
  35. #define CONFIG_SPI_IDLE_VAL 0x0
  36. #endif
  37. #endif
  38. /*
  39. * DSPI specific mode
  40. *
  41. * bit 31 - 28: Transfer size 3 to 16 bits
  42. * 27 - 26: PCS to SCK delay prescaler
  43. * 25 - 24: After SCK delay prescaler
  44. * 23 - 22: Delay after transfer prescaler
  45. * 21 : Allow overwrite for bit 31-22 and bit 20-8
  46. * 20 : Double baud rate
  47. * 19 - 16: PCS to SCK delay scaler
  48. * 15 - 12: After SCK delay scaler
  49. * 11 - 8: Delay after transfer scaler
  50. * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
  51. */
  52. #define SPI_MODE_MOD 0x00200000
  53. #define SPI_MODE_DBLRATE 0x00100000
  54. #define SPI_MODE_XFER_SZ_MASK 0xf0000000
  55. #define SPI_MODE_DLY_PRE_MASK 0x0fc00000
  56. #define SPI_MODE_DLY_SCA_MASK 0x000fff00
  57. #define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
  58. #define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
  59. #define MCF_DSPI_MAX_CTAR_REGS 8
  60. /* Default values */
  61. #define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
  62. #define MCF_DSPI_DEFAULT_MAX_CS 4
  63. #define MCF_DSPI_DEFAULT_MODE 0
  64. #define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
  65. DSPI_CTAR_PCSSCK_1CLK | \
  66. DSPI_CTAR_PASC(0) | \
  67. DSPI_CTAR_PDT(0) | \
  68. DSPI_CTAR_CSSCK(0) | \
  69. DSPI_CTAR_ASC(0) | \
  70. DSPI_CTAR_DT(1) | \
  71. DSPI_CTAR_BR(6))
  72. #define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
  73. DSPI_CTAR_PCSSCK(3) | \
  74. DSPI_CTAR_PASC_7CLK | \
  75. DSPI_CTAR_PDT(3) | \
  76. DSPI_CTAR_CSSCK(0x0f) | \
  77. DSPI_CTAR_ASC(0x0f) | \
  78. DSPI_CTAR_DT(0x0f))
  79. #define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
  80. static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
  81. u32 ctrl, u16 data)
  82. {
  83. /*
  84. * Need to check fifo level here
  85. */
  86. while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
  87. ;
  88. writel(ctrl | data, &cfspi->regs->tfr);
  89. }
  90. static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
  91. {
  92. while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
  93. ;
  94. return readw(&cfspi->regs->rfr);
  95. }
  96. static int coldfire_spi_claim_bus(struct udevice *dev)
  97. {
  98. struct udevice *bus = dev->parent;
  99. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  100. struct dspi *dspi = cfspi->regs;
  101. struct dm_spi_slave_plat *slave_plat =
  102. dev_get_parent_plat(dev);
  103. if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
  104. return -1;
  105. /* Clear FIFO and resume transfer */
  106. clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  107. dspi_chip_select(slave_plat->cs);
  108. return 0;
  109. }
  110. static int coldfire_spi_release_bus(struct udevice *dev)
  111. {
  112. struct udevice *bus = dev->parent;
  113. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  114. struct dspi *dspi = cfspi->regs;
  115. struct dm_spi_slave_plat *slave_plat =
  116. dev_get_parent_plat(dev);
  117. /* Clear FIFO */
  118. clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  119. dspi_chip_unselect(slave_plat->cs);
  120. return 0;
  121. }
  122. static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
  123. const void *dout, void *din,
  124. unsigned long flags)
  125. {
  126. struct udevice *bus = dev_get_parent(dev);
  127. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  128. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  129. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  130. u8 *spi_rd = NULL, *spi_wr = NULL;
  131. static u32 ctrl;
  132. uint len = bitlen >> 3;
  133. if (cfspi->charbit == 16) {
  134. bitlen >>= 1;
  135. spi_wr16 = (u16 *)dout;
  136. spi_rd16 = (u16 *)din;
  137. } else {
  138. spi_wr = (u8 *)dout;
  139. spi_rd = (u8 *)din;
  140. }
  141. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  142. ctrl |= DSPI_TFR_CONT;
  143. ctrl = setup_ctrl(ctrl, slave_plat->cs);
  144. if (len > 1) {
  145. int tmp_len = len - 1;
  146. while (tmp_len--) {
  147. if (dout) {
  148. if (cfspi->charbit == 16)
  149. cfspi_tx(cfspi, ctrl, *spi_wr16++);
  150. else
  151. cfspi_tx(cfspi, ctrl, *spi_wr++);
  152. cfspi_rx(cfspi);
  153. }
  154. if (din) {
  155. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  156. if (cfspi->charbit == 16)
  157. *spi_rd16++ = cfspi_rx(cfspi);
  158. else
  159. *spi_rd++ = cfspi_rx(cfspi);
  160. }
  161. }
  162. len = 1; /* remaining byte */
  163. }
  164. if (flags & SPI_XFER_END)
  165. ctrl &= ~DSPI_TFR_CONT;
  166. if (len) {
  167. if (dout) {
  168. if (cfspi->charbit == 16)
  169. cfspi_tx(cfspi, ctrl, *spi_wr16);
  170. else
  171. cfspi_tx(cfspi, ctrl, *spi_wr);
  172. cfspi_rx(cfspi);
  173. }
  174. if (din) {
  175. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  176. if (cfspi->charbit == 16)
  177. *spi_rd16 = cfspi_rx(cfspi);
  178. else
  179. *spi_rd = cfspi_rx(cfspi);
  180. }
  181. } else {
  182. /* dummy read */
  183. cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
  184. cfspi_rx(cfspi);
  185. }
  186. return 0;
  187. }
  188. static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
  189. {
  190. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  191. struct dspi *dspi = cfspi->regs;
  192. int prescaler[] = { 2, 3, 5, 7 };
  193. int scaler[] = {
  194. 2, 4, 6, 8,
  195. 16, 32, 64, 128,
  196. 256, 512, 1024, 2048,
  197. 4096, 8192, 16384, 32768
  198. };
  199. int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
  200. int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
  201. u32 bus_setup;
  202. cfspi->baudrate = max_hz;
  203. /* Read current setup */
  204. bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
  205. tmp = (prescaler[3] * scaler[15]);
  206. /* Maximum and minimum baudrate it can handle */
  207. if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
  208. (cfspi->baudrate < (gd->bus_clk / tmp))) {
  209. printf("Exceed baudrate limitation: Max %d - Min %d\n",
  210. (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
  211. return -1;
  212. }
  213. /* Activate Double Baud when it exceed 1/4 the bus clk */
  214. if ((bus_setup & DSPI_CTAR_DBR) ||
  215. (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
  216. bus_setup |= DSPI_CTAR_DBR;
  217. dbr = 1;
  218. }
  219. /* Overwrite default value set in platform configuration file */
  220. if (cfspi->mode & SPI_MODE_MOD) {
  221. /*
  222. * Check to see if it is enabled by default in platform
  223. * config, or manual setting passed by mode parameter
  224. */
  225. if (cfspi->mode & SPI_MODE_DBLRATE) {
  226. bus_setup |= DSPI_CTAR_DBR;
  227. dbr = 1;
  228. }
  229. }
  230. pbrcnt = sizeof(prescaler) / sizeof(int);
  231. brcnt = sizeof(scaler) / sizeof(int);
  232. /* baudrate calculation - to closer value, may not be exact match */
  233. for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
  234. baud_speed = gd->bus_clk / prescaler[i];
  235. for (j = 0; j < brcnt; j++) {
  236. tmp = (baud_speed / scaler[j]) * (1 + dbr);
  237. if (tmp > cfspi->baudrate)
  238. diff = tmp - cfspi->baudrate;
  239. else
  240. diff = cfspi->baudrate - tmp;
  241. if (diff < bestmatch) {
  242. bestmatch = diff;
  243. best_i = i;
  244. best_j = j;
  245. }
  246. }
  247. }
  248. bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
  249. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  250. writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
  251. return 0;
  252. }
  253. static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
  254. {
  255. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  256. struct dspi *dspi = cfspi->regs;
  257. u32 bus_setup = 0;
  258. cfspi->mode = mode;
  259. if (cfspi->mode & SPI_CPOL)
  260. bus_setup |= DSPI_CTAR_CPOL;
  261. if (cfspi->mode & SPI_CPHA)
  262. bus_setup |= DSPI_CTAR_CPHA;
  263. if (cfspi->mode & SPI_LSB_FIRST)
  264. bus_setup |= DSPI_CTAR_LSBFE;
  265. /* Overwrite default value set in platform configuration file */
  266. if (cfspi->mode & SPI_MODE_MOD) {
  267. if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
  268. bus_setup |=
  269. readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
  270. else
  271. bus_setup |=
  272. ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
  273. /* PSCSCK, PASC, PDT */
  274. bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
  275. /* CSSCK, ASC, DT */
  276. bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
  277. } else {
  278. bus_setup |=
  279. (readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
  280. }
  281. cfspi->charbit =
  282. ((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
  283. MCF_FRM_SZ_16BIT) ? 16 : 8;
  284. setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
  285. return 0;
  286. }
  287. static int coldfire_spi_probe(struct udevice *bus)
  288. {
  289. struct coldfire_spi_plat *plat = dev_get_plat(bus);
  290. struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
  291. struct dspi *dspi = cfspi->regs;
  292. int i;
  293. cfspi->regs = (struct dspi *)plat->regs_addr;
  294. cfspi->baudrate = plat->speed_hz;
  295. cfspi->mode = plat->mode;
  296. for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
  297. unsigned int ctar = 0;
  298. if (plat->ctar[i][0] == 0)
  299. break;
  300. ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
  301. DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
  302. DSPI_CTAR_PASC(plat->ctar[i][2]) |
  303. DSPI_CTAR_PDT(plat->ctar[i][3]) |
  304. DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
  305. DSPI_CTAR_ASC(plat->ctar[i][5]) |
  306. DSPI_CTAR_DT(plat->ctar[i][6]) |
  307. DSPI_CTAR_BR(plat->ctar[i][7]);
  308. writel(ctar, &cfspi->regs->ctar[i]);
  309. }
  310. /* Default CTARs */
  311. for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
  312. writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
  313. dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
  314. DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
  315. DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
  316. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  317. return 0;
  318. }
  319. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  320. static int coldfire_dspi_of_to_plat(struct udevice *bus)
  321. {
  322. fdt_addr_t addr;
  323. struct coldfire_spi_plat *plat = dev_get_plat(bus);
  324. const void *blob = gd->fdt_blob;
  325. int node = dev_of_offset(bus);
  326. int *ctar, len;
  327. addr = dev_read_addr(bus);
  328. if (addr == FDT_ADDR_T_NONE)
  329. return -ENOMEM;
  330. plat->regs_addr = addr;
  331. plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
  332. MCF_DSPI_DEFAULT_MAX_CS);
  333. plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  334. MCF_DSPI_DEFAULT_SCK_FREQ);
  335. plat->mode = fdtdec_get_int(blob, node, "spi-mode",
  336. MCF_DSPI_DEFAULT_MODE);
  337. memset(plat->ctar, 0, sizeof(plat->ctar));
  338. ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
  339. if (ctar && len) {
  340. int i, q, ctar_regs;
  341. ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
  342. if (ctar_regs > MAX_CTAR_REGS)
  343. ctar_regs = MAX_CTAR_REGS;
  344. for (i = 0; i < ctar_regs; i++) {
  345. for (q = 0; q < MAX_CTAR_FIELDS; q++)
  346. plat->ctar[i][q] = *ctar++;
  347. }
  348. }
  349. debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
  350. (void *)plat->regs_addr,
  351. plat->speed_hz, plat->num_cs, plat->mode);
  352. return 0;
  353. }
  354. static const struct udevice_id coldfire_spi_ids[] = {
  355. { .compatible = "fsl,mcf-dspi" },
  356. { }
  357. };
  358. #endif
  359. static const struct dm_spi_ops coldfire_spi_ops = {
  360. .claim_bus = coldfire_spi_claim_bus,
  361. .release_bus = coldfire_spi_release_bus,
  362. .xfer = coldfire_spi_xfer,
  363. .set_speed = coldfire_spi_set_speed,
  364. .set_mode = coldfire_spi_set_mode,
  365. };
  366. U_BOOT_DRIVER(coldfire_spi) = {
  367. .name = "spi_coldfire",
  368. .id = UCLASS_SPI,
  369. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  370. .of_match = coldfire_spi_ids,
  371. .of_to_plat = coldfire_dspi_of_to_plat,
  372. .plat_auto = sizeof(struct coldfire_spi_plat),
  373. #endif
  374. .probe = coldfire_spi_probe,
  375. .ops = &coldfire_spi_ops,
  376. .priv_auto = sizeof(struct coldfire_spi_priv),
  377. };