samsung-i2s.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. * R. Chandrasekar <rcsekar@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <i2s.h>
  9. #include <log.h>
  10. #include <sound.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/pinmux.h>
  13. #include <asm/arch/i2s-regs.h>
  14. #include <asm/io.h>
  15. #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
  16. #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
  17. #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
  18. #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
  19. #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
  20. #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
  21. /*
  22. * Sets the frame size for I2S LR clock
  23. *
  24. * @param i2s_reg i2s register address
  25. * @param rfs Frame Size
  26. */
  27. static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
  28. {
  29. unsigned int mod = readl(&i2s_reg->mod);
  30. mod &= ~MOD_RCLK_MASK;
  31. switch (rfs) {
  32. case 768:
  33. mod |= MOD_RCLK_768FS;
  34. break;
  35. case 512:
  36. mod |= MOD_RCLK_512FS;
  37. break;
  38. case 384:
  39. mod |= MOD_RCLK_384FS;
  40. break;
  41. default:
  42. mod |= MOD_RCLK_256FS;
  43. break;
  44. }
  45. writel(mod, &i2s_reg->mod);
  46. }
  47. /*
  48. * Sets the i2s transfer control
  49. *
  50. * @param i2s_reg i2s register address
  51. * @param on 1 enable tx , 0 disable tx transfer
  52. */
  53. static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
  54. {
  55. unsigned int con = readl(&i2s_reg->con);
  56. unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
  57. if (on) {
  58. con |= CON_ACTIVE;
  59. con &= ~CON_TXCH_PAUSE;
  60. } else {
  61. con |= CON_TXCH_PAUSE;
  62. con &= ~CON_ACTIVE;
  63. }
  64. writel(mod, &i2s_reg->mod);
  65. writel(con, &i2s_reg->con);
  66. }
  67. /*
  68. * set the bit clock frame size (in multiples of LRCLK)
  69. *
  70. * @param i2s_reg i2s register address
  71. * @param bfs bit Frame Size
  72. */
  73. static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
  74. {
  75. unsigned int mod = readl(&i2s_reg->mod);
  76. mod &= ~MOD_BCLK_MASK;
  77. switch (bfs) {
  78. case 48:
  79. mod |= MOD_BCLK_48FS;
  80. break;
  81. case 32:
  82. mod |= MOD_BCLK_32FS;
  83. break;
  84. case 24:
  85. mod |= MOD_BCLK_24FS;
  86. break;
  87. case 16:
  88. mod |= MOD_BCLK_16FS;
  89. break;
  90. default:
  91. return;
  92. }
  93. writel(mod, &i2s_reg->mod);
  94. }
  95. /*
  96. * flushes the i2stx fifo
  97. *
  98. * @param i2s_reg i2s register address
  99. * @param flush Tx fifo flush command (0x00 - do not flush
  100. * 0x80 - flush tx fifo)
  101. */
  102. static void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
  103. {
  104. /* Flush the FIFO */
  105. setbits_le32(&i2s_reg->fic, flush);
  106. clrbits_le32(&i2s_reg->fic, flush);
  107. }
  108. /*
  109. * Set System Clock direction
  110. *
  111. * @param i2s_reg i2s register address
  112. * @param dir Clock direction
  113. *
  114. * @return int value 0 for success, -1 in case of error
  115. */
  116. static int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
  117. {
  118. unsigned int mod = readl(&i2s_reg->mod);
  119. if (dir == SND_SOC_CLOCK_IN)
  120. mod |= MOD_CDCLKCON;
  121. else
  122. mod &= ~MOD_CDCLKCON;
  123. writel(mod, &i2s_reg->mod);
  124. return 0;
  125. }
  126. /*
  127. * Sets I2S Clcok format
  128. *
  129. * @param fmt i2s clock properties
  130. * @param i2s_reg i2s register address
  131. *
  132. * @return int value 0 for success, -1 in case of error
  133. */
  134. static int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
  135. {
  136. unsigned int mod = readl(&i2s_reg->mod);
  137. unsigned int tmp = 0;
  138. unsigned int ret = 0;
  139. /* Format is priority */
  140. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  141. case SND_SOC_DAIFMT_RIGHT_J:
  142. tmp |= MOD_LR_RLOW;
  143. tmp |= MOD_SDF_MSB;
  144. break;
  145. case SND_SOC_DAIFMT_LEFT_J:
  146. tmp |= MOD_LR_RLOW;
  147. tmp |= MOD_SDF_LSB;
  148. break;
  149. case SND_SOC_DAIFMT_I2S:
  150. tmp |= MOD_SDF_IIS;
  151. break;
  152. default:
  153. debug("%s: Invalid format priority [0x%x]\n", __func__,
  154. (fmt & SND_SOC_DAIFMT_FORMAT_MASK));
  155. return -ERANGE;
  156. }
  157. /*
  158. * INV flag is relative to the FORMAT flag - if set it simply
  159. * flips the polarity specified by the Standard
  160. */
  161. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  162. case SND_SOC_DAIFMT_NB_NF:
  163. break;
  164. case SND_SOC_DAIFMT_NB_IF:
  165. if (tmp & MOD_LR_RLOW)
  166. tmp &= ~MOD_LR_RLOW;
  167. else
  168. tmp |= MOD_LR_RLOW;
  169. break;
  170. default:
  171. debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
  172. (fmt & SND_SOC_DAIFMT_INV_MASK));
  173. return -ERANGE;
  174. }
  175. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  176. case SND_SOC_DAIFMT_CBS_CFS:
  177. tmp |= MOD_SLAVE;
  178. break;
  179. case SND_SOC_DAIFMT_CBM_CFM:
  180. /* Set default source clock in Master mode */
  181. ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
  182. if (ret != 0) {
  183. debug("%s:set i2s clock direction failed\n", __func__);
  184. return ret;
  185. }
  186. break;
  187. default:
  188. debug("%s: Invalid master selection [0x%x]\n", __func__,
  189. (fmt & SND_SOC_DAIFMT_MASTER_MASK));
  190. return -ERANGE;
  191. }
  192. mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
  193. mod |= tmp;
  194. writel(mod, &i2s_reg->mod);
  195. return 0;
  196. }
  197. /*
  198. * Sets the sample width in bits
  199. *
  200. * @param blc samplewidth (size of sample in bits)
  201. * @param i2s_reg i2s register address
  202. *
  203. * @return int value 0 for success, -1 in case of error
  204. */
  205. static int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
  206. {
  207. unsigned int mod = readl(&i2s_reg->mod);
  208. mod &= ~MOD_BLCP_MASK;
  209. mod &= ~MOD_BLC_MASK;
  210. switch (blc) {
  211. case 8:
  212. mod |= MOD_BLCP_8BIT;
  213. mod |= MOD_BLC_8BIT;
  214. break;
  215. case 16:
  216. mod |= MOD_BLCP_16BIT;
  217. mod |= MOD_BLC_16BIT;
  218. break;
  219. case 24:
  220. mod |= MOD_BLCP_24BIT;
  221. mod |= MOD_BLC_24BIT;
  222. break;
  223. default:
  224. debug("%s: Invalid sample size input [0x%x]\n",
  225. __func__, blc);
  226. return -ERANGE;
  227. }
  228. writel(mod, &i2s_reg->mod);
  229. return 0;
  230. }
  231. int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data,
  232. uint data_size)
  233. {
  234. struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address;
  235. u32 *ptr;
  236. int i;
  237. int start;
  238. if (data_size < FIFO_LENGTH) {
  239. debug("%s : Invalid data size\n", __func__);
  240. return -ENODATA; /* invalid pcm data size */
  241. }
  242. /* fill the tx buffer before stating the tx transmit */
  243. for (i = 0, ptr = data; i < FIFO_LENGTH; i++)
  244. writel(*ptr++, &i2s_reg->txd);
  245. data_size -= sizeof(*ptr) * FIFO_LENGTH;
  246. i2s_txctrl(i2s_reg, I2S_TX_ON);
  247. while (data_size > 0) {
  248. start = get_timer(0);
  249. if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
  250. writel(*ptr++, &i2s_reg->txd);
  251. data_size -= sizeof(*ptr);
  252. } else {
  253. if (get_timer(start) > TIMEOUT_I2S_TX) {
  254. i2s_txctrl(i2s_reg, I2S_TX_OFF);
  255. debug("%s: I2S Transfer Timeout\n", __func__);
  256. return -ETIMEDOUT;
  257. }
  258. }
  259. }
  260. i2s_txctrl(i2s_reg, I2S_TX_OFF);
  261. return 0;
  262. }
  263. static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
  264. {
  265. int ret;
  266. struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address;
  267. if (pi2s_tx->id == 0) {
  268. /* Initialize GPIO for I2S-0 */
  269. exynos_pinmux_config(PERIPH_ID_I2S0, 0);
  270. /* Set EPLL Clock */
  271. ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
  272. } else if (pi2s_tx->id == 1) {
  273. /* Initialize GPIO for I2S-1 */
  274. exynos_pinmux_config(PERIPH_ID_I2S1, 0);
  275. /* Set EPLL Clock */
  276. ret = set_epll_clk(pi2s_tx->audio_pll_clk);
  277. } else {
  278. debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id);
  279. return -ERANGE;
  280. }
  281. if (ret) {
  282. debug("%s: epll clock set rate failed\n", __func__);
  283. return ret;
  284. }
  285. /* Select Clk Source for Audio 0 or 1 */
  286. ret = set_i2s_clk_source(pi2s_tx->id);
  287. if (ret) {
  288. debug("%s: unsupported clock for i2s-%d\n", __func__,
  289. pi2s_tx->id);
  290. return ret;
  291. }
  292. if (pi2s_tx->id == 0) {
  293. /*Reset the i2s module */
  294. writel(CON_RESET, &i2s_reg->con);
  295. writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
  296. /* set i2s prescaler */
  297. writel(PSREN | PSVAL, &i2s_reg->psr);
  298. } else {
  299. /* Set Prescaler to get MCLK */
  300. ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
  301. (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
  302. pi2s_tx->id);
  303. }
  304. if (ret) {
  305. debug("%s: unsupported prescalar for i2s-%d\n", __func__,
  306. pi2s_tx->id);
  307. return ret;
  308. }
  309. /* Configure I2s format */
  310. ret = i2s_set_fmt(i2s_reg, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  311. SND_SOC_DAIFMT_CBM_CFM);
  312. if (ret == 0) {
  313. i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
  314. ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
  315. if (ret != 0) {
  316. debug("%s:set sample rate failed\n", __func__);
  317. return ret;
  318. }
  319. i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
  320. /* disable i2s transfer flag and flush the fifo */
  321. i2s_txctrl(i2s_reg, I2S_TX_OFF);
  322. i2s_fifo(i2s_reg, FIC_TXFLUSH);
  323. } else {
  324. debug("%s: failed\n", __func__);
  325. }
  326. return ret;
  327. }
  328. static int samsung_i2s_tx_data(struct udevice *dev, void *data, uint data_size)
  329. {
  330. struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
  331. return i2s_transfer_tx_data(priv, data, data_size);
  332. }
  333. static int samsung_i2s_probe(struct udevice *dev)
  334. {
  335. struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
  336. return i2s_tx_init(priv);
  337. }
  338. static int samsung_i2s_of_to_plat(struct udevice *dev)
  339. {
  340. struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
  341. ulong base;
  342. /*
  343. * Get the pre-defined sound specific values from FDT.
  344. * All of these are expected to be correct otherwise
  345. * wrong register values in i2s setup parameters
  346. * may result in no sound play.
  347. */
  348. base = dev_read_addr(dev);
  349. if (base == FDT_ADDR_T_NONE) {
  350. debug("%s: Missing i2s base\n", __func__);
  351. return -EINVAL;
  352. }
  353. priv->base_address = base;
  354. if (dev_read_u32u(dev, "samsung,i2s-epll-clock-frequency",
  355. &priv->audio_pll_clk))
  356. goto err;
  357. debug("audio_pll_clk = %d\n", priv->audio_pll_clk);
  358. if (dev_read_u32u(dev, "samsung,i2s-sampling-rate",
  359. &priv->samplingrate))
  360. goto err;
  361. debug("samplingrate = %d\n", priv->samplingrate);
  362. if (dev_read_u32u(dev, "samsung,i2s-bits-per-sample",
  363. &priv->bitspersample))
  364. goto err;
  365. debug("bitspersample = %d\n", priv->bitspersample);
  366. if (dev_read_u32u(dev, "samsung,i2s-channels", &priv->channels))
  367. goto err;
  368. debug("channels = %d\n", priv->channels);
  369. if (dev_read_u32u(dev, "samsung,i2s-lr-clk-framesize", &priv->rfs))
  370. goto err;
  371. debug("rfs = %d\n", priv->rfs);
  372. if (dev_read_u32u(dev, "samsung,i2s-bit-clk-framesize", &priv->bfs))
  373. goto err;
  374. debug("bfs = %d\n", priv->bfs);
  375. if (dev_read_u32u(dev, "samsung,i2s-id", &priv->id))
  376. goto err;
  377. debug("id = %d\n", priv->id);
  378. return 0;
  379. err:
  380. debug("fail to get sound i2s node properties\n");
  381. return -EINVAL;
  382. }
  383. static const struct i2s_ops samsung_i2s_ops = {
  384. .tx_data = samsung_i2s_tx_data,
  385. };
  386. static const struct udevice_id samsung_i2s_ids[] = {
  387. { .compatible = "samsung,s5pv210-i2s" },
  388. { }
  389. };
  390. U_BOOT_DRIVER(samsung_i2s) = {
  391. .name = "samsung_i2s",
  392. .id = UCLASS_I2S,
  393. .of_match = samsung_i2s_ids,
  394. .probe = samsung_i2s_probe,
  395. .of_to_plat = samsung_i2s_of_to_plat,
  396. .ops = &samsung_i2s_ops,
  397. };