broadwell_i2s.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Intel Broadwell I2S driver
  4. *
  5. * Copyright 2019 Google LLC
  6. *
  7. * Modified from dc i2s/broadwell/broadwell.h
  8. */
  9. #ifndef __BROADWELL_I2S_H__
  10. #define __BROADWELL_I2S_H__
  11. enum {
  12. SSP_FIFO_SIZE = 7,
  13. };
  14. enum frame_sync_rel_timing_t {
  15. NEXT_FRMS_AFTER_END_OF_T4 = 0,
  16. NEXT_FRMS_WITH_LSB_PREVIOUS_FRM,
  17. };
  18. enum frame_sync_pol_t {
  19. SSP_FRMS_ACTIVE_LOW = 0,
  20. SSP_FRMS_ACTIVE_HIGH,
  21. };
  22. enum end_transfer_state_t {
  23. SSP_END_TRANSFER_STATE_LOW = 0,
  24. SSP_END_TRANSFER_STATE_PEVIOUS_BIT,
  25. };
  26. enum clock_mode_t {
  27. /* Data driven (falling), data sampled (rising), idle state (low) */
  28. SCLK_MODE_DDF_DSR_ISL,
  29. /* Data driven (rising), data sampled (falling), idle state (low) */
  30. SCLK_MODE_DDR_DSF_ISL,
  31. /* Data driven (rising), data sampled (falling), idle state (high) */
  32. SCLK_MODE_DDR_DSF_ISH,
  33. /* Data driven (falling), data sampled (rising), idle state (high) */
  34. SCLK_MODE_DDF_DSR_ISH,
  35. };
  36. struct i2s_shim_regs {
  37. u32 csr; /* 0x00 */
  38. u32 reserved0[29]; /* 0x14 - 0x77 */
  39. u32 clkctl; /* 0x78 */
  40. u32 reserved1; /* 0x7c */
  41. u32 cs2; /* 0x80 */
  42. };
  43. struct broadwell_i2s_regs {
  44. u32 sscr0; /* 0x00 */
  45. u32 sscr1; /* 0x04 */
  46. u32 sssr; /* 0x08 */
  47. u32 ssitr; /* 0x0c */
  48. u32 ssdr; /* 0x10 */
  49. u32 reserved0[5]; /* 0x14 - 0x27 */
  50. u32 ssto; /* 0x28 */
  51. u32 sspsp; /* 0x2c */
  52. u32 sstsa; /* 0x30 */
  53. u32 ssrsa; /* 0x34 */
  54. u32 sstss; /* 0x38 */
  55. u32 sscr2; /* 0x40 */
  56. u32 sspsp2; /* 0x44 */
  57. };
  58. /* SHIM Configuration & Status */
  59. enum {
  60. /* Low Power Clock Select */
  61. SHIM_CS_LPCS = 1 << 31,
  62. /* SSP Force Clock Running */
  63. SHIM_CS_SFCR_SSP1 = 1 << 28,
  64. SHIM_CS_SFCR_SSP0 = 1 << 27,
  65. /* SSP1 IO Clock Select */
  66. SHIM_CS_S1IOCS = 1 << 23,
  67. /* SSP0 IO Clock Select */
  68. SHIM_CS_S0IOCS = 1 << 21,
  69. /* Parity Check Enable */
  70. SHIM_CS_PCE = 1 << 15,
  71. /* SSP DMA or PIO Mode */
  72. SHIM_CS_SDPM_PIO_SSP1 = 1 << 12,
  73. SHIM_CS_SDPM_DMA_SSP1 = 0 << 12,
  74. SHIM_CS_SDPM_PIO_SSP0 = 1 << 11,
  75. SHIM_CS_SDPM_DMA_SSP0 = 0 << 11,
  76. /* Run / Stall */
  77. SHIM_CS_STALL = 1 << 10,
  78. /* DSP Clock Select */
  79. SHIM_CS_DCS_DSP320_AF80 = 0 << 4,
  80. SHIM_CS_DCS_DSP160_AF80 = 1 << 4,
  81. SHIM_CS_DCS_DSP80_AF80 = 2 << 4,
  82. SHIM_CS_DCS_DSP320_AF160 = 4 << 4,
  83. SHIM_CS_DCS_DSP160_AF160 = 5 << 4,
  84. SHIM_CS_DCS_DSP32_AF32 = 6 << 4,
  85. SHIM_CS_DCS_MASK = 7 << 4,
  86. /* SSP Base Clock Select */
  87. SHIM_CS_SBCS_SSP0_24MHZ = 1 << 3,
  88. SHIM_CS_SBCS_SSP0_32MHZ = 0 << 3,
  89. SHIM_CS_SBCS_SSP1_24MHZ = 1 << 2,
  90. SHIM_CS_SBCS_SSP1_32MHZ = 0 << 2,
  91. /* DSP Core Reset */
  92. SHIM_CS_RST = 1 << 1,
  93. };
  94. /* SHIM Clock Control */
  95. enum {
  96. /* Clock Frequency Change In Progress */
  97. SHIM_CLKCTL_CFCIP = 1 << 31,
  98. /* SSP MCLK Output Select */
  99. SHIM_CLKCTL_MCLK_MASK = 0x3,
  100. SHIM_CLKCTL_MCLK_SHIFT = 24,
  101. SHIM_CLKCTL_MCLK_DISABLED = 0 << 24,
  102. SHIM_CLKCTL_MCLK_6MHZ = 1 << 24,
  103. SHIM_CLKCTL_MCLK_12MHZ = 2 << 24,
  104. SHIM_CLKCTL_MCLK_24MHZ = 3 << 24,
  105. /* DSP Core Prevent Local Clock Gating */
  106. SHIM_CLKCTL_DCPLCG = 1 << 18,
  107. /* SSP Clock Output Enable */
  108. SHIM_CLKCTL_SCOE_SSP1 = 1 << 17,
  109. SHIM_CLKCTL_SCOE_SSP0 = 1 << 16,
  110. /* DMA Engine Force Local Clock Gating */
  111. SHIM_CLKCTL_DEFLCGB_DMA1_CGE = 0 << 6,
  112. SHIM_CLKCTL_DEFLCGB_DMA1_CGD = 1 << 6,
  113. SHIM_CLKCTL_DEFLCGB_DMA0_CGE = 0 << 5,
  114. SHIM_CLKCTL_DEFLCGB_DMA0_CGD = 1 << 5,
  115. /* SSP Force Local Clock Gating */
  116. SHIM_CLKCTL_SFLCGB_SSP1_CGE = 0 << 1,
  117. SHIM_CLKCTL_SFLCGB_SSP1_CGD = 1 << 1,
  118. SHIM_CLKCTL_SFLCGB_SSP0_CGE = 0 << 0,
  119. SHIM_CLKCTL_SFLCGB_SSP0_CGD = 1 << 0,
  120. /* Reserved bits: 30:26, 23:19, 15:7, 4:2 */
  121. SHIM_CLKCTL_RESERVED = 0x1f << 26 | 0x1f << 19 | 0x1ff << 7 | 0x7 << 2,
  122. };
  123. /* SSP Status */
  124. enum {
  125. /* Bit Count Error */
  126. SSP_SSS_BCE = 1 << 23,
  127. /* Clock Sync Statu s*/
  128. SSP_SSS_CSS = 1 << 22,
  129. /* Transmit FIFO Underrun */
  130. SSP_SSS_TUR = 1 << 21,
  131. /* End Of Chain */
  132. SSP_SSS_EOC = 1 << 20,
  133. /* Receiver Time-out Interrupt */
  134. SSP_SSS_TINT = 1 << 19,
  135. /* Peripheral Trailing Byte Interrupt */
  136. SSP_SSS_PINT = 1 << 18,
  137. /* Received FIFO Level */
  138. SSP_RFL_MASK = 0xf,
  139. SSP_RFL_SHIFT = 12,
  140. /* Transmit FIFO Level */
  141. SSP_TFL_MASK = 0xf,
  142. SSP_TFL_SHIFT = 8,
  143. /* Receive FIFO Overrun */
  144. SSP_SSS_ROR = 1 << 7,
  145. /* Receive FIFO Service Request */
  146. SSP_SSS_RFS = 1 << 6,
  147. /* Transmit FIFO Service Request */
  148. SSP_SSS_TFS = 1 << 5,
  149. /* SSP Busy */
  150. SSP_SSS_BSY = 1 << 4,
  151. /* Receive FIFO Not Empty */
  152. SSP_SSS_RNE = 1 << 3,
  153. /* Transmit FIFO Not Full */
  154. SSP_SSS_TNF = 1 << 2,
  155. };
  156. /* SSP Control 0 */
  157. enum {
  158. /* Mode */
  159. SSP_SSC0_MODE_NORMAL = 0 << 31,
  160. SSP_SSC0_MODE_NETWORK = 1 << 31,
  161. /* Audio Clock Select */
  162. SSP_SSC0_ACS_PCH = 0 << 30,
  163. /* Frame Rate Divider Control (0-7) */
  164. SSP_SSC0_FRDC_MASK = 0x7,
  165. SSP_SSC0_FRDC_SHIFT = 24,
  166. SSP_SSC0_FRDC_STEREO = 1 << 24,
  167. /* Transmit FIFO Underrun Interrupt Mask */
  168. SSP_SSC0_TIM = 1 << 23,
  169. /* Receive FIFO Underrun Interrupt Mask */
  170. SSP_SSC0_RIM = 1 << 22,
  171. /* Network Clock Select */
  172. SSP_SSC0_NCS_PCH = 0 << 21,
  173. /* Extended Data Size Select */
  174. SSP_SSC0_EDSS = 1 << 20,
  175. /* Serial Clock Rate (0-4095) */
  176. SSP_SSC0_SCR_SHIFT = 8,
  177. SSP_SSC0_SCR_MASK = 0xfff << SSP_SSC0_SCR_SHIFT,
  178. /* Synchronous Serial Port Enable */
  179. SSP_SSC0_SSE = 1 << 7,
  180. /* External Clock Select */
  181. SSP_SSC0_ECS_PCH = 0 << 6,
  182. /* Frame Format */
  183. SSP_SSC0_FRF_MOTOROLA_SPI = 0 << 4,
  184. SSP_SSC0_FRF_TI_SSP = 1 << 4,
  185. SSP_SSC0_FRF_NS_MICROWIRE = 2 << 4,
  186. SSP_SSC0_FRF_PSP = 3 << 4,
  187. /* Data Size Select */
  188. SSP_SSC0_DSS_SHIFT = 0,
  189. SSP_SSC0_DSS_MASK = 0xf << SSP_SSC0_DSS_SHIFT,
  190. };
  191. /* SSP Control 1 */
  192. enum {
  193. /* TXD Tristate Enable on Last Phase */
  194. SSP_SSC1_TTELP = 1 << 31,
  195. /* TXD Tristate Enable */
  196. SSP_SSC1_TTE = 1 << 30,
  197. /* Enable Bit Count Error Interrupt */
  198. SSP_SSC1_EBCEI = 1 << 29,
  199. /* Slave Clock Running */
  200. SSP_SSC1_SCFR = 1 << 28,
  201. /* Enable Clock Request A */
  202. SSP_SSC1_ECRA = 1 << 27,
  203. /* Enable Clock Request B */
  204. SSP_SSC1_ECRB = 1 << 26,
  205. /* SSPCLK Direction */
  206. SSP_SSC1_SCLKDIR_SLAVE = 1 << 25,
  207. SSP_SSC1_SCLKDIR_MASTER = 0 << 25,
  208. /* SSPFRM Direction */
  209. SSP_SSC1_SFRMDIR_SLAVE = 1 << 24,
  210. SSP_SSC1_SFRMDIR_MASTER = 0 << 24,
  211. /* Receive without Transmit */
  212. SSP_SSC1_RWOT = 1 << 23,
  213. /* Trailing Byte */
  214. SSP_SSC1_TRAIL = 1 << 22,
  215. /* DMA Tx Service Request Enable */
  216. SSP_SSC1_TSRE = 1 << 21,
  217. /* DMA Rx Service Request Enable */
  218. SSP_SSC1_RSRE = 1 << 20,
  219. /* Receiver Timeout Interrupt Enable */
  220. SSP_SSC1_TINTE = 1 << 19,
  221. /* Periph. Trailing Byte Int. Enable */
  222. SSP_SSC1_PINTE = 1 << 18,
  223. /* Invert Frame Signal */
  224. SSP_SSC1_IFS = 1 << 16,
  225. /* Select FIFO for EFWR: test mode */
  226. SSP_SSC1_STRF = 1 << 15,
  227. /* Enable FIFO Write/Read: test mode */
  228. SSP_SSC1_EFWR = 1 << 14,
  229. /* Receive FIFO Trigger Threshold */
  230. SSP_SSC1_RFT_SHIFT = 10,
  231. SSP_SSC1_RFT_MASK = 0xf << SSP_SSC1_RFT_SHIFT,
  232. /* Transmit FIFO Trigger Threshold */
  233. SSP_SSC1_TFT_SHIFT = 6,
  234. SSP_SSC1_TFT_MASK = 0xf << SSP_SSC1_TFT_SHIFT,
  235. /* Microwire Transmit Data Size */
  236. SSP_SSC1_MWDS = 1 << 5,
  237. /* Motorola SPI SSPSCLK Phase Setting*/
  238. SSP_SSC1_SPH = 1 << 4,
  239. /* Motorola SPI SSPSCLK Polarity */
  240. SSP_SSC1_SPO = 1 << 3,
  241. /* Loopback mode: test mode */
  242. SSP_SSC1_LBM = 1 << 2,
  243. /* Transmit FIFO Interrupt Enable */
  244. SSP_SSC1_TIE = 1 << 1,
  245. /* Receive FIFO Interrupt Enable */
  246. SSP_SSC1_RIE = 1 << 0,
  247. SSP_SSC1_RESERVED = 17 << 1,
  248. };
  249. /* SSP Programmable Serial Protocol */
  250. enum {
  251. /* Extended Dummy Stop (0-31) */
  252. SSP_PSP_EDYMSTOP_SHIFT = 26,
  253. SSP_PSP_EDMYSTOP_MASK = 0x7 << SSP_PSP_EDYMSTOP_SHIFT,
  254. /* Frame Sync Relative Timing */
  255. SSP_PSP_FSRT = 1 << 25,
  256. /* Dummy Stop low bits */
  257. SSP_PSP_DMYSTOP_SHIFT = 23,
  258. SSP_PSP_DMYSTOP_MASK = 0x3 << SSP_PSP_DMYSTOP_SHIFT,
  259. /* Serial Frame Width */
  260. SSP_PSP_SFRMWDTH_SHIFT = 16,
  261. SSP_PSP_SFRMWDTH_MASK = 0x3f << SSP_PSP_SFRMWDTH_SHIFT,
  262. /* Serial Frame Delay */
  263. SSP_PSP_SFRMDLY_MASK = 0x7f,
  264. SSP_PSP_SFRMDLY_SHIFT = 9,
  265. /* Start Delay */
  266. SSP_PSP_STRTDLY_MASK = 0x7,
  267. SSP_PSP_STRTDLY_SHIFT = 4,
  268. /* End of Transfer Data State */
  269. SSP_PSP_ETDS = 1 << 3,
  270. /* Serial Frame Polarity */
  271. SSP_PSP_SFRMP = 1 << 2,
  272. /* Serial Clock Mode */
  273. SSP_PSP_SCMODE_SHIFT = 0,
  274. SSP_PSP_SCMODE_MASK = 0x3 << SSP_PSP_SCMODE_SHIFT,
  275. SSP_PSP_RESERVED = 1 << 22,
  276. };
  277. /* SSP TX Time Slot Active */
  278. enum {
  279. SSP_SSTSA_EN = 1 << 8,
  280. SSP_SSTSA_MASK = 0xff,
  281. };
  282. #endif /* __BROADWELL_I2S_H__ */