serial_zynq.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <log.h>
  13. #include <watchdog.h>
  14. #include <asm/io.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/compiler.h>
  18. #include <serial.h>
  19. #include <linux/err.h>
  20. #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
  21. #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
  22. #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
  23. #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
  24. #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
  25. #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
  26. #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
  27. #define ZYNQ_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
  28. #define ZYNQ_UART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */
  29. #define ZYNQ_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
  30. #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
  31. #define ZYNQ_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
  32. #define ZYNQ_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
  33. #define ZYNQ_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
  34. #define ZYNQ_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
  35. #define ZYNQ_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
  36. struct uart_zynq {
  37. u32 control; /* 0x0 - Control Register [8:0] */
  38. u32 mode; /* 0x4 - Mode Register [10:0] */
  39. u32 reserved1[4];
  40. u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  41. u32 reserved2[4];
  42. u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  43. u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  44. u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  45. };
  46. struct zynq_uart_plat {
  47. struct uart_zynq *regs;
  48. };
  49. /* Set up the baud rate */
  50. static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  51. unsigned long clock, unsigned long baud)
  52. {
  53. /* Calculation results. */
  54. unsigned int calc_bauderror, bdiv, bgen;
  55. unsigned long calc_baud = 0;
  56. /* Covering case where input clock is so slow */
  57. if (clock < 1000000 && baud > 4800)
  58. baud = 4800;
  59. /* master clock
  60. * Baud rate = ------------------
  61. * bgen * (bdiv + 1)
  62. *
  63. * Find acceptable values for baud generation.
  64. */
  65. for (bdiv = 4; bdiv < 255; bdiv++) {
  66. bgen = clock / (baud * (bdiv + 1));
  67. if (bgen < 2 || bgen > 65535)
  68. continue;
  69. calc_baud = clock / (bgen * (bdiv + 1));
  70. /*
  71. * Use first calculated baudrate with
  72. * an acceptable (<3%) error
  73. */
  74. if (baud > calc_baud)
  75. calc_bauderror = baud - calc_baud;
  76. else
  77. calc_bauderror = calc_baud - baud;
  78. if (((calc_bauderror * 100) / baud) < 3)
  79. break;
  80. }
  81. writel(bdiv, &regs->baud_rate_divider);
  82. writel(bgen, &regs->baud_rate_gen);
  83. }
  84. /* Initialize the UART, with...some settings. */
  85. static void _uart_zynq_serial_init(struct uart_zynq *regs)
  86. {
  87. /* RX/TX enabled & reset */
  88. writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  89. ZYNQ_UART_CR_RXRST, &regs->control);
  90. writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  91. }
  92. static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
  93. {
  94. if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
  95. return -EAGAIN;
  96. writel(c, &regs->tx_rx_fifo);
  97. return 0;
  98. }
  99. static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
  100. {
  101. struct zynq_uart_plat *plat = dev_get_plat(dev);
  102. unsigned long clock;
  103. int ret;
  104. struct clk clk;
  105. ret = clk_get_by_index(dev, 0, &clk);
  106. if (ret < 0) {
  107. dev_err(dev, "failed to get clock\n");
  108. return ret;
  109. }
  110. clock = clk_get_rate(&clk);
  111. if (IS_ERR_VALUE(clock)) {
  112. dev_err(dev, "failed to get rate\n");
  113. return clock;
  114. }
  115. debug("%s: CLK %ld\n", __func__, clock);
  116. ret = clk_enable(&clk);
  117. if (ret) {
  118. dev_err(dev, "failed to enable clock\n");
  119. return ret;
  120. }
  121. _uart_zynq_serial_setbrg(plat->regs, clock, baudrate);
  122. return 0;
  123. }
  124. #if !defined(CONFIG_SPL_BUILD)
  125. static int zynq_serial_setconfig(struct udevice *dev, uint serial_config)
  126. {
  127. struct zynq_uart_plat *plat = dev_get_plat(dev);
  128. struct uart_zynq *regs = plat->regs;
  129. u32 val = 0;
  130. switch (SERIAL_GET_BITS(serial_config)) {
  131. case SERIAL_6_BITS:
  132. val |= ZYNQ_UART_MR_CHARLEN_6_BIT;
  133. break;
  134. case SERIAL_7_BITS:
  135. val |= ZYNQ_UART_MR_CHARLEN_7_BIT;
  136. break;
  137. case SERIAL_8_BITS:
  138. val |= ZYNQ_UART_MR_CHARLEN_8_BIT;
  139. break;
  140. default:
  141. return -ENOTSUPP; /* not supported in driver */
  142. }
  143. switch (SERIAL_GET_STOP(serial_config)) {
  144. case SERIAL_ONE_STOP:
  145. val |= ZYNQ_UART_MR_STOPMODE_1_BIT;
  146. break;
  147. case SERIAL_ONE_HALF_STOP:
  148. val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT;
  149. break;
  150. case SERIAL_TWO_STOP:
  151. val |= ZYNQ_UART_MR_STOPMODE_2_BIT;
  152. break;
  153. default:
  154. return -ENOTSUPP; /* not supported in driver */
  155. }
  156. switch (SERIAL_GET_PARITY(serial_config)) {
  157. case SERIAL_PAR_NONE:
  158. val |= ZYNQ_UART_MR_PARITY_NONE;
  159. break;
  160. case SERIAL_PAR_ODD:
  161. val |= ZYNQ_UART_MR_PARITY_ODD;
  162. break;
  163. case SERIAL_PAR_EVEN:
  164. val |= ZYNQ_UART_MR_PARITY_EVEN;
  165. break;
  166. default:
  167. return -ENOTSUPP; /* not supported in driver */
  168. }
  169. writel(val, &regs->mode);
  170. return 0;
  171. }
  172. #else
  173. #define zynq_serial_setconfig NULL
  174. #endif
  175. static int zynq_serial_probe(struct udevice *dev)
  176. {
  177. struct zynq_uart_plat *plat = dev_get_plat(dev);
  178. struct uart_zynq *regs = plat->regs;
  179. u32 val;
  180. /* No need to reinitialize the UART if TX already enabled */
  181. val = readl(&regs->control);
  182. if (val & ZYNQ_UART_CR_TX_EN)
  183. return 0;
  184. _uart_zynq_serial_init(plat->regs);
  185. return 0;
  186. }
  187. static int zynq_serial_getc(struct udevice *dev)
  188. {
  189. struct zynq_uart_plat *plat = dev_get_plat(dev);
  190. struct uart_zynq *regs = plat->regs;
  191. if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
  192. return -EAGAIN;
  193. return readl(&regs->tx_rx_fifo);
  194. }
  195. static int zynq_serial_putc(struct udevice *dev, const char ch)
  196. {
  197. struct zynq_uart_plat *plat = dev_get_plat(dev);
  198. return _uart_zynq_serial_putc(plat->regs, ch);
  199. }
  200. static int zynq_serial_pending(struct udevice *dev, bool input)
  201. {
  202. struct zynq_uart_plat *plat = dev_get_plat(dev);
  203. struct uart_zynq *regs = plat->regs;
  204. if (input)
  205. return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
  206. else
  207. return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
  208. }
  209. static int zynq_serial_of_to_plat(struct udevice *dev)
  210. {
  211. struct zynq_uart_plat *plat = dev_get_plat(dev);
  212. plat->regs = (struct uart_zynq *)dev_read_addr(dev);
  213. if (IS_ERR(plat->regs))
  214. return PTR_ERR(plat->regs);
  215. return 0;
  216. }
  217. static const struct dm_serial_ops zynq_serial_ops = {
  218. .putc = zynq_serial_putc,
  219. .pending = zynq_serial_pending,
  220. .getc = zynq_serial_getc,
  221. .setbrg = zynq_serial_setbrg,
  222. .setconfig = zynq_serial_setconfig,
  223. };
  224. static const struct udevice_id zynq_serial_ids[] = {
  225. { .compatible = "xlnx,xuartps" },
  226. { .compatible = "cdns,uart-r1p8" },
  227. { .compatible = "cdns,uart-r1p12" },
  228. { }
  229. };
  230. U_BOOT_DRIVER(serial_zynq) = {
  231. .name = "serial_zynq",
  232. .id = UCLASS_SERIAL,
  233. .of_match = zynq_serial_ids,
  234. .of_to_plat = zynq_serial_of_to_plat,
  235. .plat_auto = sizeof(struct zynq_uart_plat),
  236. .probe = zynq_serial_probe,
  237. .ops = &zynq_serial_ops,
  238. };
  239. #ifdef CONFIG_DEBUG_UART_ZYNQ
  240. static inline void _debug_uart_init(void)
  241. {
  242. struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
  243. _uart_zynq_serial_init(regs);
  244. _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
  245. CONFIG_BAUDRATE);
  246. }
  247. static inline void _debug_uart_putc(int ch)
  248. {
  249. struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
  250. while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
  251. WATCHDOG_RESET();
  252. }
  253. DEBUG_UART_FUNCS
  254. #endif