serial_sh.h 17 KB

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  1. /*
  2. * Copy and modify from linux/drivers/serial/sh-sci.h
  3. */
  4. #include <dm/platform_data/serial_sh.h>
  5. struct uart_port {
  6. unsigned long iobase; /* in/out[bwl] */
  7. unsigned char *membase; /* read/write[bwl] */
  8. unsigned long mapbase; /* for ioremap */
  9. enum sh_serial_type type; /* port type */
  10. enum sh_clk_mode clk_mode; /* clock mode */
  11. };
  12. #if defined(CONFIG_CPU_SH7721) || \
  13. defined(CONFIG_SH73A0) || \
  14. defined(CONFIG_R8A7740)
  15. # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  16. # define PORT_PTCR 0xA405011EUL
  17. # define PORT_PVCR 0xA4050122UL
  18. # define SCIF_ORER 0x0200 /* overrun error bit */
  19. #elif defined(CONFIG_CPU_SH7750) || \
  20. defined(CONFIG_CPU_SH7750R) || \
  21. defined(CONFIG_CPU_SH7750S) || \
  22. defined(CONFIG_CPU_SH7751) || \
  23. defined(CONFIG_CPU_SH7751R)
  24. # define SCSPTR1 0xffe0001c /* 8 bit SCI */
  25. # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  26. # define SCIF_ORER 0x0001 /* overrun error bit */
  27. # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  28. 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  29. 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
  30. #elif defined(CONFIG_CPU_SH7722)
  31. # define PADR 0xA4050120
  32. # undef PSDR
  33. # define PSDR 0xA405013e
  34. # define PWDR 0xA4050166
  35. # define PSCR 0xA405011E
  36. # define SCIF_ORER 0x0001 /* overrun error bit */
  37. # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  38. #elif defined(CONFIG_CPU_SH7723)
  39. # define SCSPTR0 0xa4050160
  40. # define SCSPTR1 0xa405013e
  41. # define SCSPTR2 0xa4050160
  42. # define SCSPTR3 0xa405013e
  43. # define SCSPTR4 0xa4050128
  44. # define SCSPTR5 0xa4050128
  45. # define SCIF_ORER 0x0001 /* overrun error bit */
  46. # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  47. #elif defined(CONFIG_CPU_SH7734)
  48. # define SCSPTR0 0xFFE40020
  49. # define SCSPTR1 0xFFE41020
  50. # define SCSPTR2 0xFFE42020
  51. # define SCSPTR3 0xFFE43020
  52. # define SCSPTR4 0xFFE44020
  53. # define SCSPTR5 0xFFE45020
  54. # define SCIF_ORER 0x0001 /* overrun error bit */
  55. # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  56. #elif defined(CONFIG_CPU_SH7757) || \
  57. defined(CONFIG_CPU_SH7752) || \
  58. defined(CONFIG_CPU_SH7753)
  59. # define SCSPTR0 0xfe4b0020
  60. # define SCSPTR1 0xfe4b0020
  61. # define SCSPTR2 0xfe4b0020
  62. # define SCIF_ORER 0x0001
  63. # define SCSCR_INIT(port) 0x38
  64. # define SCIF_ONLY
  65. #elif defined(CONFIG_CPU_SH7763)
  66. # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
  67. # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
  68. # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
  69. # define SCIF_ORER 0x0001 /* overrun error bit */
  70. # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  71. #elif defined(CONFIG_CPU_SH7780)
  72. # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
  73. # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
  74. # define SCIF_ORER 0x0001 /* Overrun error bit */
  75. /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
  76. # define SCSCR_INIT(port) 0x3a
  77. #elif defined(CONFIG_RZA1)
  78. # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
  79. # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
  80. # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
  81. # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
  82. # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
  83. # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
  84. # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
  85. # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
  86. # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  87. # define SCIF_ORER 0x0001 /* overrun error bit */
  88. #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
  89. defined(CONFIG_R7S72100)
  90. # if defined(CONFIG_SCIF_A)
  91. # define SCIF_ORER 0x0200
  92. # else
  93. # define SCIF_ORER 0x0001
  94. # endif
  95. # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
  96. /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
  97. #else
  98. # error CPU subtype not defined
  99. #endif
  100. /* SCSCR */
  101. #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
  102. #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
  103. #define SCI_CTRL_FLAGS_TE 0x20 /* all */
  104. #define SCI_CTRL_FLAGS_RE 0x10 /* all */
  105. #if defined(CONFIG_CPU_SH7750) || \
  106. defined(CONFIG_CPU_SH7750R) || \
  107. defined(CONFIG_CPU_SH7722) || \
  108. defined(CONFIG_CPU_SH7734) || \
  109. defined(CONFIG_CPU_SH7750S) || \
  110. defined(CONFIG_CPU_SH7751) || \
  111. defined(CONFIG_CPU_SH7751R) || \
  112. defined(CONFIG_CPU_SH7763) || \
  113. defined(CONFIG_CPU_SH7780)
  114. #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
  115. #else
  116. #define SCI_CTRL_FLAGS_REIE 0
  117. #endif
  118. /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  119. /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  120. /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
  121. /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
  122. /* SCxSR SCI */
  123. #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  124. #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  125. #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  126. #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  127. #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  128. #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  129. /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  130. /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
  131. #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
  132. /* SCxSR SCIF */
  133. #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  134. #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  135. #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  136. #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  137. #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  138. #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  139. #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  140. #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
  141. #if defined(CONFIG_CPU_SH7721) || \
  142. defined(CONFIG_SH73A0) || \
  143. defined(CONFIG_R8A7740)
  144. # define SCIF_ORER 0x0200
  145. # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
  146. # define SCIF_RFDC_MASK 0x007f
  147. # define SCIF_TXROOM_MAX 64
  148. #elif defined(CONFIG_CPU_SH7763)
  149. # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
  150. # define SCIF_RFDC_MASK 0x007f
  151. # define SCIF_TXROOM_MAX 64
  152. /* SH7763 SCIF2 support */
  153. # define SCIF2_RFDC_MASK 0x001f
  154. # define SCIF2_TXROOM_MAX 16
  155. #elif defined(CONFIG_RCAR_GEN2)
  156. # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
  157. # if defined(CONFIG_SCIF_A)
  158. # define SCIF_RFDC_MASK 0x007f
  159. # else
  160. # define SCIF_RFDC_MASK 0x001f
  161. # endif
  162. #else
  163. # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
  164. # define SCIF_RFDC_MASK 0x001f
  165. # define SCIF_TXROOM_MAX 16
  166. #endif
  167. #ifndef SCIF_ORER
  168. #define SCIF_ORER 0x0000
  169. #endif
  170. #define SCxSR_TEND(port)\
  171. (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
  172. #define SCxSR_ERRORS(port)\
  173. (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
  174. #define SCxSR_RDxF(port)\
  175. (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
  176. #define SCxSR_TDxE(port)\
  177. (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
  178. #define SCxSR_FER(port)\
  179. (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
  180. #define SCxSR_PER(port)\
  181. (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
  182. #define SCxSR_BRK(port)\
  183. ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
  184. #define SCxSR_ORER(port)\
  185. (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
  186. #if defined(CONFIG_CPU_SH7721) || \
  187. defined(CONFIG_SH73A0) || \
  188. defined(CONFIG_R8A7740)
  189. # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
  190. # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
  191. # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
  192. # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
  193. #else
  194. # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
  195. # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
  196. # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
  197. # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
  198. #endif
  199. /* SCFCR */
  200. #define SCFCR_RFRST 0x0002
  201. #define SCFCR_TFRST 0x0004
  202. #define SCFCR_TCRST 0x4000
  203. #define SCFCR_MCE 0x0008
  204. #define SCI_MAJOR 204
  205. #define SCI_MINOR_START 8
  206. /* Generic serial flags */
  207. #define SCI_RX_THROTTLE 0x0000001
  208. #define SCI_MAGIC 0xbabeface
  209. /*
  210. * Events are used to schedule things to happen at timer-interrupt
  211. * time, instead of at rs interrupt time.
  212. */
  213. #define SCI_EVENT_WRITE_WAKEUP 0
  214. #define SCI_IN(size, offset)\
  215. if ((size) == 8) {\
  216. return readb(port->membase + (offset));\
  217. } else {\
  218. return readw(port->membase + (offset));\
  219. }
  220. #define SCI_OUT(size, offset, value)\
  221. if ((size) == 8) {\
  222. writeb(value, port->membase + (offset));\
  223. } else if ((size) == 16) {\
  224. writew(value, port->membase + (offset));\
  225. }
  226. #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
  227. static inline unsigned int sci_##name##_in(struct uart_port *port) {\
  228. if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
  229. SCI_IN(scif_size, scif_offset)\
  230. } else { /* PORT_SCI or PORT_SCIFA */\
  231. SCI_IN(sci_size, sci_offset);\
  232. }\
  233. }\
  234. static inline void sci_##name##_out(struct uart_port *port,\
  235. unsigned int value) {\
  236. if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
  237. SCI_OUT(scif_size, scif_offset, value)\
  238. } else { /* PORT_SCI or PORT_SCIFA */\
  239. SCI_OUT(sci_size, sci_offset, value);\
  240. }\
  241. }
  242. #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
  243. static inline unsigned int sci_##name##_in(struct uart_port *port) {\
  244. SCI_IN(scif_size, scif_offset);\
  245. }\
  246. static inline void sci_##name##_out(struct uart_port *port,\
  247. unsigned int value) {\
  248. SCI_OUT(scif_size, scif_offset, value);\
  249. }
  250. #define CPU_SCI_FNS(name, sci_offset, sci_size)\
  251. static inline unsigned int sci_##name##_in(struct uart_port *port) {\
  252. SCI_IN(sci_size, sci_offset);\
  253. }\
  254. static inline void sci_##name##_out(struct uart_port *port,\
  255. unsigned int value) {\
  256. SCI_OUT(sci_size, sci_offset, value);\
  257. }
  258. #if defined(CONFIG_SH73A0) || \
  259. defined(CONFIG_R8A7740)
  260. #if defined(CONFIG_CPU_SH7721) || \
  261. defined(CONFIG_SH73A0)
  262. #define SCIF_FNS(name, scif_offset, scif_size) \
  263. CPU_SCIF_FNS(name, scif_offset, scif_size)
  264. #elif defined(CONFIG_R8A7740)
  265. #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
  266. sh4_scifb_offset, sh4_scifb_size) \
  267. CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
  268. sh4_scifb_offset, sh4_scifb_size)
  269. #define SCIF_FNS(name, scif_offset, scif_size) \
  270. CPU_SCIF_FNS(name, scif_offset, scif_size)
  271. #else
  272. #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
  273. sh4_sci_offset, sh4_sci_size, \
  274. sh3_scif_offset, sh3_scif_size,\
  275. sh4_scif_offset, sh4_scif_size, \
  276. h8_sci_offset, h8_sci_size) \
  277. CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
  278. sh3_scif_offset, sh3_scif_size)
  279. #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
  280. sh4_scif_offset, sh4_scif_size) \
  281. CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
  282. #endif
  283. #elif defined(CONFIG_CPU_SH7723)
  284. #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
  285. sh4_scif_offset, sh4_scif_size) \
  286. CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
  287. sh4_scif_offset, sh4_scif_size)
  288. #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
  289. CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
  290. #else
  291. #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
  292. sh4_sci_offset, sh4_sci_size, \
  293. sh3_scif_offset, sh3_scif_size,\
  294. sh4_scif_offset, sh4_scif_size, \
  295. h8_sci_offset, h8_sci_size) \
  296. CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
  297. sh4_scif_offset, sh4_scif_size)
  298. #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
  299. sh4_scif_offset, sh4_scif_size) \
  300. CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
  301. #endif
  302. #if defined(CONFIG_CPU_SH7721) || \
  303. defined(CONFIG_SH73A0)
  304. SCIF_FNS(SCSMR, 0x00, 16)
  305. SCIF_FNS(SCBRR, 0x04, 8)
  306. SCIF_FNS(SCSCR, 0x08, 16)
  307. SCIF_FNS(SCTDSR, 0x0c, 8)
  308. SCIF_FNS(SCFER, 0x10, 16)
  309. SCIF_FNS(SCxSR, 0x14, 16)
  310. SCIF_FNS(SCFCR, 0x18, 16)
  311. SCIF_FNS(SCFDR, 0x1c, 16)
  312. SCIF_FNS(SCxTDR, 0x20, 8)
  313. SCIF_FNS(SCxRDR, 0x24, 8)
  314. SCIF_FNS(SCLSR, 0x00, 0)
  315. SCIF_FNS(DL, 0x00, 0) /* dummy */
  316. #elif defined(CONFIG_R8A7740)
  317. SCIF_FNS(SCSMR, 0x00, 16)
  318. SCIF_FNS(SCBRR, 0x04, 8)
  319. SCIF_FNS(SCSCR, 0x08, 16)
  320. SCIF_FNS(SCTDSR, 0x0c, 16)
  321. SCIF_FNS(SCFER, 0x10, 16)
  322. SCIF_FNS(SCxSR, 0x14, 16)
  323. SCIF_FNS(SCFCR, 0x18, 16)
  324. SCIF_FNS(SCFDR, 0x1c, 16)
  325. SCIF_FNS(SCTFDR, 0x38, 16)
  326. SCIF_FNS(SCRFDR, 0x3c, 16)
  327. SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
  328. SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
  329. SCIF_FNS(SCLSR, 0x00, 0)
  330. SCIF_FNS(DL, 0x00, 0) /* dummy */
  331. #elif defined(CONFIG_CPU_SH7723)
  332. SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
  333. SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
  334. SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
  335. SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
  336. SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
  337. SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
  338. SCIx_FNS(SCSPTR, 0, 0, 0, 0)
  339. SCIF_FNS(SCTDSR, 0x0c, 8)
  340. SCIF_FNS(SCFER, 0x10, 16)
  341. SCIF_FNS(SCFCR, 0x18, 16)
  342. SCIF_FNS(SCFDR, 0x1c, 16)
  343. SCIF_FNS(SCLSR, 0x24, 16)
  344. SCIF_FNS(DL, 0x00, 0) /* dummy */
  345. #elif defined(CONFIG_RCAR_GEN2)
  346. /* SCIFA and SCIF register offsets and size */
  347. SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
  348. SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
  349. SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
  350. SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
  351. SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
  352. SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
  353. SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
  354. SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
  355. SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
  356. SCIF_FNS(DL, 0, 0, 0x30, 16)
  357. SCIF_FNS(CKS, 0, 0, 0x34, 16)
  358. #if defined(CONFIG_SCIF_A)
  359. SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
  360. #else
  361. SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
  362. #endif
  363. #else
  364. /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
  365. /* name off sz off sz off sz off sz off sz*/
  366. SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
  367. SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
  368. SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
  369. SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
  370. SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
  371. SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
  372. SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
  373. #if defined(CONFIG_CPU_SH7780)
  374. SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
  375. SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
  376. SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
  377. SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
  378. SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
  379. #elif defined(CONFIG_CPU_SH7763)
  380. SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
  381. SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
  382. SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
  383. SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
  384. SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
  385. SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
  386. SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
  387. #else
  388. SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
  389. #if defined(CONFIG_CPU_SH7722)
  390. SCIF_FNS(SCSPTR, 0, 0, 0, 0)
  391. #else
  392. SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
  393. #endif
  394. SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
  395. #endif
  396. SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
  397. #endif
  398. #define sci_in(port, reg) sci_##reg##_in(port)
  399. #define sci_out(port, reg, value) sci_##reg##_out(port, value)
  400. #if defined(CONFIG_CPU_SH7750) || \
  401. defined(CONFIG_CPU_SH7751) || \
  402. defined(CONFIG_CPU_SH7751R) || \
  403. defined(CONFIG_CPU_SH7750R) || \
  404. defined(CONFIG_CPU_SH7750S)
  405. static inline int sci_rxd_in(struct uart_port *port)
  406. {
  407. if (port->mapbase == 0xffe00000)
  408. return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
  409. return 1;
  410. }
  411. #else /* default case for non-SCI processors */
  412. static inline int sci_rxd_in(struct uart_port *port)
  413. {
  414. return 1;
  415. }
  416. #endif
  417. /*
  418. * Values for the BitRate Register (SCBRR)
  419. *
  420. * The values are actually divisors for a frequency which can
  421. * be internal to the SH3 (14.7456MHz) or derived from an external
  422. * clock source. This driver assumes the internal clock is used;
  423. * to support using an external clock source, config options or
  424. * possibly command-line options would need to be added.
  425. *
  426. * Also, to support speeds below 2400 (why?) the lower 2 bits of
  427. * the SCSMR register would also need to be set to non-zero values.
  428. *
  429. * -- Greg Banks 27Feb2000
  430. *
  431. * Answer: The SCBRR register is only eight bits, and the value in
  432. * it gets larger with lower baud rates. At around 2400 (depending on
  433. * the peripherial module clock) you run out of bits. However the
  434. * lower two bits of SCSMR allow the module clock to be divided down,
  435. * scaling the value which is needed in SCBRR.
  436. *
  437. * -- Stuart Menefy - 23 May 2000
  438. *
  439. * I meant, why would anyone bother with bitrates below 2400.
  440. *
  441. * -- Greg Banks - 7Jul2000
  442. *
  443. * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
  444. * tape reader as a console!
  445. *
  446. * -- Mitch Davis - 15 Jul 2000
  447. */
  448. #if defined(CONFIG_CPU_SH7780)
  449. #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
  450. #elif defined(CONFIG_CPU_SH7721) || \
  451. defined(CONFIG_SH73A0) || \
  452. defined(CONFIG_R8A7740)
  453. #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
  454. #elif defined(CONFIG_CPU_SH7723)
  455. static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
  456. {
  457. if (port->type == PORT_SCIF)
  458. return (clk+16*bps)/(32*bps)-1;
  459. else
  460. return ((clk*2)+16*bps)/(16*bps)-1;
  461. }
  462. #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
  463. #elif defined(CONFIG_RCAR_GEN2)
  464. #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
  465. #if defined(CONFIG_SCIF_A)
  466. #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
  467. #else
  468. #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
  469. #endif
  470. #else /* Generic SH */
  471. #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
  472. #endif
  473. #ifndef DL_VALUE
  474. #define DL_VALUE(bps, clk) 0
  475. #endif