serial_octeon_pcie_console.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 Marvell International Ltd.
  4. * Copyright (C) 2021 Stefan Roese <sr@denx.de>
  5. */
  6. #include <dm.h>
  7. #include <dm/uclass.h>
  8. #include <errno.h>
  9. #include <input.h>
  10. #include <iomux.h>
  11. #include <log.h>
  12. #include <serial.h>
  13. #include <stdio_dev.h>
  14. #include <string.h>
  15. #include <watchdog.h>
  16. #include <linux/delay.h>
  17. #include <asm/io.h>
  18. #include <mach/cvmx-regs.h>
  19. #include <mach/cvmx-bootmem.h>
  20. #define DRIVER_NAME "pci-console"
  21. #define OCTEONTX_PCIE_CONSOLE_NAME_LEN 16
  22. /* Current versions */
  23. #define OCTEON_PCIE_CONSOLE_MAJOR_VERSION 1
  24. #define OCTEON_PCIE_CONSOLE_MINOR_VERSION 0
  25. #define OCTEON_PCIE_CONSOLE_BLOCK_NAME "__pci_console"
  26. /*
  27. * Structure that defines a single console.
  28. * Note: when read_index == write_index, the buffer is empty.
  29. * The actual usable size of each console is console_buf_size -1;
  30. */
  31. struct octeon_pcie_console {
  32. u64 input_base_addr;
  33. u32 input_read_index;
  34. u32 input_write_index;
  35. u64 output_base_addr;
  36. u32 output_read_index;
  37. u32 output_write_index;
  38. u32 lock;
  39. u32 buf_size;
  40. };
  41. /*
  42. * This is the main container structure that contains all the information
  43. * about all PCI consoles. The address of this structure is passed to various
  44. * routines that operation on PCI consoles.
  45. */
  46. struct octeon_pcie_console_desc {
  47. u32 major_version;
  48. u32 minor_version;
  49. u32 lock;
  50. u32 flags;
  51. u32 num_consoles;
  52. u32 pad;
  53. /* must be 64 bit aligned here... */
  54. /* Array of addresses of octeon_pcie_console_t structures */
  55. u64 console_addr_array[0];
  56. /* Implicit storage for console_addr_array */
  57. };
  58. struct octeon_pcie_console_priv {
  59. struct octeon_pcie_console *console;
  60. int console_num;
  61. bool console_active;
  62. };
  63. /* Flag definitions for read/write functions */
  64. enum {
  65. /*
  66. * If set, read/write functions won't block waiting for space or data.
  67. * For reads, 0 bytes may be read, and for writes not all of the
  68. * supplied data may be written.
  69. */
  70. OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,
  71. };
  72. static int buffer_free_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
  73. {
  74. if (rd_idx >= buffer_size || wr_idx >= buffer_size)
  75. return -1;
  76. return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
  77. }
  78. static int buffer_avail_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
  79. {
  80. if (rd_idx >= buffer_size || wr_idx >= buffer_size)
  81. return -1;
  82. return buffer_size - 1 - buffer_free_bytes(buffer_size, wr_idx, rd_idx);
  83. }
  84. static int buffer_read_avail(struct udevice *dev, unsigned int console_num)
  85. {
  86. struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
  87. struct octeon_pcie_console *cons_ptr = priv->console;
  88. int avail;
  89. avail = buffer_avail_bytes(cons_ptr->buf_size,
  90. cons_ptr->input_write_index,
  91. cons_ptr->input_read_index);
  92. if (avail >= 0)
  93. return avail;
  94. return 0;
  95. }
  96. static int octeon_pcie_console_read(struct udevice *dev,
  97. unsigned int console_num, char *buffer,
  98. int buffer_size, u32 flags)
  99. {
  100. struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
  101. struct octeon_pcie_console *cons_ptr = priv->console;
  102. int avail;
  103. char *buf_ptr;
  104. int bytes_read;
  105. int read_size;
  106. buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
  107. avail = buffer_avail_bytes(cons_ptr->buf_size,
  108. cons_ptr->input_write_index,
  109. cons_ptr->input_read_index);
  110. if (avail < 0)
  111. return avail;
  112. if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) {
  113. /* Wait for some data to be available */
  114. while (0 == (avail = buffer_avail_bytes(cons_ptr->buf_size,
  115. cons_ptr->input_write_index,
  116. cons_ptr->input_read_index))) {
  117. mdelay(10);
  118. WATCHDOG_RESET();
  119. }
  120. }
  121. bytes_read = 0;
  122. /* Don't overflow the buffer passed to us */
  123. read_size = min_t(int, avail, buffer_size);
  124. /* Limit ourselves to what we can input in a contiguous block */
  125. if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
  126. read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
  127. memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
  128. cons_ptr->input_read_index =
  129. (cons_ptr->input_read_index + read_size) % cons_ptr->buf_size;
  130. bytes_read += read_size;
  131. /* Mark the PCIe console to be active from now on */
  132. if (bytes_read)
  133. priv->console_active = true;
  134. return bytes_read;
  135. }
  136. static int octeon_pcie_console_write(struct udevice *dev,
  137. unsigned int console_num,
  138. const char *buffer,
  139. int bytes_to_write, u32 flags)
  140. {
  141. struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
  142. struct octeon_pcie_console *cons_ptr = priv->console;
  143. int avail;
  144. char *buf_ptr;
  145. int bytes_written;
  146. buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
  147. bytes_written = 0;
  148. while (bytes_to_write > 0) {
  149. avail = buffer_free_bytes(cons_ptr->buf_size,
  150. cons_ptr->output_write_index,
  151. cons_ptr->output_read_index);
  152. if (avail > 0) {
  153. int write_size = min_t(int, avail, bytes_to_write);
  154. /*
  155. * Limit ourselves to what we can output in a contiguous
  156. * block
  157. */
  158. if (cons_ptr->output_write_index + write_size >=
  159. cons_ptr->buf_size) {
  160. write_size = cons_ptr->buf_size -
  161. cons_ptr->output_write_index;
  162. }
  163. memcpy(buf_ptr + cons_ptr->output_write_index,
  164. buffer + bytes_written, write_size);
  165. /*
  166. * Make sure data is visible before changing write
  167. * index
  168. */
  169. CVMX_SYNCW;
  170. cons_ptr->output_write_index =
  171. (cons_ptr->output_write_index + write_size) %
  172. cons_ptr->buf_size;
  173. bytes_to_write -= write_size;
  174. bytes_written += write_size;
  175. } else if (avail == 0) {
  176. /*
  177. * Check to see if we should wait for room, or return
  178. * after a partial write
  179. */
  180. if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
  181. goto done;
  182. WATCHDOG_RESET();
  183. mdelay(10); /* Delay if we are spinning */
  184. } else {
  185. bytes_written = -1;
  186. goto done;
  187. }
  188. }
  189. done:
  190. return bytes_written;
  191. }
  192. static struct octeon_pcie_console_desc *octeon_pcie_console_init(int num_consoles,
  193. int buffer_size)
  194. {
  195. struct octeon_pcie_console_desc *cons_desc_ptr;
  196. struct octeon_pcie_console *cons_ptr;
  197. s64 addr;
  198. u64 avail_addr;
  199. int alloc_size;
  200. int i;
  201. /* Compute size required for pci console structure */
  202. alloc_size = num_consoles *
  203. (buffer_size * 2 + sizeof(struct octeon_pcie_console) +
  204. sizeof(u64)) + sizeof(struct octeon_pcie_console_desc);
  205. /*
  206. * Allocate memory for the consoles. This must be in the range
  207. * addresssible by the bootloader.
  208. * Try to do so in a manner which minimizes fragmentation. We try to
  209. * put it at the top of DDR0 or bottom of DDR2 first, and only do
  210. * generic allocation if those fail
  211. */
  212. addr = cvmx_bootmem_phy_named_block_alloc(alloc_size,
  213. OCTEON_DDR0_SIZE - alloc_size - 128,
  214. OCTEON_DDR0_SIZE, 128,
  215. OCTEON_PCIE_CONSOLE_BLOCK_NAME,
  216. CVMX_BOOTMEM_FLAG_END_ALLOC);
  217. if (addr < 0) {
  218. addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0,
  219. 0x1fffffff, 128,
  220. OCTEON_PCIE_CONSOLE_BLOCK_NAME,
  221. CVMX_BOOTMEM_FLAG_END_ALLOC);
  222. }
  223. if (addr < 0)
  224. return 0;
  225. cons_desc_ptr = cvmx_phys_to_ptr(addr);
  226. /* Clear entire alloc'ed memory */
  227. memset(cons_desc_ptr, 0, alloc_size);
  228. /* Initialize as locked until we are done */
  229. cons_desc_ptr->lock = 1;
  230. CVMX_SYNCW;
  231. cons_desc_ptr->num_consoles = num_consoles;
  232. cons_desc_ptr->flags = 0;
  233. cons_desc_ptr->major_version = OCTEON_PCIE_CONSOLE_MAJOR_VERSION;
  234. cons_desc_ptr->minor_version = OCTEON_PCIE_CONSOLE_MINOR_VERSION;
  235. avail_addr = addr + sizeof(struct octeon_pcie_console_desc) +
  236. num_consoles * sizeof(u64);
  237. for (i = 0; i < num_consoles; i++) {
  238. cons_desc_ptr->console_addr_array[i] = avail_addr;
  239. cons_ptr = (void *)cons_desc_ptr->console_addr_array[i];
  240. avail_addr += sizeof(struct octeon_pcie_console);
  241. cons_ptr->input_base_addr = avail_addr;
  242. avail_addr += buffer_size;
  243. cons_ptr->output_base_addr = avail_addr;
  244. avail_addr += buffer_size;
  245. cons_ptr->buf_size = buffer_size;
  246. }
  247. CVMX_SYNCW;
  248. cons_desc_ptr->lock = 0;
  249. return cvmx_phys_to_ptr(addr);
  250. }
  251. static int octeon_pcie_console_getc(struct udevice *dev)
  252. {
  253. char c;
  254. octeon_pcie_console_read(dev, 0, &c, 1, 0);
  255. return c;
  256. }
  257. static int octeon_pcie_console_putc(struct udevice *dev, const char c)
  258. {
  259. struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
  260. if (priv->console_active)
  261. octeon_pcie_console_write(dev, 0, (char *)&c, 1, 0);
  262. return 0;
  263. }
  264. static int octeon_pcie_console_pending(struct udevice *dev, bool input)
  265. {
  266. if (input) {
  267. udelay(100);
  268. return buffer_read_avail(dev, 0) > 0;
  269. }
  270. return 0;
  271. }
  272. static const struct dm_serial_ops octeon_pcie_console_ops = {
  273. .getc = octeon_pcie_console_getc,
  274. .putc = octeon_pcie_console_putc,
  275. .pending = octeon_pcie_console_pending,
  276. };
  277. static int octeon_pcie_console_probe(struct udevice *dev)
  278. {
  279. struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
  280. struct octeon_pcie_console_desc *cons_desc;
  281. int console_count;
  282. int console_size;
  283. int console_num;
  284. /*
  285. * Currently only 1 console is supported. Perhaps we need to add
  286. * a console nexus if more than one needs to be supported.
  287. */
  288. console_count = 1;
  289. console_size = 1024;
  290. console_num = 0;
  291. cons_desc = octeon_pcie_console_init(console_count, console_size);
  292. priv->console =
  293. cvmx_phys_to_ptr(cons_desc->console_addr_array[console_num]);
  294. debug("PCI console init succeeded, %d consoles, %d bytes each\n",
  295. console_count, console_size);
  296. return 0;
  297. }
  298. static const struct udevice_id octeon_pcie_console_serial_id[] = {
  299. { .compatible = "marvell,pci-console", },
  300. { },
  301. };
  302. U_BOOT_DRIVER(octeon_pcie_console) = {
  303. .name = DRIVER_NAME,
  304. .id = UCLASS_SERIAL,
  305. .ops = &octeon_pcie_console_ops,
  306. .of_match = of_match_ptr(octeon_pcie_console_serial_id),
  307. .probe = octeon_pcie_console_probe,
  308. .priv_auto = sizeof(struct octeon_pcie_console_priv),
  309. };