serial_mt7620.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * UART driver for MediaTek MT7620 and earlier SoCs
  4. *
  5. * Copyright (C) 2020 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <reset.h>
  14. #include <serial.h>
  15. #include <watchdog.h>
  16. #include <asm/io.h>
  17. #include <asm/types.h>
  18. #include <asm/addrspace.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/err.h>
  21. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  22. #include <dt-structs.h>
  23. #endif
  24. struct mt7620_serial_regs {
  25. u32 rbr;
  26. u32 thr;
  27. u32 ier;
  28. u32 iir;
  29. u32 fcr;
  30. u32 lcr;
  31. u32 mcr;
  32. u32 lsr;
  33. u32 msr;
  34. u32 scratch;
  35. u32 dl;
  36. u32 dll;
  37. u32 dlm;
  38. u32 ifctl;
  39. };
  40. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  41. #define UART_LSR_DR 0x01 /* Data ready */
  42. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  43. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  44. #define UART_MCR_DTR 0x01 /* DTR */
  45. #define UART_MCR_RTS 0x02 /* RTS */
  46. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  47. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  48. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  49. #define UART_MCRVAL (UART_MCR_DTR | \
  50. UART_MCR_RTS)
  51. /* Clear & enable FIFOs */
  52. #define UART_FCRVAL (UART_FCR_FIFO_EN | \
  53. UART_FCR_RXSR | \
  54. UART_FCR_TXSR)
  55. struct mt7620_serial_plat {
  56. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  57. struct dtd_serial_mt7620 dtplat;
  58. #endif
  59. struct mt7620_serial_regs __iomem *regs;
  60. u32 clock;
  61. };
  62. static void _mt7620_serial_setbrg(struct mt7620_serial_plat *plat, int baud)
  63. {
  64. u32 quot;
  65. /* set divisor */
  66. quot = DIV_ROUND_CLOSEST(plat->clock, 16 * baud);
  67. writel(quot, &plat->regs->dl);
  68. /* set character length and stop bits */
  69. writel(UART_LCR_WLS_8, &plat->regs->lcr);
  70. }
  71. static int mt7620_serial_setbrg(struct udevice *dev, int baudrate)
  72. {
  73. struct mt7620_serial_plat *plat = dev_get_plat(dev);
  74. _mt7620_serial_setbrg(plat, baudrate);
  75. return 0;
  76. }
  77. static int mt7620_serial_putc(struct udevice *dev, const char ch)
  78. {
  79. struct mt7620_serial_plat *plat = dev_get_plat(dev);
  80. if (!(readl(&plat->regs->lsr) & UART_LSR_THRE))
  81. return -EAGAIN;
  82. writel(ch, &plat->regs->thr);
  83. if (ch == '\n')
  84. WATCHDOG_RESET();
  85. return 0;
  86. }
  87. static int mt7620_serial_getc(struct udevice *dev)
  88. {
  89. struct mt7620_serial_plat *plat = dev_get_plat(dev);
  90. if (!(readl(&plat->regs->lsr) & UART_LSR_DR))
  91. return -EAGAIN;
  92. return readl(&plat->regs->rbr);
  93. }
  94. static int mt7620_serial_pending(struct udevice *dev, bool input)
  95. {
  96. struct mt7620_serial_plat *plat = dev_get_plat(dev);
  97. if (input)
  98. return (readl(&plat->regs->lsr) & UART_LSR_DR) ? 1 : 0;
  99. return (readl(&plat->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
  100. }
  101. static int mt7620_serial_probe(struct udevice *dev)
  102. {
  103. struct mt7620_serial_plat *plat = dev_get_plat(dev);
  104. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  105. plat->regs = (void __iomem *)KSEG1ADDR(plat->dtplat.reg[0]);
  106. plat->clock = plat->dtplat.clock_frequency;
  107. #endif
  108. /* Disable interrupt */
  109. writel(0, &plat->regs->ier);
  110. writel(UART_MCRVAL, &plat->regs->mcr);
  111. writel(UART_FCRVAL, &plat->regs->fcr);
  112. return 0;
  113. }
  114. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  115. static int mt7620_serial_of_to_plat(struct udevice *dev)
  116. {
  117. struct mt7620_serial_plat *plat = dev_get_plat(dev);
  118. struct reset_ctl reset_uart;
  119. struct clk clk;
  120. int err;
  121. err = reset_get_by_index(dev, 0, &reset_uart);
  122. if (!err)
  123. reset_deassert(&reset_uart);
  124. plat->regs = dev_remap_addr_index(dev, 0);
  125. if (!plat->regs) {
  126. dev_err(dev, "mt7620_serial: unable to map UART registers\n");
  127. return -EINVAL;
  128. }
  129. err = clk_get_by_index(dev, 0, &clk);
  130. if (!err) {
  131. err = clk_get_rate(&clk);
  132. if (!IS_ERR_VALUE(err))
  133. plat->clock = err;
  134. } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
  135. dev_err(dev, "mt7620_serial: failed to get clock\n");
  136. return err;
  137. }
  138. if (!plat->clock)
  139. plat->clock = dev_read_u32_default(dev, "clock-frequency", 0);
  140. if (!plat->clock) {
  141. dev_err(dev, "mt7620_serial: clock not defined\n");
  142. return -EINVAL;
  143. }
  144. return 0;
  145. }
  146. static const struct udevice_id mt7620_serial_ids[] = {
  147. { .compatible = "mediatek,mt7620-uart" },
  148. { }
  149. };
  150. #endif
  151. static const struct dm_serial_ops mt7620_serial_ops = {
  152. .putc = mt7620_serial_putc,
  153. .pending = mt7620_serial_pending,
  154. .getc = mt7620_serial_getc,
  155. .setbrg = mt7620_serial_setbrg,
  156. };
  157. U_BOOT_DRIVER(serial_mt7620) = {
  158. .name = "serial_mt7620",
  159. .id = UCLASS_SERIAL,
  160. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  161. .of_match = mt7620_serial_ids,
  162. .of_to_plat = mt7620_serial_of_to_plat,
  163. #endif
  164. .plat_auto = sizeof(struct mt7620_serial_plat),
  165. .probe = mt7620_serial_probe,
  166. .ops = &mt7620_serial_ops,
  167. .flags = DM_FLAG_PRE_RELOC,
  168. };
  169. DM_DRIVER_ALIAS(serial_mt7620, mediatek_mt7620_uart);
  170. #ifdef CONFIG_DEBUG_UART_MT7620
  171. #include <debug_uart.h>
  172. static inline void _debug_uart_init(void)
  173. {
  174. struct mt7620_serial_plat plat;
  175. plat.regs = (void *)CONFIG_DEBUG_UART_BASE;
  176. plat.clock = CONFIG_DEBUG_UART_CLOCK;
  177. writel(0, &plat.regs->ier);
  178. writel(UART_MCRVAL, &plat.regs->mcr);
  179. writel(UART_FCRVAL, &plat.regs->fcr);
  180. _mt7620_serial_setbrg(&plat, CONFIG_BAUDRATE);
  181. }
  182. static inline void _debug_uart_putc(int ch)
  183. {
  184. struct mt7620_serial_regs __iomem *regs =
  185. (void *)CONFIG_DEBUG_UART_BASE;
  186. while (!(readl(&regs->lsr) & UART_LSR_THRE))
  187. ;
  188. writel(ch, &regs->thr);
  189. }
  190. DEBUG_UART_FUNCS
  191. #endif