serial_mcf.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  4. * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
  5. *
  6. * Modified to add device model (DM) support
  7. * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
  8. *
  9. * Modified to add DM and fdt support, removed non DM code
  10. * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
  11. */
  12. /*
  13. * Minimal serial functions needed to use one of the uart ports
  14. * as serial console interface.
  15. */
  16. #include <common.h>
  17. #include <dm.h>
  18. #include <asm/global_data.h>
  19. #include <dm/platform_data/serial_coldfire.h>
  20. #include <serial.h>
  21. #include <linux/compiler.h>
  22. #include <asm/immap.h>
  23. #include <asm/uart.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. extern void uart_port_conf(int port);
  26. static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
  27. {
  28. u32 counter;
  29. uart_port_conf(port_idx);
  30. /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
  31. writeb(UART_UCR_RESET_RX, &uart->ucr);
  32. writeb(UART_UCR_RESET_TX, &uart->ucr);
  33. writeb(UART_UCR_RESET_ERROR, &uart->ucr);
  34. writeb(UART_UCR_RESET_MR, &uart->ucr);
  35. __asm__("nop");
  36. writeb(0, &uart->uimr);
  37. /* write to CSR: RX/TX baud rate from timers */
  38. writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
  39. writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
  40. writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
  41. /* Setting up BaudRate */
  42. counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
  43. counter = counter / baudrate;
  44. /* write to CTUR: divide counter upper byte */
  45. writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
  46. /* write to CTLR: divide counter lower byte */
  47. writeb((u8)(counter & 0x00ff), &uart->ubg2);
  48. writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  49. return (0);
  50. }
  51. static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
  52. {
  53. u32 counter;
  54. /* Setting up BaudRate */
  55. counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
  56. counter = counter / baudrate;
  57. /* write to CTUR: divide counter upper byte */
  58. writeb(((counter & 0xff00) >> 8), &uart->ubg1);
  59. /* write to CTLR: divide counter lower byte */
  60. writeb((counter & 0x00ff), &uart->ubg2);
  61. writeb(UART_UCR_RESET_RX, &uart->ucr);
  62. writeb(UART_UCR_RESET_TX, &uart->ucr);
  63. writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  64. }
  65. static int coldfire_serial_probe(struct udevice *dev)
  66. {
  67. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  68. plat->port = dev_seq(dev);
  69. return mcf_serial_init_common((uart_t *)plat->base,
  70. plat->port, plat->baudrate);
  71. }
  72. static int coldfire_serial_putc(struct udevice *dev, const char ch)
  73. {
  74. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  75. uart_t *uart = (uart_t *)plat->base;
  76. /* Wait for last character to go. */
  77. if (!(readb(&uart->usr) & UART_USR_TXRDY))
  78. return -EAGAIN;
  79. writeb(ch, &uart->utb);
  80. return 0;
  81. }
  82. static int coldfire_serial_getc(struct udevice *dev)
  83. {
  84. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  85. uart_t *uart = (uart_t *)(plat->base);
  86. /* Wait for a character to arrive. */
  87. if (!(readb(&uart->usr) & UART_USR_RXRDY))
  88. return -EAGAIN;
  89. return readb(&uart->urb);
  90. }
  91. int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
  92. {
  93. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  94. uart_t *uart = (uart_t *)(plat->base);
  95. mcf_serial_setbrg_common(uart, baudrate);
  96. return 0;
  97. }
  98. static int coldfire_serial_pending(struct udevice *dev, bool input)
  99. {
  100. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  101. uart_t *uart = (uart_t *)(plat->base);
  102. if (input)
  103. return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
  104. else
  105. return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
  106. return 0;
  107. }
  108. static int coldfire_of_to_plat(struct udevice *dev)
  109. {
  110. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  111. fdt_addr_t addr_base;
  112. addr_base = dev_read_addr(dev);
  113. if (addr_base == FDT_ADDR_T_NONE)
  114. return -ENODEV;
  115. plat->base = (uint32_t)addr_base;
  116. plat->baudrate = gd->baudrate;
  117. return 0;
  118. }
  119. static const struct dm_serial_ops coldfire_serial_ops = {
  120. .putc = coldfire_serial_putc,
  121. .pending = coldfire_serial_pending,
  122. .getc = coldfire_serial_getc,
  123. .setbrg = coldfire_serial_setbrg,
  124. };
  125. static const struct udevice_id coldfire_serial_ids[] = {
  126. { .compatible = "fsl,mcf-uart" },
  127. { }
  128. };
  129. U_BOOT_DRIVER(serial_coldfire) = {
  130. .name = "serial_coldfire",
  131. .id = UCLASS_SERIAL,
  132. .of_match = coldfire_serial_ids,
  133. .of_to_plat = coldfire_of_to_plat,
  134. .plat_auto = sizeof(struct coldfire_serial_plat),
  135. .probe = coldfire_serial_probe,
  136. .ops = &coldfire_serial_ops,
  137. .flags = DM_FLAG_PRE_RELOC,
  138. };