rx8025.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  5. */
  6. /*
  7. * Epson RX8025 RTC driver.
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <dm.h>
  12. #include <i2c.h>
  13. #include <rtc.h>
  14. /*---------------------------------------------------------------------*/
  15. #undef DEBUG_RTC
  16. #ifdef DEBUG_RTC
  17. #define DEBUGR(fmt,args...) printf(fmt ,##args)
  18. #else
  19. #define DEBUGR(fmt,args...)
  20. #endif
  21. /*---------------------------------------------------------------------*/
  22. #ifndef CONFIG_SYS_I2C_RTC_ADDR
  23. # define CONFIG_SYS_I2C_RTC_ADDR 0x32
  24. #endif
  25. #ifdef CONFIG_DM_RTC
  26. #define DEV_TYPE struct udevice
  27. #else
  28. /* Local udevice */
  29. struct ludevice {
  30. u8 chip;
  31. };
  32. #define DEV_TYPE struct ludevice
  33. #endif
  34. /*
  35. * RTC register addresses
  36. */
  37. #define RTC_SEC_REG_ADDR 0x00
  38. #define RTC_MIN_REG_ADDR 0x01
  39. #define RTC_HR_REG_ADDR 0x02
  40. #define RTC_DAY_REG_ADDR 0x03
  41. #define RTC_DATE_REG_ADDR 0x04
  42. #define RTC_MON_REG_ADDR 0x05
  43. #define RTC_YR_REG_ADDR 0x06
  44. #define RTC_CTL1_REG_ADDR 0x0e
  45. #define RTC_CTL2_REG_ADDR 0x0f
  46. /*
  47. * Control register 1 bits
  48. */
  49. #define RTC_CTL1_BIT_2412 0x20
  50. /*
  51. * Control register 2 bits
  52. */
  53. #define RTC_CTL2_BIT_PON 0x10
  54. #define RTC_CTL2_BIT_VDET 0x40
  55. #define RTC_CTL2_BIT_XST 0x20
  56. #define RTC_CTL2_BIT_VDSL 0x80
  57. /*
  58. * Note: the RX8025 I2C RTC requires register
  59. * reads and write to consist of a single bus
  60. * cycle. It is not allowed to write the register
  61. * address in a first cycle that is terminated by
  62. * a STOP condition. The chips needs a 'restart'
  63. * sequence (start sequence without a prior stop).
  64. * This driver has been written for a 4xx board.
  65. * U-Boot's 4xx i2c driver is currently not capable
  66. * to generate such cycles to some work arounds
  67. * are used.
  68. */
  69. /* static uchar rtc_read (uchar reg); */
  70. #ifdef CONFIG_DM_RTC
  71. /*
  72. * on mpc85xx based board with DM and offset len 1
  73. * accessing rtc works fine. May we can drop this ?
  74. */
  75. #define rtc_read(reg) buf[(reg) & 0xf]
  76. #else
  77. #define rtc_read(reg) buf[((reg) + 1) & 0xf]
  78. #endif
  79. static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val);
  80. /*
  81. * Get the current time from the RTC
  82. */
  83. static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
  84. {
  85. int rel = 0;
  86. uchar sec, min, hour, mday, wday, mon, year, ctl2;
  87. uchar buf[16];
  88. #ifdef CONFIG_DM_RTC
  89. if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
  90. #else
  91. if (i2c_read(dev->chip, 0, 0, buf, 16)) {
  92. #endif
  93. printf("Error reading from RTC\n");
  94. return -EIO;
  95. }
  96. sec = rtc_read(RTC_SEC_REG_ADDR);
  97. min = rtc_read(RTC_MIN_REG_ADDR);
  98. hour = rtc_read(RTC_HR_REG_ADDR);
  99. wday = rtc_read(RTC_DAY_REG_ADDR);
  100. mday = rtc_read(RTC_DATE_REG_ADDR);
  101. mon = rtc_read(RTC_MON_REG_ADDR);
  102. year = rtc_read(RTC_YR_REG_ADDR);
  103. DEBUGR("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
  104. "hr: %02x min: %02x sec: %02x\n",
  105. year, mon, mday, wday, hour, min, sec);
  106. /* dump status */
  107. ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
  108. if (ctl2 & RTC_CTL2_BIT_PON) {
  109. printf("RTC: power-on detected\n");
  110. rel = -1;
  111. }
  112. if (ctl2 & RTC_CTL2_BIT_VDET) {
  113. printf("RTC: voltage drop detected\n");
  114. rel = -1;
  115. }
  116. if (!(ctl2 & RTC_CTL2_BIT_XST)) {
  117. printf("RTC: oscillator stop detected\n");
  118. rel = -1;
  119. }
  120. tmp->tm_sec = bcd2bin(sec & 0x7F);
  121. tmp->tm_min = bcd2bin(min & 0x7F);
  122. if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
  123. tmp->tm_hour = bcd2bin(hour & 0x3F);
  124. else
  125. tmp->tm_hour = bcd2bin(hour & 0x1F) % 12 +
  126. ((hour & 0x20) ? 12 : 0);
  127. tmp->tm_mday = bcd2bin (mday & 0x3F);
  128. tmp->tm_mon = bcd2bin (mon & 0x1F);
  129. tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
  130. tmp->tm_wday = bcd2bin (wday & 0x07);
  131. tmp->tm_yday = 0;
  132. tmp->tm_isdst= 0;
  133. DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  134. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  135. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  136. return rel;
  137. }
  138. /*
  139. * Set the RTC
  140. */
  141. static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp)
  142. {
  143. DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  144. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  145. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  146. if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
  147. printf("WARNING: year should be between 1970 and 2069!\n");
  148. if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)))
  149. return -EIO;
  150. if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)))
  151. return -EIO;
  152. if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday)))
  153. return -EIO;
  154. if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)))
  155. return -EIO;
  156. if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)))
  157. return -EIO;
  158. if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)))
  159. return -EIO;
  160. if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)))
  161. return -EIO;
  162. return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
  163. }
  164. /*
  165. * Reset the RTC
  166. */
  167. static int rx8025_rtc_reset(DEV_TYPE *dev)
  168. {
  169. uchar buf[16];
  170. uchar ctl2;
  171. #ifdef CONFIG_DM_RTC
  172. if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
  173. #else
  174. if (i2c_read(dev->chip, 0, 0, buf, 16)) {
  175. #endif
  176. printf("Error reading from RTC\n");
  177. return -EIO;
  178. }
  179. ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
  180. ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
  181. ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
  182. return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2);
  183. }
  184. /*
  185. * Helper functions
  186. */
  187. static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val)
  188. {
  189. uchar buf[2];
  190. buf[0] = reg << 4;
  191. buf[1] = val;
  192. #ifdef CONFIG_DM_RTC
  193. if (dm_i2c_write(dev, 0, buf, 2)) {
  194. #else
  195. if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) {
  196. #endif
  197. printf("Error writing to RTC\n");
  198. return -EIO;
  199. }
  200. return 0;
  201. }
  202. #ifdef CONFIG_DM_RTC
  203. static int rx8025_probe(struct udevice *dev)
  204. {
  205. uchar buf[16];
  206. int ret = 0;
  207. if (i2c_get_chip_offset_len(dev) != 1)
  208. ret = i2c_set_chip_offset_len(dev, 1);
  209. if (ret)
  210. return ret;
  211. return dm_i2c_read(dev, 0, buf, sizeof(buf));
  212. }
  213. static const struct rtc_ops rx8025_rtc_ops = {
  214. .get = rx8025_rtc_get,
  215. .set = rx8025_rtc_set,
  216. .reset = rx8025_rtc_reset,
  217. };
  218. static const struct udevice_id rx8025_rtc_ids[] = {
  219. { .compatible = "epson,rx8025" },
  220. { }
  221. };
  222. U_BOOT_DRIVER(rx8010sj_rtc) = {
  223. .name = "rx8025_rtc",
  224. .id = UCLASS_RTC,
  225. .probe = rx8025_probe,
  226. .of_match = rx8025_rtc_ids,
  227. .ops = &rx8025_rtc_ops,
  228. };
  229. #else
  230. int rtc_get(struct rtc_time *tm)
  231. {
  232. struct ludevice dev = {
  233. .chip = CONFIG_SYS_I2C_RTC_ADDR,
  234. };
  235. return rx8025_rtc_get(&dev, tm);
  236. }
  237. int rtc_set(struct rtc_time *tm)
  238. {
  239. struct ludevice dev = {
  240. .chip = CONFIG_SYS_I2C_RTC_ADDR,
  241. };
  242. return rx8025_rtc_set(&dev, tm);
  243. }
  244. void rtc_reset(void)
  245. {
  246. struct ludevice dev = {
  247. .chip = CONFIG_SYS_I2C_RTC_ADDR,
  248. };
  249. rx8025_rtc_reset(&dev);
  250. }
  251. #endif