pt7c4338.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. *
  6. * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  7. */
  8. /*
  9. * This file provides Date & Time support (no alarms) for PT7C4338 chip.
  10. *
  11. * This file is based on drivers/rtc/ds1337.c
  12. *
  13. * PT7C4338 chip is manufactured by Pericom Technology Inc.
  14. * It is a serial real-time clock which provides
  15. * 1)Low-power clock/calendar.
  16. * 2)Programmable square-wave output.
  17. * It has 56 bytes of nonvolatile RAM.
  18. */
  19. #include <common.h>
  20. #include <command.h>
  21. #include <dm.h>
  22. #include <log.h>
  23. #include <rtc.h>
  24. #include <i2c.h>
  25. /* RTC register addresses */
  26. #define RTC_SEC_REG_ADDR 0x0
  27. #define RTC_MIN_REG_ADDR 0x1
  28. #define RTC_HR_REG_ADDR 0x2
  29. #define RTC_DAY_REG_ADDR 0x3
  30. #define RTC_DATE_REG_ADDR 0x4
  31. #define RTC_MON_REG_ADDR 0x5
  32. #define RTC_YR_REG_ADDR 0x6
  33. #define RTC_CTL_STAT_REG_ADDR 0x7
  34. /* RTC second register address bit */
  35. #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
  36. /* RTC control and status register bits */
  37. #define RTC_CTL_STAT_BIT_RS0 0x1 /* Rate select 0 */
  38. #define RTC_CTL_STAT_BIT_RS1 0x2 /* Rate select 1 */
  39. #define RTC_CTL_STAT_BIT_SQWE 0x10 /* Square Wave Enable */
  40. #define RTC_CTL_STAT_BIT_OSF 0x20 /* Oscillator Stop Flag */
  41. #define RTC_CTL_STAT_BIT_OUT 0x80 /* Output Level Control */
  42. /* RTC reset value */
  43. #define RTC_PT7C4338_RESET_VAL \
  44. (RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT)
  45. #if !CONFIG_IS_ENABLED(DM_RTC)
  46. /****** Helper functions ****************************************/
  47. static u8 rtc_read(u8 reg)
  48. {
  49. return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
  50. }
  51. static void rtc_write(u8 reg, u8 val)
  52. {
  53. i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
  54. }
  55. /****************************************************************/
  56. /* Get the current time from the RTC */
  57. int rtc_get(struct rtc_time *tmp)
  58. {
  59. int ret = 0;
  60. u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
  61. ctl_stat = rtc_read(RTC_CTL_STAT_REG_ADDR);
  62. sec = rtc_read(RTC_SEC_REG_ADDR);
  63. min = rtc_read(RTC_MIN_REG_ADDR);
  64. hour = rtc_read(RTC_HR_REG_ADDR);
  65. wday = rtc_read(RTC_DAY_REG_ADDR);
  66. mday = rtc_read(RTC_DATE_REG_ADDR);
  67. mon = rtc_read(RTC_MON_REG_ADDR);
  68. year = rtc_read(RTC_YR_REG_ADDR);
  69. debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
  70. "hr: %02x min: %02x sec: %02x control_status: %02x\n",
  71. year, mon, mday, wday, hour, min, sec, ctl_stat);
  72. if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
  73. printf("### Warning: RTC oscillator has stopped\n");
  74. /* clear the OSF flag */
  75. rtc_write(RTC_CTL_STAT_REG_ADDR,
  76. rtc_read(RTC_CTL_STAT_REG_ADDR)\
  77. & ~RTC_CTL_STAT_BIT_OSF);
  78. ret = -1;
  79. }
  80. tmp->tm_sec = bcd2bin(sec & 0x7F);
  81. tmp->tm_min = bcd2bin(min & 0x7F);
  82. tmp->tm_hour = bcd2bin(hour & 0x3F);
  83. tmp->tm_mday = bcd2bin(mday & 0x3F);
  84. tmp->tm_mon = bcd2bin(mon & 0x1F);
  85. tmp->tm_year = bcd2bin(year) + 2000;
  86. tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
  87. tmp->tm_yday = 0;
  88. tmp->tm_isdst = 0;
  89. debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  90. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  91. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  92. return ret;
  93. }
  94. /* Set the RTC */
  95. int rtc_set(struct rtc_time *tmp)
  96. {
  97. debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  98. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  99. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  100. rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
  101. rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
  102. rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
  103. rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
  104. rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
  105. rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
  106. rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
  107. return 0;
  108. }
  109. /* Reset the RTC */
  110. void rtc_reset(void)
  111. {
  112. rtc_write(RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
  113. rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
  114. }
  115. #else
  116. static u8 rtc_read(struct udevice *dev, u8 reg)
  117. {
  118. return dm_i2c_reg_read(dev, reg);
  119. }
  120. static void rtc_write(struct udevice *dev, u8 reg, u8 val)
  121. {
  122. dm_i2c_reg_write(dev, reg, val);
  123. }
  124. static int pt7c4338_rtc_get(struct udevice *dev, struct rtc_time *tmp)
  125. {
  126. int ret = 0;
  127. u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
  128. ctl_stat = rtc_read(dev, RTC_CTL_STAT_REG_ADDR);
  129. sec = rtc_read(dev, RTC_SEC_REG_ADDR);
  130. min = rtc_read(dev, RTC_MIN_REG_ADDR);
  131. hour = rtc_read(dev, RTC_HR_REG_ADDR);
  132. wday = rtc_read(dev, RTC_DAY_REG_ADDR);
  133. mday = rtc_read(dev, RTC_DATE_REG_ADDR);
  134. mon = rtc_read(dev, RTC_MON_REG_ADDR);
  135. year = rtc_read(dev, RTC_YR_REG_ADDR);
  136. debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x\n",
  137. year, mon, mday, wday);
  138. debug("hr: %02x min: %02x sec: %02x control_status: %02x\n",
  139. hour, min, sec, ctl_stat);
  140. if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
  141. printf("### Warning: RTC oscillator has stopped\n");
  142. /* clear the OSF flag */
  143. rtc_write(dev, RTC_CTL_STAT_REG_ADDR,
  144. rtc_read(dev,
  145. RTC_CTL_STAT_REG_ADDR)
  146. & ~RTC_CTL_STAT_BIT_OSF);
  147. ret = -1;
  148. }
  149. tmp->tm_sec = bcd2bin(sec & 0x7F);
  150. tmp->tm_min = bcd2bin(min & 0x7F);
  151. tmp->tm_hour = bcd2bin(hour & 0x3F);
  152. tmp->tm_mday = bcd2bin(mday & 0x3F);
  153. tmp->tm_mon = bcd2bin(mon & 0x1F);
  154. tmp->tm_year = bcd2bin(year) + 2000;
  155. tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
  156. tmp->tm_yday = 0;
  157. tmp->tm_isdst = 0;
  158. debug("Get DATE: %4d-%02d-%02d [wday=%d] TIME: %2d:%02d:%02d\n",
  159. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  160. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  161. return ret;
  162. }
  163. static int pt7c4338_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
  164. {
  165. debug("Set DATE: %4d-%02d-%02d [wday=%d] TIME: %2d:%02d:%02d\n",
  166. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  167. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  168. rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
  169. rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
  170. rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
  171. rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
  172. rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
  173. rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
  174. rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
  175. return 0;
  176. }
  177. static int pt7c4338_rtc_reset(struct udevice *dev)
  178. {
  179. rtc_write(dev, RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
  180. rtc_write(dev, RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
  181. return 0;
  182. }
  183. static const struct rtc_ops pt7c4338_rtc_ops = {
  184. .get = pt7c4338_rtc_get,
  185. .set = pt7c4338_rtc_set,
  186. .reset = pt7c4338_rtc_reset,
  187. };
  188. static const struct udevice_id pt7c4338_rtc_ids[] = {
  189. { .compatible = "pericom,pt7c4338" },
  190. { }
  191. };
  192. U_BOOT_DRIVER(rtc_pt7c4338) = {
  193. .name = "rtc-pt7c4338",
  194. .id = UCLASS_RTC,
  195. .of_match = pt7c4338_rtc_ids,
  196. .ops = &pt7c4338_rtc_ops,
  197. };
  198. #endif