davinci.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 DENX Software Engineering GmbH
  4. * Heiko Schocher <hs@denx.de>
  5. * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <dm.h>
  10. #include <clk.h>
  11. #include <log.h>
  12. #include <rtc.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/delay.h>
  16. /* RTC registers */
  17. #define OMAP_RTC_SECONDS_REG 0x00
  18. #define OMAP_RTC_MINUTES_REG 0x04
  19. #define OMAP_RTC_HOURS_REG 0x08
  20. #define OMAP_RTC_DAYS_REG 0x0C
  21. #define OMAP_RTC_MONTHS_REG 0x10
  22. #define OMAP_RTC_YEARS_REG 0x14
  23. #define OMAP_RTC_WEEKS_REG 0x18
  24. #define OMAP_RTC_CTRL_REG 0x40
  25. #define OMAP_RTC_STATUS_REG 0x44
  26. #define OMAP_RTC_INTERRUPTS_REG 0x48
  27. #define OMAP_RTC_OSC_REG 0x54
  28. #define OMAP_RTC_SCRATCH0_REG 0x60
  29. #define OMAP_RTC_SCRATCH1_REG 0x64
  30. #define OMAP_RTC_SCRATCH2_REG 0x68
  31. #define OMAP_RTC_KICK0_REG 0x6c
  32. #define OMAP_RTC_KICK1_REG 0x70
  33. #define OMAP_RTC_PMIC_REG 0x98
  34. /* OMAP_RTC_CTRL_REG bit fields: */
  35. #define OMAP_RTC_CTRL_SPLIT BIT(7)
  36. #define OMAP_RTC_CTRL_DISABLE BIT(6)
  37. #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
  38. #define OMAP_RTC_CTRL_TEST BIT(4)
  39. #define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
  40. #define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
  41. #define OMAP_RTC_CTRL_ROUND_30S BIT(1)
  42. #define OMAP_RTC_CTRL_STOP BIT(0)
  43. /* OMAP_RTC_STATUS_REG bit fields */
  44. #define OMAP_RTC_STATUS_POWER_UP BIT(7)
  45. #define OMAP_RTC_STATUS_ALARM2 BIT(7)
  46. #define OMAP_RTC_STATUS_ALARM BIT(6)
  47. #define OMAP_RTC_STATUS_1D_EVENT BIT(5)
  48. #define OMAP_RTC_STATUS_1H_EVENT BIT(4)
  49. #define OMAP_RTC_STATUS_1M_EVENT BIT(3)
  50. #define OMAP_RTC_STATUS_1S_EVENT BIT(2)
  51. #define OMAP_RTC_STATUS_RUN BIT(1)
  52. #define OMAP_RTC_STATUS_BUSY BIT(0)
  53. /* OMAP_RTC_OSC_REG bit fields */
  54. #define OMAP_RTC_OSC_32KCLK_EN BIT(6)
  55. #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
  56. #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
  57. /* OMAP_RTC_KICKER values */
  58. #define OMAP_RTC_KICK0_VALUE 0x83e70b13
  59. #define OMAP_RTC_KICK1_VALUE 0x95a4f1e0
  60. struct omap_rtc_device_type {
  61. bool has_32kclk_en;
  62. bool has_irqwakeen;
  63. bool has_pmic_mode;
  64. bool has_power_up_reset;
  65. };
  66. struct omap_rtc_priv {
  67. fdt_addr_t base;
  68. u8 max_reg;
  69. struct udevice *dev;
  70. struct clk clk;
  71. bool has_ext_clk;
  72. const struct omap_rtc_device_type *type;
  73. };
  74. static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg)
  75. {
  76. return readb(priv->base + reg);
  77. }
  78. static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg)
  79. {
  80. return readl(priv->base + reg);
  81. }
  82. static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg,
  83. u8 val)
  84. {
  85. writeb(val, priv->base + reg);
  86. }
  87. static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg,
  88. u32 val)
  89. {
  90. writel(val, priv->base + reg);
  91. }
  92. static inline void omap_rtc_unlock(struct omap_rtc_priv *priv)
  93. {
  94. omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE);
  95. omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE);
  96. }
  97. static inline void omap_rtc_lock(struct omap_rtc_priv *priv)
  98. {
  99. omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0);
  100. omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0);
  101. }
  102. static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv)
  103. {
  104. int count;
  105. u8 status;
  106. status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
  107. if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) {
  108. printf("RTC doesn't run\n");
  109. return -1;
  110. }
  111. /* BUSY may stay active for 1/32768 second (~30 usec) */
  112. for (count = 0; count < 50; count++) {
  113. if (!(status & OMAP_RTC_STATUS_BUSY))
  114. break;
  115. udelay(1);
  116. status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
  117. }
  118. /* now we have ~15 usec to read/write various registers */
  119. return 0;
  120. }
  121. static int omap_rtc_reset(struct udevice *dev)
  122. {
  123. struct omap_rtc_priv *priv = dev_get_priv(dev);
  124. /* run RTC counter */
  125. omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01);
  126. return 0;
  127. }
  128. static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm)
  129. {
  130. struct omap_rtc_priv *priv = dev_get_priv(dev);
  131. int ret;
  132. ret = omap_rtc_wait_not_busy(priv);
  133. if (ret)
  134. return ret;
  135. omap_rtc_unlock(priv);
  136. omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100));
  137. omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon));
  138. omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday));
  139. omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday));
  140. omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour));
  141. omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min));
  142. omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec));
  143. omap_rtc_lock(priv);
  144. dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  145. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
  146. tm->tm_min, tm->tm_sec);
  147. return 0;
  148. }
  149. static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm)
  150. {
  151. struct omap_rtc_priv *priv = dev_get_priv(dev);
  152. unsigned long sec, min, hour, mday, wday, mon_cent, year;
  153. int ret;
  154. ret = omap_rtc_wait_not_busy(priv);
  155. if (ret)
  156. return ret;
  157. sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG);
  158. min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG);
  159. hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG);
  160. mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG);
  161. wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG);
  162. mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG);
  163. year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG);
  164. dev_dbg(dev,
  165. "Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
  166. "hr: %02lx min: %02lx sec: %02lx\n",
  167. year, mon_cent, mday, wday,
  168. hour, min, sec);
  169. tm->tm_sec = bcd2bin(sec & 0x7F);
  170. tm->tm_min = bcd2bin(min & 0x7F);
  171. tm->tm_hour = bcd2bin(hour & 0x3F);
  172. tm->tm_mday = bcd2bin(mday & 0x3F);
  173. tm->tm_mon = bcd2bin(mon_cent & 0x1F);
  174. tm->tm_year = bcd2bin(year) + 2000;
  175. tm->tm_wday = bcd2bin(wday & 0x07);
  176. tm->tm_yday = 0;
  177. tm->tm_isdst = 0;
  178. dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  179. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
  180. tm->tm_min, tm->tm_sec);
  181. return 0;
  182. }
  183. static int omap_rtc_scratch_read(struct udevice *dev, uint offset,
  184. u8 *buffer, uint len)
  185. {
  186. struct omap_rtc_priv *priv = dev_get_priv(dev);
  187. u32 *val = (u32 *)buffer;
  188. unsigned int reg;
  189. int i;
  190. if (len & 3)
  191. return -EFAULT;
  192. for (i = 0; i < len / 4; i++) {
  193. reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
  194. if (reg >= OMAP_RTC_KICK0_REG)
  195. return -EFAULT;
  196. val[i] = omap_rtc_readl(priv, reg);
  197. }
  198. return 0;
  199. }
  200. static int omap_rtc_scratch_write(struct udevice *dev, uint offset,
  201. const u8 *buffer, uint len)
  202. {
  203. struct omap_rtc_priv *priv = dev_get_priv(dev);
  204. u32 *val = (u32 *)buffer;
  205. unsigned int reg;
  206. int i;
  207. if (len & 3)
  208. return -EFAULT;
  209. omap_rtc_unlock(priv);
  210. for (i = 0; i < len / 4; i++) {
  211. reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
  212. if (reg >= OMAP_RTC_KICK0_REG)
  213. return -EFAULT;
  214. omap_rtc_writel(priv, reg, val[i]);
  215. }
  216. omap_rtc_lock(priv);
  217. return 0;
  218. }
  219. static int omap_rtc_remove(struct udevice *dev)
  220. {
  221. struct omap_rtc_priv *priv = dev_get_priv(dev);
  222. u8 reg;
  223. if (priv->clk.dev)
  224. clk_disable(&priv->clk);
  225. omap_rtc_unlock(priv);
  226. /* leave rtc running, but disable irqs */
  227. omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0);
  228. if (priv->has_ext_clk) {
  229. reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
  230. reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
  231. omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
  232. }
  233. omap_rtc_lock(priv);
  234. return 0;
  235. }
  236. static int omap_rtc_probe(struct udevice *dev)
  237. {
  238. struct omap_rtc_priv *priv = dev_get_priv(dev);
  239. struct rtc_time tm;
  240. u8 reg, mask, new_ctrl;
  241. priv->dev = dev;
  242. priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev);
  243. priv->max_reg = OMAP_RTC_PMIC_REG;
  244. if (!clk_get_by_name(dev, "ext-clk", &priv->clk))
  245. priv->has_ext_clk = true;
  246. else
  247. clk_get_by_name(dev, "int-clk", &priv->clk);
  248. if (priv->clk.dev)
  249. clk_enable(&priv->clk);
  250. else
  251. dev_warn(dev, "missing clock\n");
  252. omap_rtc_unlock(priv);
  253. /*
  254. * disable interrupts
  255. *
  256. * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
  257. */
  258. omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0);
  259. if (priv->type->has_32kclk_en) {
  260. reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
  261. omap_rtc_writeb(priv, OMAP_RTC_OSC_REG,
  262. reg | OMAP_RTC_OSC_32KCLK_EN);
  263. }
  264. /* clear old status */
  265. reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
  266. mask = OMAP_RTC_STATUS_ALARM;
  267. if (priv->type->has_pmic_mode)
  268. mask |= OMAP_RTC_STATUS_ALARM2;
  269. if (priv->type->has_power_up_reset) {
  270. mask |= OMAP_RTC_STATUS_POWER_UP;
  271. if (reg & OMAP_RTC_STATUS_POWER_UP)
  272. dev_info(dev, "RTC power up reset detected\n");
  273. }
  274. if (reg & mask)
  275. omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask);
  276. /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
  277. reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG);
  278. if (reg & OMAP_RTC_CTRL_STOP)
  279. dev_info(dev, "already running\n");
  280. /* force to 24 hour mode */
  281. new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
  282. new_ctrl |= OMAP_RTC_CTRL_STOP;
  283. /*
  284. * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
  285. *
  286. * - Device wake-up capability setting should come through chip
  287. * init logic. OMAP1 boards should initialize the "wakeup capable"
  288. * flag in the platform device if the board is wired right for
  289. * being woken up by RTC alarm. For OMAP-L138, this capability
  290. * is built into the SoC by the "Deep Sleep" capability.
  291. *
  292. * - Boards wired so RTC_ON_nOFF is used as the reset signal,
  293. * rather than nPWRON_RESET, should forcibly enable split
  294. * power mode. (Some chip errata report that RTC_CTRL_SPLIT
  295. * is write-only, and always reads as zero...)
  296. */
  297. if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
  298. dev_info(dev, "split power mode\n");
  299. if (reg != new_ctrl)
  300. omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl);
  301. /*
  302. * If we have the external clock then switch to it so we can keep
  303. * ticking across suspend.
  304. */
  305. if (priv->has_ext_clk) {
  306. reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
  307. reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
  308. reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
  309. omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
  310. }
  311. omap_rtc_lock(priv);
  312. if (omap_rtc_get(dev, &tm)) {
  313. dev_err(dev, "failed to get datetime\n");
  314. } else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 &&
  315. tm.tm_wday == 0) {
  316. tm.tm_wday = 6;
  317. omap_rtc_set(dev, &tm);
  318. }
  319. return 0;
  320. }
  321. static int omap_rtc_of_to_plat(struct udevice *dev)
  322. {
  323. struct omap_rtc_priv *priv = dev_get_priv(dev);
  324. priv->base = dev_read_addr(dev);
  325. if (priv->base == FDT_ADDR_T_NONE) {
  326. dev_err(dev, "invalid address\n");
  327. return -EINVAL;
  328. }
  329. dev_dbg(dev, "base=%pa\n", &priv->base);
  330. return 0;
  331. }
  332. static const struct rtc_ops omap_rtc_ops = {
  333. .get = omap_rtc_get,
  334. .set = omap_rtc_set,
  335. .reset = omap_rtc_reset,
  336. .read = omap_rtc_scratch_read,
  337. .write = omap_rtc_scratch_write,
  338. };
  339. static const struct omap_rtc_device_type omap_rtc_am3352_type = {
  340. .has_32kclk_en = true,
  341. .has_irqwakeen = true,
  342. .has_pmic_mode = true,
  343. };
  344. static const struct omap_rtc_device_type omap_rtc_da830_type = {
  345. .has_32kclk_en = false,
  346. .has_irqwakeen = false,
  347. .has_pmic_mode = false,
  348. };
  349. static const struct udevice_id omap_rtc_ids[] = {
  350. {.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type},
  351. {.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type }
  352. };
  353. U_BOOT_DRIVER(omap_rtc) = {
  354. .name = "omap_rtc",
  355. .id = UCLASS_RTC,
  356. .of_match = omap_rtc_ids,
  357. .ops = &omap_rtc_ops,
  358. .of_to_plat = omap_rtc_of_to_plat,
  359. .probe = omap_rtc_probe,
  360. .remove = omap_rtc_remove,
  361. .priv_auto = sizeof(struct omap_rtc_priv),
  362. };