stm32-reset.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #define LOG_CATEGORY UCLASS_RESET
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <reset-uclass.h>
  13. #include <stm32_rcc.h>
  14. #include <asm/io.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. /* offset of register without set/clear management */
  18. #define RCC_MP_GCR_OFFSET 0x10C
  19. /* reset clear offset for STM32MP RCC */
  20. #define RCC_CL 0x4
  21. struct stm32_reset_priv {
  22. fdt_addr_t base;
  23. };
  24. static int stm32_reset_request(struct reset_ctl *reset_ctl)
  25. {
  26. return 0;
  27. }
  28. static int stm32_reset_free(struct reset_ctl *reset_ctl)
  29. {
  30. return 0;
  31. }
  32. static int stm32_reset_assert(struct reset_ctl *reset_ctl)
  33. {
  34. struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
  35. int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
  36. int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
  37. dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
  38. reset_ctl->id, bank, offset);
  39. if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
  40. if (bank != RCC_MP_GCR_OFFSET)
  41. /* reset assert is done in rcc set register */
  42. writel(BIT(offset), priv->base + bank);
  43. else
  44. clrbits_le32(priv->base + bank, BIT(offset));
  45. else
  46. setbits_le32(priv->base + bank, BIT(offset));
  47. return 0;
  48. }
  49. static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
  50. {
  51. struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
  52. int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
  53. int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
  54. dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
  55. reset_ctl->id, bank, offset);
  56. if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
  57. if (bank != RCC_MP_GCR_OFFSET)
  58. /* reset deassert is done in rcc clr register */
  59. writel(BIT(offset), priv->base + bank + RCC_CL);
  60. else
  61. setbits_le32(priv->base + bank, BIT(offset));
  62. else
  63. clrbits_le32(priv->base + bank, BIT(offset));
  64. return 0;
  65. }
  66. static const struct reset_ops stm32_reset_ops = {
  67. .request = stm32_reset_request,
  68. .rfree = stm32_reset_free,
  69. .rst_assert = stm32_reset_assert,
  70. .rst_deassert = stm32_reset_deassert,
  71. };
  72. static int stm32_reset_probe(struct udevice *dev)
  73. {
  74. struct stm32_reset_priv *priv = dev_get_priv(dev);
  75. priv->base = dev_read_addr(dev);
  76. if (priv->base == FDT_ADDR_T_NONE) {
  77. /* for MFD, get address of parent */
  78. priv->base = dev_read_addr(dev->parent);
  79. if (priv->base == FDT_ADDR_T_NONE)
  80. return -EINVAL;
  81. }
  82. return 0;
  83. }
  84. U_BOOT_DRIVER(stm32_rcc_reset) = {
  85. .name = "stm32_rcc_reset",
  86. .id = UCLASS_RESET,
  87. .probe = stm32_reset_probe,
  88. .priv_auto = sizeof(struct stm32_reset_priv),
  89. .ops = &stm32_reset_ops,
  90. };