reset-imx7.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017, Impinj, Inc.
  4. */
  5. #include <log.h>
  6. #include <malloc.h>
  7. #include <asm/io.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dt-bindings/reset/imx7-reset.h>
  11. #include <dt-bindings/reset/imx8mq-reset.h>
  12. #include <reset-uclass.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. struct imx7_reset_priv {
  16. void __iomem *base;
  17. struct reset_ops ops;
  18. };
  19. struct imx7_src_signal {
  20. unsigned int offset, bit;
  21. };
  22. enum imx7_src_registers {
  23. SRC_A7RCR0 = 0x0004,
  24. SRC_M4RCR = 0x000c,
  25. SRC_ERCR = 0x0014,
  26. SRC_HSICPHY_RCR = 0x001c,
  27. SRC_USBOPHY1_RCR = 0x0020,
  28. SRC_USBOPHY2_RCR = 0x0024,
  29. SRC_MIPIPHY_RCR = 0x0028,
  30. SRC_PCIEPHY_RCR = 0x002c,
  31. SRC_DDRC_RCR = 0x1000,
  32. };
  33. static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
  34. [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
  35. [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
  36. [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
  37. [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
  38. [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
  39. [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
  40. [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
  41. [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
  42. [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
  43. [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
  44. [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
  45. [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
  46. [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
  47. [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
  48. [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
  49. [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
  50. [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
  51. [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
  52. [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
  53. [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
  54. [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
  55. [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  56. [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  57. [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  58. [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
  59. [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
  60. };
  61. static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
  62. {
  63. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  64. const struct imx7_src_signal *sig = imx7_src_signals;
  65. u32 val;
  66. if (rst->id >= IMX7_RESET_NUM)
  67. return -EINVAL;
  68. if (rst->id == IMX7_RESET_PCIEPHY) {
  69. /*
  70. * wait for more than 10us to release phy g_rst and
  71. * btnrst
  72. */
  73. udelay(10);
  74. }
  75. val = readl(priv->base + sig[rst->id].offset);
  76. switch (rst->id) {
  77. case IMX7_RESET_PCIE_CTRL_APPS_EN:
  78. val |= sig[rst->id].bit;
  79. break;
  80. default:
  81. val &= ~sig[rst->id].bit;
  82. break;
  83. }
  84. writel(val, priv->base + sig[rst->id].offset);
  85. return 0;
  86. }
  87. static int imx7_reset_assert_imx7(struct reset_ctl *rst)
  88. {
  89. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  90. const struct imx7_src_signal *sig = imx7_src_signals;
  91. u32 val;
  92. if (rst->id >= IMX7_RESET_NUM)
  93. return -EINVAL;
  94. val = readl(priv->base + sig[rst->id].offset);
  95. switch (rst->id) {
  96. case IMX7_RESET_PCIE_CTRL_APPS_EN:
  97. val &= ~sig[rst->id].bit;
  98. break;
  99. default:
  100. val |= sig[rst->id].bit;
  101. break;
  102. }
  103. writel(val, priv->base + sig[rst->id].offset);
  104. return 0;
  105. }
  106. enum imx8mq_src_registers {
  107. SRC_A53RCR0 = 0x0004,
  108. SRC_HDMI_RCR = 0x0030,
  109. SRC_DISP_RCR = 0x0034,
  110. SRC_GPU_RCR = 0x0040,
  111. SRC_VPU_RCR = 0x0044,
  112. SRC_PCIE2_RCR = 0x0048,
  113. SRC_MIPIPHY1_RCR = 0x004c,
  114. SRC_MIPIPHY2_RCR = 0x0050,
  115. SRC_DDRC2_RCR = 0x1004,
  116. };
  117. static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
  118. [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
  119. [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
  120. [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
  121. [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
  122. [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
  123. [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
  124. [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
  125. [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
  126. [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
  127. [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
  128. [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
  129. [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
  130. [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
  131. [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
  132. [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
  133. [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
  134. [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
  135. [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
  136. [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
  137. [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
  138. [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
  139. [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
  140. [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
  141. [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
  142. [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
  143. [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
  144. [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
  145. BIT(2) | BIT(1) },
  146. [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
  147. [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
  148. [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
  149. [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
  150. [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
  151. [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
  152. [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
  153. [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
  154. BIT(2) | BIT(1) },
  155. [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
  156. [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
  157. [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
  158. [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
  159. [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
  160. [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
  161. [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
  162. [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
  163. [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
  164. [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
  165. [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
  166. [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
  167. [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
  168. [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
  169. [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
  170. };
  171. static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
  172. {
  173. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  174. const struct imx7_src_signal *sig = imx8mq_src_signals;
  175. u32 val;
  176. if (rst->id >= IMX8MQ_RESET_NUM)
  177. return -EINVAL;
  178. if (rst->id == IMX8MQ_RESET_PCIEPHY ||
  179. rst->id == IMX8MQ_RESET_PCIEPHY2) {
  180. /*
  181. * wait for more than 10us to release phy g_rst and
  182. * btnrst
  183. */
  184. udelay(10);
  185. }
  186. val = readl(priv->base + sig[rst->id].offset);
  187. switch (rst->id) {
  188. case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
  189. case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
  190. case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
  191. case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
  192. case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
  193. case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
  194. case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
  195. val |= sig[rst->id].bit;
  196. break;
  197. default:
  198. val &= ~sig[rst->id].bit;
  199. break;
  200. }
  201. writel(val, priv->base + sig[rst->id].offset);
  202. return 0;
  203. }
  204. static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
  205. {
  206. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  207. const struct imx7_src_signal *sig = imx8mq_src_signals;
  208. u32 val;
  209. if (rst->id >= IMX8MQ_RESET_NUM)
  210. return -EINVAL;
  211. val = readl(priv->base + sig[rst->id].offset);
  212. switch (rst->id) {
  213. case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
  214. case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
  215. case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */
  216. case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */
  217. case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */
  218. case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
  219. case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
  220. val &= ~sig[rst->id].bit;
  221. break;
  222. default:
  223. val |= sig[rst->id].bit;
  224. break;
  225. }
  226. writel(val, priv->base + sig[rst->id].offset);
  227. return 0;
  228. }
  229. static int imx7_reset_assert(struct reset_ctl *rst)
  230. {
  231. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  232. return priv->ops.rst_assert(rst);
  233. }
  234. static int imx7_reset_deassert(struct reset_ctl *rst)
  235. {
  236. struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
  237. return priv->ops.rst_deassert(rst);
  238. }
  239. static int imx7_reset_free(struct reset_ctl *rst)
  240. {
  241. return 0;
  242. }
  243. static int imx7_reset_request(struct reset_ctl *rst)
  244. {
  245. return 0;
  246. }
  247. static const struct reset_ops imx7_reset_reset_ops = {
  248. .request = imx7_reset_request,
  249. .rfree = imx7_reset_free,
  250. .rst_assert = imx7_reset_assert,
  251. .rst_deassert = imx7_reset_deassert,
  252. };
  253. static const struct udevice_id imx7_reset_ids[] = {
  254. { .compatible = "fsl,imx7d-src" },
  255. { .compatible = "fsl,imx8mq-src" },
  256. { }
  257. };
  258. static int imx7_reset_probe(struct udevice *dev)
  259. {
  260. struct imx7_reset_priv *priv = dev_get_priv(dev);
  261. priv->base = dev_remap_addr(dev);
  262. if (!priv->base)
  263. return -ENOMEM;
  264. if (device_is_compatible(dev, "fsl,imx8mq-src")) {
  265. priv->ops.rst_assert = imx7_reset_assert_imx8mq;
  266. priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
  267. } else if (device_is_compatible(dev, "fsl,imx7d-src")) {
  268. priv->ops.rst_assert = imx7_reset_assert_imx7;
  269. priv->ops.rst_deassert = imx7_reset_deassert_imx7;
  270. }
  271. return 0;
  272. }
  273. U_BOOT_DRIVER(imx7_reset) = {
  274. .name = "imx7_reset",
  275. .id = UCLASS_RESET,
  276. .of_match = imx7_reset_ids,
  277. .ops = &imx7_reset_reset_ops,
  278. .probe = imx7_reset_probe,
  279. .priv_auto = sizeof(struct imx7_reset_priv),
  280. };