stm32_sdram.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #define LOG_CATEGORY UCLASS_RAM
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #define MEM_MODE_MASK GENMASK(2, 0)
  18. #define SWP_FMC_OFFSET 10
  19. #define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
  20. #define NOT_FOUND 0xff
  21. struct stm32_fmc_regs {
  22. /* 0x0 */
  23. u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
  24. u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
  25. u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
  26. u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
  27. u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
  28. u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
  29. u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
  30. u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
  31. u32 reserved1[24];
  32. /* 0x80 */
  33. u32 pcr; /* NAND Flash control register */
  34. u32 sr; /* FIFO status and interrupt register */
  35. u32 pmem; /* Common memory space timing register */
  36. u32 patt; /* Attribute memory space timing registers */
  37. u32 reserved2[1];
  38. u32 eccr; /* ECC result registers */
  39. u32 reserved3[27];
  40. /* 0x104 */
  41. u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
  42. u32 reserved4[1];
  43. u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
  44. u32 reserved5[1];
  45. u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
  46. u32 reserved6[1];
  47. u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
  48. u32 reserved7[8];
  49. /* 0x140 */
  50. u32 sdcr1; /* SDRAM Control register 1 */
  51. u32 sdcr2; /* SDRAM Control register 2 */
  52. u32 sdtr1; /* SDRAM Timing register 1 */
  53. u32 sdtr2; /* SDRAM Timing register 2 */
  54. u32 sdcmr; /* SDRAM Mode register */
  55. u32 sdrtr; /* SDRAM Refresh timing register */
  56. u32 sdsr; /* SDRAM Status register */
  57. };
  58. /*
  59. * NOR/PSRAM Control register BCR1
  60. * FMC controller Enable, only availabe for H7
  61. */
  62. #define FMC_BCR1_FMCEN BIT(31)
  63. /* Control register SDCR */
  64. #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
  65. #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
  66. #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
  67. #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
  68. #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
  69. #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
  70. #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
  71. #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
  72. #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
  73. /* Timings register SDTR */
  74. #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
  75. #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
  76. #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
  77. #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
  78. #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
  79. #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
  80. #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
  81. #define FMC_SDCMR_NRFS_SHIFT 5
  82. #define FMC_SDCMR_MODE_NORMAL 0
  83. #define FMC_SDCMR_MODE_START_CLOCK 1
  84. #define FMC_SDCMR_MODE_PRECHARGE 2
  85. #define FMC_SDCMR_MODE_AUTOREFRESH 3
  86. #define FMC_SDCMR_MODE_WRITE_MODE 4
  87. #define FMC_SDCMR_MODE_SELFREFRESH 5
  88. #define FMC_SDCMR_MODE_POWERDOWN 6
  89. #define FMC_SDCMR_BANK_1 BIT(4)
  90. #define FMC_SDCMR_BANK_2 BIT(3)
  91. #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
  92. #define FMC_SDSR_BUSY BIT(5)
  93. #define FMC_BUSY_WAIT(regs) do { \
  94. __asm__ __volatile__ ("dsb" : : : "memory"); \
  95. while (regs->sdsr & FMC_SDSR_BUSY) \
  96. ; \
  97. } while (0)
  98. struct stm32_sdram_control {
  99. u8 no_columns;
  100. u8 no_rows;
  101. u8 memory_width;
  102. u8 no_banks;
  103. u8 cas_latency;
  104. u8 sdclk;
  105. u8 rd_burst;
  106. u8 rd_pipe_delay;
  107. };
  108. struct stm32_sdram_timing {
  109. u8 tmrd;
  110. u8 txsr;
  111. u8 tras;
  112. u8 trc;
  113. u8 trp;
  114. u8 twr;
  115. u8 trcd;
  116. };
  117. enum stm32_fmc_bank {
  118. SDRAM_BANK1,
  119. SDRAM_BANK2,
  120. MAX_SDRAM_BANK,
  121. };
  122. enum stm32_fmc_family {
  123. STM32F7_FMC,
  124. STM32H7_FMC,
  125. };
  126. struct bank_params {
  127. struct stm32_sdram_control *sdram_control;
  128. struct stm32_sdram_timing *sdram_timing;
  129. u32 sdram_ref_count;
  130. enum stm32_fmc_bank target_bank;
  131. };
  132. struct stm32_sdram_params {
  133. struct stm32_fmc_regs *base;
  134. u8 no_sdram_banks;
  135. struct bank_params bank_params[MAX_SDRAM_BANK];
  136. enum stm32_fmc_family family;
  137. };
  138. #define SDRAM_MODE_BL_SHIFT 0
  139. #define SDRAM_MODE_CAS_SHIFT 4
  140. #define SDRAM_MODE_BL 0
  141. int stm32_sdram_init(struct udevice *dev)
  142. {
  143. struct stm32_sdram_params *params = dev_get_plat(dev);
  144. struct stm32_sdram_control *control;
  145. struct stm32_sdram_timing *timing;
  146. struct stm32_fmc_regs *regs = params->base;
  147. enum stm32_fmc_bank target_bank;
  148. u32 ctb; /* SDCMR register: Command Target Bank */
  149. u32 ref_count;
  150. u8 i;
  151. /* disable the FMC controller */
  152. if (params->family == STM32H7_FMC)
  153. clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
  154. for (i = 0; i < params->no_sdram_banks; i++) {
  155. control = params->bank_params[i].sdram_control;
  156. timing = params->bank_params[i].sdram_timing;
  157. target_bank = params->bank_params[i].target_bank;
  158. ref_count = params->bank_params[i].sdram_ref_count;
  159. writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
  160. | control->cas_latency << FMC_SDCR_CAS_SHIFT
  161. | control->no_banks << FMC_SDCR_NB_SHIFT
  162. | control->memory_width << FMC_SDCR_MWID_SHIFT
  163. | control->no_rows << FMC_SDCR_NR_SHIFT
  164. | control->no_columns << FMC_SDCR_NC_SHIFT
  165. | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
  166. | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
  167. &regs->sdcr1);
  168. if (target_bank == SDRAM_BANK2)
  169. writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
  170. | control->no_banks << FMC_SDCR_NB_SHIFT
  171. | control->memory_width << FMC_SDCR_MWID_SHIFT
  172. | control->no_rows << FMC_SDCR_NR_SHIFT
  173. | control->no_columns << FMC_SDCR_NC_SHIFT,
  174. &regs->sdcr2);
  175. writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
  176. | timing->trp << FMC_SDTR_TRP_SHIFT
  177. | timing->twr << FMC_SDTR_TWR_SHIFT
  178. | timing->trc << FMC_SDTR_TRC_SHIFT
  179. | timing->tras << FMC_SDTR_TRAS_SHIFT
  180. | timing->txsr << FMC_SDTR_TXSR_SHIFT
  181. | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
  182. &regs->sdtr1);
  183. if (target_bank == SDRAM_BANK2)
  184. writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
  185. | timing->trp << FMC_SDTR_TRP_SHIFT
  186. | timing->twr << FMC_SDTR_TWR_SHIFT
  187. | timing->trc << FMC_SDTR_TRC_SHIFT
  188. | timing->tras << FMC_SDTR_TRAS_SHIFT
  189. | timing->txsr << FMC_SDTR_TXSR_SHIFT
  190. | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
  191. &regs->sdtr2);
  192. if (target_bank == SDRAM_BANK1)
  193. ctb = FMC_SDCMR_BANK_1;
  194. else
  195. ctb = FMC_SDCMR_BANK_2;
  196. writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
  197. udelay(200); /* 200 us delay, page 10, "Power-Up" */
  198. FMC_BUSY_WAIT(regs);
  199. writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
  200. udelay(100);
  201. FMC_BUSY_WAIT(regs);
  202. writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
  203. &regs->sdcmr);
  204. udelay(100);
  205. FMC_BUSY_WAIT(regs);
  206. writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
  207. | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
  208. << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
  209. &regs->sdcmr);
  210. udelay(100);
  211. FMC_BUSY_WAIT(regs);
  212. writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
  213. FMC_BUSY_WAIT(regs);
  214. /* Refresh timer */
  215. writel(ref_count << 1, &regs->sdrtr);
  216. }
  217. /* enable the FMC controller */
  218. if (params->family == STM32H7_FMC)
  219. setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
  220. return 0;
  221. }
  222. static int stm32_fmc_of_to_plat(struct udevice *dev)
  223. {
  224. struct stm32_sdram_params *params = dev_get_plat(dev);
  225. struct bank_params *bank_params;
  226. struct ofnode_phandle_args args;
  227. u32 *syscfg_base;
  228. u32 mem_remap;
  229. u32 swp_fmc;
  230. ofnode bank_node;
  231. char *bank_name;
  232. char _bank_name[128] = {0};
  233. u8 bank = 0;
  234. int ret;
  235. ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
  236. &args);
  237. if (ret) {
  238. dev_dbg(dev, "can't find syscon device (%d)\n", ret);
  239. } else {
  240. syscfg_base = (u32 *)ofnode_get_addr(args.node);
  241. mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
  242. if (mem_remap != NOT_FOUND) {
  243. /* set memory mapping selection */
  244. clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
  245. } else {
  246. dev_dbg(dev, "cannot find st,mem_remap property\n");
  247. }
  248. swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
  249. if (swp_fmc != NOT_FOUND) {
  250. /* set fmc swapping selection */
  251. clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
  252. } else {
  253. dev_dbg(dev, "cannot find st,swp_fmc property\n");
  254. }
  255. dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
  256. }
  257. dev_for_each_subnode(bank_node, dev) {
  258. /* extract the bank index from DT */
  259. bank_name = (char *)ofnode_get_name(bank_node);
  260. strlcpy(_bank_name, bank_name, sizeof(_bank_name));
  261. bank_name = (char *)_bank_name;
  262. strsep(&bank_name, "@");
  263. if (!bank_name) {
  264. pr_err("missing sdram bank index");
  265. return -EINVAL;
  266. }
  267. bank_params = &params->bank_params[bank];
  268. strict_strtoul(bank_name, 10,
  269. (long unsigned int *)&bank_params->target_bank);
  270. if (bank_params->target_bank >= MAX_SDRAM_BANK) {
  271. pr_err("Found bank %d , but only bank 0 and 1 are supported",
  272. bank_params->target_bank);
  273. return -EINVAL;
  274. }
  275. debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
  276. params->bank_params[bank].sdram_control =
  277. (struct stm32_sdram_control *)
  278. ofnode_read_u8_array_ptr(bank_node,
  279. "st,sdram-control",
  280. sizeof(struct stm32_sdram_control));
  281. if (!params->bank_params[bank].sdram_control) {
  282. pr_err("st,sdram-control not found for %s",
  283. ofnode_get_name(bank_node));
  284. return -EINVAL;
  285. }
  286. params->bank_params[bank].sdram_timing =
  287. (struct stm32_sdram_timing *)
  288. ofnode_read_u8_array_ptr(bank_node,
  289. "st,sdram-timing",
  290. sizeof(struct stm32_sdram_timing));
  291. if (!params->bank_params[bank].sdram_timing) {
  292. pr_err("st,sdram-timing not found for %s",
  293. ofnode_get_name(bank_node));
  294. return -EINVAL;
  295. }
  296. bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
  297. "st,sdram-refcount", 8196);
  298. bank++;
  299. }
  300. params->no_sdram_banks = bank;
  301. dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);
  302. return 0;
  303. }
  304. static int stm32_fmc_probe(struct udevice *dev)
  305. {
  306. struct stm32_sdram_params *params = dev_get_plat(dev);
  307. int ret;
  308. fdt_addr_t addr;
  309. addr = dev_read_addr(dev);
  310. if (addr == FDT_ADDR_T_NONE)
  311. return -EINVAL;
  312. params->base = (struct stm32_fmc_regs *)addr;
  313. params->family = dev_get_driver_data(dev);
  314. #ifdef CONFIG_CLK
  315. struct clk clk;
  316. ret = clk_get_by_index(dev, 0, &clk);
  317. if (ret < 0)
  318. return ret;
  319. ret = clk_enable(&clk);
  320. if (ret) {
  321. dev_err(dev, "failed to enable clock\n");
  322. return ret;
  323. }
  324. #endif
  325. ret = stm32_sdram_init(dev);
  326. if (ret)
  327. return ret;
  328. return 0;
  329. }
  330. static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
  331. {
  332. return 0;
  333. }
  334. static struct ram_ops stm32_fmc_ops = {
  335. .get_info = stm32_fmc_get_info,
  336. };
  337. static const struct udevice_id stm32_fmc_ids[] = {
  338. { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
  339. { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
  340. { }
  341. };
  342. U_BOOT_DRIVER(stm32_fmc) = {
  343. .name = "stm32_fmc",
  344. .id = UCLASS_RAM,
  345. .of_match = stm32_fmc_ids,
  346. .ops = &stm32_fmc_ops,
  347. .of_to_plat = stm32_fmc_of_to_plat,
  348. .probe = stm32_fmc_probe,
  349. .plat_auto = sizeof(struct stm32_sdram_params),
  350. };