mpc83xx_sdram.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <ram.h>
  11. #include <asm/bitops.h>
  12. #include <asm/global_data.h>
  13. #include <dt-bindings/memory/mpc83xx-sdram.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /* Masks for the CS config register */
  16. static const u32 CSCONFIG_ENABLE = 0x80000000;
  17. static const u32 BANK_BITS_2;
  18. static const u32 BANK_BITS_3 = 0x00004000;
  19. static const u32 ROW_BITS_12;
  20. static const u32 ROW_BITS_13 = 0x00000100;
  21. static const u32 ROW_BITS_14 = 0x00000200;
  22. static const u32 COL_BITS_8;
  23. static const u32 COL_BITS_9 = 0x00000001;
  24. static const u32 COL_BITS_10 = 0x00000002;
  25. static const u32 COL_BITS_11 = 0x00000003;
  26. /* Shifts for the DDR SDRAM Timing Configuration 3 register */
  27. static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
  28. /* Shifts for the DDR SDRAM Timing Configuration 0 register */
  29. static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1);
  30. static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3);
  31. static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5);
  32. static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7);
  33. static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11);
  34. static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15);
  35. static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23);
  36. static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31);
  37. /* Shifts for the DDR SDRAM Timing Configuration 1 register */
  38. static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3);
  39. static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7);
  40. static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11);
  41. static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15);
  42. static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19);
  43. static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23);
  44. static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27);
  45. static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31);
  46. /* Shifts for the DDR SDRAM Timing Configuration 2 register */
  47. static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8);
  48. static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21);
  49. static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3);
  50. static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12);
  51. static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18);
  52. static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25);
  53. static const uint TIMING_CFG2_FOUR_ACT_SHIFT;
  54. /* Shifts for the DDR SDRAM Control Configuration register */
  55. static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1);
  56. static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2);
  57. static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3);
  58. static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7);
  59. static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10);
  60. static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12);
  61. static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14);
  62. static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16);
  63. static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23);
  64. static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27);
  65. static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28);
  66. static const uint SDRAM_CFG_BI_SHIFT = (31 - 31);
  67. /* Shifts for the DDR SDRAM Control Configuration 2 register */
  68. static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0);
  69. static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2);
  70. static const uint SDRAM_CFG2_DQS_CFG = (31 - 5);
  71. static const uint SDRAM_CFG2_ODT_CFG = (31 - 10);
  72. static const uint SDRAM_CFG2_NUM_PR = (31 - 19);
  73. /* Shifts for the DDR SDRAM Mode register */
  74. static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15);
  75. static const uint SDRAM_MODE_SD_SHIFT = (31 - 31);
  76. /* Shifts for the DDR SDRAM Mode 2 register */
  77. static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15);
  78. static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31);
  79. /* Shifts for the DDR SDRAM Interval Configuration register */
  80. static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15);
  81. static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31);
  82. /* Mask for the DDR SDRAM Mode Control register */
  83. static const u32 SDRAM_CFG_MEM_EN = 0x80000000;
  84. int dram_init(void)
  85. {
  86. struct udevice *ram_ctrl;
  87. int ret;
  88. /* Current assumption: There is only one RAM controller */
  89. ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl);
  90. if (ret) {
  91. debug("%s: uclass_first_device_err failed: %d\n",
  92. __func__, ret);
  93. return ret;
  94. }
  95. /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */
  96. return 0;
  97. }
  98. phys_size_t get_effective_memsize(void)
  99. {
  100. if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
  101. return gd->ram_size;
  102. /* Limit stack to what we can reasonable map */
  103. return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
  104. CONFIG_MAX_MEM_MAPPED : gd->ram_size);
  105. }
  106. /**
  107. * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
  108. * @total_size: The total size of all RAM modules associated with this RAM
  109. * controller in bytes
  110. */
  111. struct mpc83xx_sdram_priv {
  112. ulong total_size;
  113. };
  114. /**
  115. * mpc83xx_sdram_static_init() - Statically initialize a RAM module.
  116. * @node: Device tree node associated with ths module in question
  117. * @cs: The chip select to use for this RAM module
  118. * @mapaddr: The address where the RAM module should be mapped
  119. * @size: The size of the RAM module to be mapped in bytes
  120. *
  121. * Return: 0 if OK, -ve on error
  122. */
  123. static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
  124. {
  125. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  126. u32 msize = size;
  127. u32 msize_log2 = __ilog2(msize);
  128. u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits,
  129. col_bits;
  130. u32 bank_bits_mask, row_bits_mask, col_bits_mask;
  131. /* Configure the DDR local access window */
  132. out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
  133. out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
  134. out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
  135. auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0);
  136. switch (auto_precharge) {
  137. case AUTO_PRECHARGE_ENABLE:
  138. case AUTO_PRECHARGE_DISABLE:
  139. break;
  140. default:
  141. debug("%s: auto_precharge value %d invalid.\n",
  142. ofnode_get_name(node), auto_precharge);
  143. return -EINVAL;
  144. }
  145. odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
  146. switch (odt_rd_cfg) {
  147. case ODT_RD_ONLY_OTHER_DIMM:
  148. if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  149. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  150. debug("%s: odt_rd_cfg value %d invalid.\n",
  151. ofnode_get_name(node), odt_rd_cfg);
  152. return -EINVAL;
  153. }
  154. /* fall through */
  155. case ODT_RD_NEVER:
  156. case ODT_RD_ONLY_CURRENT:
  157. case ODT_RD_ONLY_OTHER_CS:
  158. if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
  159. !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
  160. !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  161. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  162. debug("%s: odt_rd_cfg value %d invalid.\n",
  163. ofnode_get_name(node), odt_rd_cfg);
  164. return -EINVAL;
  165. }
  166. /* fall through */
  167. /* Only MPC832x knows this value */
  168. case ODT_RD_ALL:
  169. break;
  170. default:
  171. debug("%s: odt_rd_cfg value %d invalid.\n",
  172. ofnode_get_name(node), odt_rd_cfg);
  173. return -EINVAL;
  174. }
  175. odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
  176. switch (odt_wr_cfg) {
  177. case ODT_WR_ONLY_OTHER_DIMM:
  178. if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  179. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  180. debug("%s: odt_wr_cfg value %d invalid.\n",
  181. ofnode_get_name(node), odt_wr_cfg);
  182. return -EINVAL;
  183. }
  184. /* fall through */
  185. case ODT_WR_NEVER:
  186. case ODT_WR_ONLY_CURRENT:
  187. case ODT_WR_ONLY_OTHER_CS:
  188. if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
  189. !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
  190. !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  191. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  192. debug("%s: odt_wr_cfg value %d invalid.\n",
  193. ofnode_get_name(node), odt_wr_cfg);
  194. return -EINVAL;
  195. }
  196. /* fall through */
  197. /* MPC832x only knows this value */
  198. case ODT_WR_ALL:
  199. break;
  200. default:
  201. debug("%s: odt_wr_cfg value %d invalid.\n",
  202. ofnode_get_name(node), odt_wr_cfg);
  203. return -EINVAL;
  204. }
  205. bank_bits = ofnode_read_u32_default(node, "bank_bits", 0);
  206. switch (bank_bits) {
  207. case 2:
  208. bank_bits_mask = BANK_BITS_2;
  209. break;
  210. case 3:
  211. bank_bits_mask = BANK_BITS_3;
  212. break;
  213. default:
  214. debug("%s: bank_bits value %d invalid.\n",
  215. ofnode_get_name(node), bank_bits);
  216. return -EINVAL;
  217. }
  218. row_bits = ofnode_read_u32_default(node, "row_bits", 0);
  219. switch (row_bits) {
  220. case 12:
  221. row_bits_mask = ROW_BITS_12;
  222. break;
  223. case 13:
  224. row_bits_mask = ROW_BITS_13;
  225. break;
  226. case 14:
  227. row_bits_mask = ROW_BITS_14;
  228. break;
  229. default:
  230. debug("%s: row_bits value %d invalid.\n",
  231. ofnode_get_name(node), row_bits);
  232. return -EINVAL;
  233. }
  234. col_bits = ofnode_read_u32_default(node, "col_bits", 0);
  235. switch (col_bits) {
  236. case 8:
  237. col_bits_mask = COL_BITS_8;
  238. break;
  239. case 9:
  240. col_bits_mask = COL_BITS_9;
  241. break;
  242. case 10:
  243. col_bits_mask = COL_BITS_10;
  244. break;
  245. case 11:
  246. col_bits_mask = COL_BITS_11;
  247. break;
  248. default:
  249. debug("%s: col_bits value %d invalid.\n",
  250. ofnode_get_name(node), col_bits);
  251. return -EINVAL;
  252. }
  253. /* Write CS config value */
  254. out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
  255. odt_rd_cfg | odt_wr_cfg |
  256. bank_bits_mask | row_bits_mask |
  257. col_bits_mask);
  258. return 0;
  259. }
  260. /**
  261. * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash.
  262. * @node: Device tree node associated with ths module in question
  263. * @cs: The chip select to use for this RAM module
  264. * @mapaddr: The address where the RAM module should be mapped
  265. * @size: The size of the RAM module to be mapped in bytes
  266. *
  267. * Return: 0 if OK, -ve on error
  268. */
  269. static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
  270. {
  271. /* TODO(mario.six@gdsys.cc): Implement */
  272. return 0;
  273. }
  274. static int mpc83xx_sdram_of_to_plat(struct udevice *dev)
  275. {
  276. return 0;
  277. }
  278. static int mpc83xx_sdram_probe(struct udevice *dev)
  279. {
  280. struct mpc83xx_sdram_priv *priv = dev_get_priv(dev);
  281. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  282. int ret = 0;
  283. ofnode subnode;
  284. /* DDR control driver register values */
  285. u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr;
  286. u32 ddrcdr;
  287. /* DDR SDRAM Clock Control register values */
  288. u32 clock_adjust;
  289. /* DDR SDRAM Timing Configuration 3 register values */
  290. u32 ext_refresh_rec, ext_refresh_rec_mask;
  291. /* DDR SDRAM Timing Configuration 0 register values */
  292. u32 read_to_write, write_to_read, read_to_read, write_to_write,
  293. active_powerdown_exit, precharge_powerdown_exit,
  294. odt_powerdown_exit, mode_reg_set_cycle;
  295. u32 timing_cfg_0;
  296. /* DDR SDRAM Timing Configuration 1 register values */
  297. u32 precharge_to_activate, activate_to_precharge,
  298. activate_to_readwrite, mcas_latency, refresh_recovery,
  299. last_data_to_precharge, activate_to_activate,
  300. last_write_data_to_read;
  301. u32 timing_cfg_1;
  302. /* DDR SDRAM Timing Configuration 2 register values */
  303. u32 additive_latency, mcas_to_preamble_override, write_latency,
  304. read_to_precharge, write_cmd_to_write_data,
  305. minimum_cke_pulse_width, four_activates_window;
  306. u32 timing_cfg_2;
  307. /* DDR SDRAM Control Configuration register values */
  308. u32 self_refresh, ecc, registered_dram, sdram_type,
  309. dynamic_power_management, databus_width, nc_auto_precharge,
  310. timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength,
  311. bypass_initialization;
  312. u32 sdram_cfg;
  313. /* DDR SDRAM Control Configuration 2 register values */
  314. u32 force_self_refresh, dll_reset, dqs_config, odt_config,
  315. posted_refreshes;
  316. u32 sdram_cfg2;
  317. /* DDR SDRAM Mode Configuration register values */
  318. u32 sdmode, esdmode;
  319. u32 sdram_mode;
  320. /* DDR SDRAM Mode Configuration 2 register values */
  321. u32 esdmode2, esdmode3;
  322. u32 sdram_mode2;
  323. /* DDR SDRAM Interval Configuration register values */
  324. u32 refresh_interval, precharge_interval;
  325. u32 sdram_interval;
  326. priv->total_size = 0;
  327. /* Disable both banks initially (might be re-enabled in loop below) */
  328. out_be32(&im->ddr.cs_config[0], 0);
  329. out_be32(&im->ddr.cs_config[1], 0);
  330. dso = dev_read_u32_default(dev, "driver_software_override", 0);
  331. if (dso > 1) {
  332. debug("%s: driver_software_override value %d invalid.\n",
  333. dev->name, dso);
  334. return -EINVAL;
  335. }
  336. pz_override = dev_read_u32_default(dev, "p_impedance_override", 0);
  337. switch (pz_override) {
  338. case DSO_P_IMPEDANCE_HIGHEST_Z:
  339. case DSO_P_IMPEDANCE_MUCH_HIGHER_Z:
  340. case DSO_P_IMPEDANCE_HIGHER_Z:
  341. case DSO_P_IMPEDANCE_NOMINAL:
  342. case DSO_P_IMPEDANCE_LOWER_Z:
  343. break;
  344. default:
  345. debug("%s: p_impedance_override value %d invalid.\n",
  346. dev->name, pz_override);
  347. return -EINVAL;
  348. }
  349. nz_override = dev_read_u32_default(dev, "n_impedance_override", 0);
  350. switch (nz_override) {
  351. case DSO_N_IMPEDANCE_HIGHEST_Z:
  352. case DSO_N_IMPEDANCE_MUCH_HIGHER_Z:
  353. case DSO_N_IMPEDANCE_HIGHER_Z:
  354. case DSO_N_IMPEDANCE_NOMINAL:
  355. case DSO_N_IMPEDANCE_LOWER_Z:
  356. break;
  357. default:
  358. debug("%s: n_impedance_override value %d invalid.\n",
  359. dev->name, nz_override);
  360. return -EINVAL;
  361. }
  362. odt_term = dev_read_u32_default(dev, "odt_termination_value", 0);
  363. if (odt_term > 1) {
  364. debug("%s: odt_termination_value value %d invalid.\n",
  365. dev->name, odt_term);
  366. return -EINVAL;
  367. }
  368. ddr_type = dev_read_u32_default(dev, "ddr_type", 0);
  369. if (ddr_type > 1) {
  370. debug("%s: ddr_type value %d invalid.\n",
  371. dev->name, ddr_type);
  372. return -EINVAL;
  373. }
  374. mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0);
  375. if (mvref_sel > 1) {
  376. debug("%s: mvref_sel value %d invalid.\n",
  377. dev->name, mvref_sel);
  378. return -EINVAL;
  379. }
  380. m_odr = dev_read_u32_default(dev, "m_odr", 0);
  381. if (mvref_sel > 1) {
  382. debug("%s: m_odr value %d invalid.\n",
  383. dev->name, m_odr);
  384. return -EINVAL;
  385. }
  386. ddrcdr = dso << (31 - 1) |
  387. pz_override << (31 - 5) |
  388. nz_override << (31 - 9) |
  389. odt_term << (31 - 12) |
  390. ddr_type << (31 - 13) |
  391. mvref_sel << (31 - 29) |
  392. m_odr << (31 - 30) | 1;
  393. /* Configure the DDR control driver register */
  394. out_be32(&im->sysconf.ddrcdr, ddrcdr);
  395. dev_for_each_subnode(subnode, dev) {
  396. u32 val[3];
  397. u32 cs, addr, size;
  398. /* CS, map address, size -> three values */
  399. ofnode_read_u32_array(subnode, "reg", val, 3);
  400. cs = val[0];
  401. addr = val[1];
  402. size = val[2];
  403. if (cs > 1) {
  404. debug("%s: chip select value %d invalid.\n",
  405. dev->name, cs);
  406. return -EINVAL;
  407. }
  408. /* TODO(mario.six@gdsys.cc): Sanity check for size. */
  409. if (ofnode_read_bool(subnode, "read-spd"))
  410. ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size);
  411. else
  412. ret = mpc83xx_sdram_static_init(subnode, cs, addr,
  413. size);
  414. if (ret) {
  415. debug("%s: RAM init failed.\n", dev->name);
  416. return ret;
  417. }
  418. };
  419. /*
  420. * TODO(mario.six@gdsys.cc): This should only occur for static
  421. * configuration
  422. */
  423. clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0);
  424. switch (clock_adjust) {
  425. case CLOCK_ADJUST_025:
  426. case CLOCK_ADJUST_05:
  427. case CLOCK_ADJUST_075:
  428. case CLOCK_ADJUST_1:
  429. break;
  430. default:
  431. debug("%s: clock_adjust value %d invalid.\n",
  432. dev->name, clock_adjust);
  433. return -EINVAL;
  434. }
  435. /* Configure the DDR SDRAM Clock Control register */
  436. out_be32(&im->ddr.sdram_clk_cntl, clock_adjust);
  437. ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0);
  438. switch (ext_refresh_rec) {
  439. case 0:
  440. ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT;
  441. break;
  442. case 16:
  443. ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT;
  444. break;
  445. case 32:
  446. ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT;
  447. break;
  448. case 48:
  449. ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT;
  450. break;
  451. case 64:
  452. ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT;
  453. break;
  454. case 80:
  455. ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT;
  456. break;
  457. case 96:
  458. ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT;
  459. break;
  460. case 112:
  461. ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT;
  462. break;
  463. default:
  464. debug("%s: ext_refresh_rec value %d invalid.\n",
  465. dev->name, ext_refresh_rec);
  466. return -EINVAL;
  467. }
  468. /* Configure the DDR SDRAM Timing Configuration 3 register */
  469. out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
  470. read_to_write = dev_read_u32_default(dev, "read_to_write", 0);
  471. if (read_to_write > 3) {
  472. debug("%s: read_to_write value %d invalid.\n",
  473. dev->name, read_to_write);
  474. return -EINVAL;
  475. }
  476. write_to_read = dev_read_u32_default(dev, "write_to_read", 0);
  477. if (write_to_read > 3) {
  478. debug("%s: write_to_read value %d invalid.\n",
  479. dev->name, write_to_read);
  480. return -EINVAL;
  481. }
  482. read_to_read = dev_read_u32_default(dev, "read_to_read", 0);
  483. if (read_to_read > 3) {
  484. debug("%s: read_to_read value %d invalid.\n",
  485. dev->name, read_to_read);
  486. return -EINVAL;
  487. }
  488. write_to_write = dev_read_u32_default(dev, "write_to_write", 0);
  489. if (write_to_write > 3) {
  490. debug("%s: write_to_write value %d invalid.\n",
  491. dev->name, write_to_write);
  492. return -EINVAL;
  493. }
  494. active_powerdown_exit =
  495. dev_read_u32_default(dev, "active_powerdown_exit", 0);
  496. if (active_powerdown_exit > 7) {
  497. debug("%s: active_powerdown_exit value %d invalid.\n",
  498. dev->name, active_powerdown_exit);
  499. return -EINVAL;
  500. }
  501. precharge_powerdown_exit =
  502. dev_read_u32_default(dev, "precharge_powerdown_exit", 0);
  503. if (precharge_powerdown_exit > 7) {
  504. debug("%s: precharge_powerdown_exit value %d invalid.\n",
  505. dev->name, precharge_powerdown_exit);
  506. return -EINVAL;
  507. }
  508. odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0);
  509. if (odt_powerdown_exit > 15) {
  510. debug("%s: odt_powerdown_exit value %d invalid.\n",
  511. dev->name, odt_powerdown_exit);
  512. return -EINVAL;
  513. }
  514. mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0);
  515. if (mode_reg_set_cycle > 15) {
  516. debug("%s: mode_reg_set_cycle value %d invalid.\n",
  517. dev->name, mode_reg_set_cycle);
  518. return -EINVAL;
  519. }
  520. timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
  521. write_to_read << TIMING_CFG0_WRT_SHIFT |
  522. read_to_read << TIMING_CFG0_RRT_SHIFT |
  523. write_to_write << TIMING_CFG0_WWT_SHIFT |
  524. active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT |
  525. precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT |
  526. odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT |
  527. mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT;
  528. out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
  529. precharge_to_activate =
  530. dev_read_u32_default(dev, "precharge_to_activate", 0);
  531. if (precharge_to_activate > 7 || precharge_to_activate == 0) {
  532. debug("%s: precharge_to_activate value %d invalid.\n",
  533. dev->name, precharge_to_activate);
  534. return -EINVAL;
  535. }
  536. activate_to_precharge =
  537. dev_read_u32_default(dev, "activate_to_precharge", 0);
  538. if (activate_to_precharge > 19) {
  539. debug("%s: activate_to_precharge value %d invalid.\n",
  540. dev->name, activate_to_precharge);
  541. return -EINVAL;
  542. }
  543. activate_to_readwrite =
  544. dev_read_u32_default(dev, "activate_to_readwrite", 0);
  545. if (activate_to_readwrite > 7 || activate_to_readwrite == 0) {
  546. debug("%s: activate_to_readwrite value %d invalid.\n",
  547. dev->name, activate_to_readwrite);
  548. return -EINVAL;
  549. }
  550. mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0);
  551. switch (mcas_latency) {
  552. case CASLAT_20:
  553. case CASLAT_25:
  554. if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) {
  555. debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n",
  556. dev->name);
  557. return -EINVAL;
  558. }
  559. /* fall through */
  560. case CASLAT_30:
  561. case CASLAT_35:
  562. case CASLAT_40:
  563. case CASLAT_45:
  564. case CASLAT_50:
  565. case CASLAT_55:
  566. case CASLAT_60:
  567. case CASLAT_65:
  568. case CASLAT_70:
  569. case CASLAT_75:
  570. case CASLAT_80:
  571. break;
  572. default:
  573. debug("%s: mcas_latency value %d invalid.\n",
  574. dev->name, mcas_latency);
  575. return -EINVAL;
  576. }
  577. refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0);
  578. if (refresh_recovery > 23 || refresh_recovery < 8) {
  579. debug("%s: refresh_recovery value %d invalid.\n",
  580. dev->name, refresh_recovery);
  581. return -EINVAL;
  582. }
  583. last_data_to_precharge =
  584. dev_read_u32_default(dev, "last_data_to_precharge", 0);
  585. if (last_data_to_precharge > 7 || last_data_to_precharge == 0) {
  586. debug("%s: last_data_to_precharge value %d invalid.\n",
  587. dev->name, last_data_to_precharge);
  588. return -EINVAL;
  589. }
  590. activate_to_activate =
  591. dev_read_u32_default(dev, "activate_to_activate", 0);
  592. if (activate_to_activate > 7 || activate_to_activate == 0) {
  593. debug("%s: activate_to_activate value %d invalid.\n",
  594. dev->name, activate_to_activate);
  595. return -EINVAL;
  596. }
  597. last_write_data_to_read =
  598. dev_read_u32_default(dev, "last_write_data_to_read", 0);
  599. if (last_write_data_to_read > 7 || last_write_data_to_read == 0) {
  600. debug("%s: last_write_data_to_read value %d invalid.\n",
  601. dev->name, last_write_data_to_read);
  602. return -EINVAL;
  603. }
  604. timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
  605. (activate_to_precharge > 15 ?
  606. activate_to_precharge - 16 :
  607. activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT |
  608. activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT |
  609. mcas_latency << TIMING_CFG1_CASLAT_SHIFT |
  610. (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT |
  611. last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT |
  612. activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT |
  613. last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT;
  614. /* Configure the DDR SDRAM Timing Configuration 1 register */
  615. out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
  616. additive_latency = dev_read_u32_default(dev, "additive_latency", 0);
  617. if (additive_latency > 5) {
  618. debug("%s: additive_latency value %d invalid.\n",
  619. dev->name, additive_latency);
  620. return -EINVAL;
  621. }
  622. mcas_to_preamble_override =
  623. dev_read_u32_default(dev, "mcas_to_preamble_override", 0);
  624. switch (mcas_to_preamble_override) {
  625. case READ_LAT_PLUS_1:
  626. case READ_LAT:
  627. case READ_LAT_PLUS_1_4:
  628. case READ_LAT_PLUS_1_2:
  629. case READ_LAT_PLUS_3_4:
  630. case READ_LAT_PLUS_5_4:
  631. case READ_LAT_PLUS_3_2:
  632. case READ_LAT_PLUS_7_4:
  633. case READ_LAT_PLUS_2:
  634. case READ_LAT_PLUS_9_4:
  635. case READ_LAT_PLUS_5_2:
  636. case READ_LAT_PLUS_11_4:
  637. case READ_LAT_PLUS_3:
  638. case READ_LAT_PLUS_13_4:
  639. case READ_LAT_PLUS_7_2:
  640. case READ_LAT_PLUS_15_4:
  641. case READ_LAT_PLUS_4:
  642. case READ_LAT_PLUS_17_4:
  643. case READ_LAT_PLUS_9_2:
  644. case READ_LAT_PLUS_19_4:
  645. break;
  646. default:
  647. debug("%s: mcas_to_preamble_override value %d invalid.\n",
  648. dev->name, mcas_to_preamble_override);
  649. return -EINVAL;
  650. }
  651. write_latency = dev_read_u32_default(dev, "write_latency", 0);
  652. if (write_latency > 7 || write_latency == 0) {
  653. debug("%s: write_latency value %d invalid.\n",
  654. dev->name, write_latency);
  655. return -EINVAL;
  656. }
  657. read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0);
  658. if (read_to_precharge > 4 || read_to_precharge == 0) {
  659. debug("%s: read_to_precharge value %d invalid.\n",
  660. dev->name, read_to_precharge);
  661. return -EINVAL;
  662. }
  663. write_cmd_to_write_data =
  664. dev_read_u32_default(dev, "write_cmd_to_write_data", 0);
  665. switch (write_cmd_to_write_data) {
  666. case CLOCK_DELAY_0:
  667. case CLOCK_DELAY_1_4:
  668. case CLOCK_DELAY_1_2:
  669. case CLOCK_DELAY_3_4:
  670. case CLOCK_DELAY_1:
  671. case CLOCK_DELAY_5_4:
  672. case CLOCK_DELAY_3_2:
  673. break;
  674. default:
  675. debug("%s: write_cmd_to_write_data value %d invalid.\n",
  676. dev->name, write_cmd_to_write_data);
  677. return -EINVAL;
  678. }
  679. minimum_cke_pulse_width =
  680. dev_read_u32_default(dev, "minimum_cke_pulse_width", 0);
  681. if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) {
  682. debug("%s: minimum_cke_pulse_width value %d invalid.\n",
  683. dev->name, minimum_cke_pulse_width);
  684. return -EINVAL;
  685. }
  686. four_activates_window =
  687. dev_read_u32_default(dev, "four_activates_window", 0);
  688. if (four_activates_window > 20 || four_activates_window == 0) {
  689. debug("%s: four_activates_window value %d invalid.\n",
  690. dev->name, four_activates_window);
  691. return -EINVAL;
  692. }
  693. timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
  694. mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT |
  695. write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT |
  696. read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT |
  697. write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT |
  698. minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT |
  699. four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT;
  700. out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
  701. self_refresh = dev_read_u32_default(dev, "self_refresh", 0);
  702. switch (self_refresh) {
  703. case SREN_DISABLE:
  704. case SREN_ENABLE:
  705. break;
  706. default:
  707. debug("%s: self_refresh value %d invalid.\n",
  708. dev->name, self_refresh);
  709. return -EINVAL;
  710. }
  711. ecc = dev_read_u32_default(dev, "ecc", 0);
  712. switch (ecc) {
  713. case ECC_DISABLE:
  714. case ECC_ENABLE:
  715. break;
  716. default:
  717. debug("%s: ecc value %d invalid.\n", dev->name, ecc);
  718. return -EINVAL;
  719. }
  720. registered_dram = dev_read_u32_default(dev, "registered_dram", 0);
  721. switch (registered_dram) {
  722. case RD_DISABLE:
  723. case RD_ENABLE:
  724. break;
  725. default:
  726. debug("%s: registered_dram value %d invalid.\n",
  727. dev->name, registered_dram);
  728. return -EINVAL;
  729. }
  730. sdram_type = dev_read_u32_default(dev, "sdram_type", 0);
  731. switch (sdram_type) {
  732. case TYPE_DDR1:
  733. case TYPE_DDR2:
  734. break;
  735. default:
  736. debug("%s: sdram_type value %d invalid.\n",
  737. dev->name, sdram_type);
  738. return -EINVAL;
  739. }
  740. dynamic_power_management =
  741. dev_read_u32_default(dev, "dynamic_power_management", 0);
  742. switch (dynamic_power_management) {
  743. case DYN_PWR_DISABLE:
  744. case DYN_PWR_ENABLE:
  745. break;
  746. default:
  747. debug("%s: dynamic_power_management value %d invalid.\n",
  748. dev->name, dynamic_power_management);
  749. return -EINVAL;
  750. }
  751. databus_width = dev_read_u32_default(dev, "databus_width", 0);
  752. switch (databus_width) {
  753. case DATA_BUS_WIDTH_16:
  754. case DATA_BUS_WIDTH_32:
  755. break;
  756. default:
  757. debug("%s: databus_width value %d invalid.\n",
  758. dev->name, databus_width);
  759. return -EINVAL;
  760. }
  761. nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0);
  762. switch (nc_auto_precharge) {
  763. case NCAP_DISABLE:
  764. case NCAP_ENABLE:
  765. break;
  766. default:
  767. debug("%s: nc_auto_precharge value %d invalid.\n",
  768. dev->name, nc_auto_precharge);
  769. return -EINVAL;
  770. }
  771. timing_2t = dev_read_u32_default(dev, "timing_2t", 0);
  772. switch (timing_2t) {
  773. case TIMING_1T:
  774. case TIMING_2T:
  775. break;
  776. default:
  777. debug("%s: timing_2t value %d invalid.\n",
  778. dev->name, timing_2t);
  779. return -EINVAL;
  780. }
  781. bank_interleaving_ctrl =
  782. dev_read_u32_default(dev, "bank_interleaving_ctrl", 0);
  783. switch (bank_interleaving_ctrl) {
  784. case INTERLEAVE_NONE:
  785. case INTERLEAVE_1_AND_2:
  786. break;
  787. default:
  788. debug("%s: bank_interleaving_ctrl value %d invalid.\n",
  789. dev->name, bank_interleaving_ctrl);
  790. return -EINVAL;
  791. }
  792. precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0);
  793. switch (precharge_bit_8) {
  794. case PRECHARGE_MA_10:
  795. case PRECHARGE_MA_8:
  796. break;
  797. default:
  798. debug("%s: precharge_bit_8 value %d invalid.\n",
  799. dev->name, precharge_bit_8);
  800. return -EINVAL;
  801. }
  802. half_strength = dev_read_u32_default(dev, "half_strength", 0);
  803. switch (half_strength) {
  804. case STRENGTH_FULL:
  805. case STRENGTH_HALF:
  806. break;
  807. default:
  808. debug("%s: half_strength value %d invalid.\n",
  809. dev->name, half_strength);
  810. return -EINVAL;
  811. }
  812. bypass_initialization =
  813. dev_read_u32_default(dev, "bypass_initialization", 0);
  814. switch (bypass_initialization) {
  815. case INITIALIZATION_DONT_BYPASS:
  816. case INITIALIZATION_BYPASS:
  817. break;
  818. default:
  819. debug("%s: bypass_initialization value %d invalid.\n",
  820. dev->name, bypass_initialization);
  821. return -EINVAL;
  822. }
  823. sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
  824. ecc << SDRAM_CFG_ECC_EN_SHIFT |
  825. registered_dram << SDRAM_CFG_RD_EN_SHIFT |
  826. sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT |
  827. dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT |
  828. databus_width << SDRAM_CFG_DBW_SHIFT |
  829. nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT |
  830. timing_2t << SDRAM_CFG_2T_EN_SHIFT |
  831. bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT |
  832. precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT |
  833. half_strength << SDRAM_CFG_HSE_SHIFT |
  834. bypass_initialization << SDRAM_CFG_BI_SHIFT;
  835. out_be32(&im->ddr.sdram_cfg, sdram_cfg);
  836. force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0);
  837. switch (force_self_refresh) {
  838. case MODE_NORMAL:
  839. case MODE_REFRESH:
  840. break;
  841. default:
  842. debug("%s: force_self_refresh value %d invalid.\n",
  843. dev->name, force_self_refresh);
  844. return -EINVAL;
  845. }
  846. dll_reset = dev_read_u32_default(dev, "dll_reset", 0);
  847. switch (dll_reset) {
  848. case DLL_RESET_ENABLE:
  849. case DLL_RESET_DISABLE:
  850. break;
  851. default:
  852. debug("%s: dll_reset value %d invalid.\n",
  853. dev->name, dll_reset);
  854. return -EINVAL;
  855. }
  856. dqs_config = dev_read_u32_default(dev, "dqs_config", 0);
  857. switch (dqs_config) {
  858. case DQS_TRUE:
  859. break;
  860. default:
  861. debug("%s: dqs_config value %d invalid.\n",
  862. dev->name, dqs_config);
  863. return -EINVAL;
  864. }
  865. odt_config = dev_read_u32_default(dev, "odt_config", 0);
  866. switch (odt_config) {
  867. case ODT_ASSERT_NEVER:
  868. case ODT_ASSERT_WRITES:
  869. case ODT_ASSERT_READS:
  870. case ODT_ASSERT_ALWAYS:
  871. break;
  872. default:
  873. debug("%s: odt_config value %d invalid.\n",
  874. dev->name, odt_config);
  875. return -EINVAL;
  876. }
  877. posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0);
  878. if (posted_refreshes > 8 || posted_refreshes == 0) {
  879. debug("%s: posted_refreshes value %d invalid.\n",
  880. dev->name, posted_refreshes);
  881. return -EINVAL;
  882. }
  883. sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT |
  884. dll_reset << SDRAM_CFG2_DLL_RST_DIS |
  885. dqs_config << SDRAM_CFG2_DQS_CFG |
  886. odt_config << SDRAM_CFG2_ODT_CFG |
  887. posted_refreshes << SDRAM_CFG2_NUM_PR;
  888. out_be32(&im->ddr.sdram_cfg2, sdram_cfg2);
  889. sdmode = dev_read_u32_default(dev, "sdmode", 0);
  890. if (sdmode > 0xFFFF) {
  891. debug("%s: sdmode value %d invalid.\n",
  892. dev->name, sdmode);
  893. return -EINVAL;
  894. }
  895. esdmode = dev_read_u32_default(dev, "esdmode", 0);
  896. if (esdmode > 0xFFFF) {
  897. debug("%s: esdmode value %d invalid.\n", dev->name, esdmode);
  898. return -EINVAL;
  899. }
  900. sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT |
  901. esdmode << SDRAM_MODE_ESD_SHIFT;
  902. out_be32(&im->ddr.sdram_mode, sdram_mode);
  903. esdmode2 = dev_read_u32_default(dev, "esdmode2", 0);
  904. if (esdmode2 > 0xFFFF) {
  905. debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2);
  906. return -EINVAL;
  907. }
  908. esdmode3 = dev_read_u32_default(dev, "esdmode3", 0);
  909. if (esdmode3 > 0xFFFF) {
  910. debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3);
  911. return -EINVAL;
  912. }
  913. sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT |
  914. esdmode3 << SDRAM_MODE2_ESD3_SHIFT;
  915. out_be32(&im->ddr.sdram_mode2, sdram_mode2);
  916. refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0);
  917. if (refresh_interval > 0xFFFF) {
  918. debug("%s: refresh_interval value %d invalid.\n",
  919. dev->name, refresh_interval);
  920. return -EINVAL;
  921. }
  922. precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0);
  923. if (precharge_interval > 0x3FFF) {
  924. debug("%s: precharge_interval value %d invalid.\n",
  925. dev->name, precharge_interval);
  926. return -EINVAL;
  927. }
  928. sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT |
  929. precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT;
  930. out_be32(&im->ddr.sdram_interval, sdram_interval);
  931. sync();
  932. /* Enable DDR controller */
  933. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  934. sync();
  935. dev_for_each_subnode(subnode, dev) {
  936. u32 val[3];
  937. u32 addr, size;
  938. /* CS, map address, size -> three values */
  939. ofnode_read_u32_array(subnode, "reg", val, 3);
  940. addr = val[1];
  941. size = val[2];
  942. priv->total_size += get_ram_size((long int *)addr, size);
  943. };
  944. gd->ram_size = priv->total_size;
  945. return 0;
  946. }
  947. static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info)
  948. {
  949. /* TODO(mario.six@gdsys.cc): Implement */
  950. return 0;
  951. }
  952. static struct ram_ops mpc83xx_sdram_ops = {
  953. .get_info = mpc83xx_sdram_get_info,
  954. };
  955. static const struct udevice_id mpc83xx_sdram_ids[] = {
  956. { .compatible = "fsl,mpc83xx-mem-controller" },
  957. { /* sentinel */ }
  958. };
  959. U_BOOT_DRIVER(mpc83xx_sdram) = {
  960. .name = "mpc83xx_sdram",
  961. .id = UCLASS_RAM,
  962. .of_match = mpc83xx_sdram_ids,
  963. .ops = &mpc83xx_sdram_ops,
  964. .of_to_plat = mpc83xx_sdram_of_to_plat,
  965. .probe = mpc83xx_sdram_probe,
  966. .priv_auto = sizeof(struct mpc83xx_sdram_priv),
  967. };