uec_phy.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Shlomi Gridish
  6. *
  7. * Description: UCC GETH Driver -- PHY handling
  8. * Driver for UEC on QE
  9. * Based on 8260_io/fcc_enet.c
  10. */
  11. #include <common.h>
  12. #include <net.h>
  13. #include <malloc.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include <linux/immap_qe.h>
  17. #include <asm/io.h>
  18. #include "uccf.h"
  19. #include "uec.h"
  20. #include "uec_phy.h"
  21. #include "miiphy.h"
  22. #include <fsl_qe.h>
  23. #include <phy.h>
  24. #if !defined(CONFIG_DM_ETH)
  25. #define ugphy_printk(format, arg...) \
  26. printf(format "\n", ## arg)
  27. #define ugphy_dbg(format, arg...) \
  28. ugphy_printk(format, ## arg)
  29. #define ugphy_err(format, arg...) \
  30. ugphy_printk(format, ## arg)
  31. #define ugphy_info(format, arg...) \
  32. ugphy_printk(format, ## arg)
  33. #define ugphy_warn(format, arg...) \
  34. ugphy_printk(format, ## arg)
  35. #ifdef UEC_VERBOSE_DEBUG
  36. #define ugphy_vdbg ugphy_dbg
  37. #else
  38. #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
  39. #endif /* UEC_VERBOSE_DEBUG */
  40. /*
  41. * --------------------------------------------------------------------
  42. * Fixed PHY (PHY-less) support for Ethernet Ports.
  43. *
  44. * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
  45. *--------------------------------------------------------------------
  46. *
  47. * Some boards do not have a PHY for each ethernet port. These ports are known
  48. * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
  49. * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
  50. * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
  51. * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
  52. * speed and duplex should be for the port.
  53. *
  54. * Example board header configuration file:
  55. * #define CONFIG_FIXED_PHY 0xFFFFFFFF
  56. * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
  57. *
  58. * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
  59. * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
  60. * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
  61. * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
  62. *
  63. * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
  64. * {name, speed, duplex},
  65. *
  66. * #define CONFIG_SYS_FIXED_PHY_PORTS \
  67. * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
  68. * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
  69. */
  70. #ifndef CONFIG_FIXED_PHY
  71. #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
  72. #endif
  73. #ifndef CONFIG_SYS_FIXED_PHY_PORTS
  74. #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
  75. #endif
  76. struct fixed_phy_port {
  77. char name[16]; /* ethernet port name */
  78. unsigned int speed; /* specified speed 10,100 or 1000 */
  79. unsigned int duplex; /* specified duplex FULL or HALF */
  80. };
  81. static const struct fixed_phy_port fixed_phy_port[] = {
  82. CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
  83. };
  84. /*
  85. * -------------------------------------------------------------------
  86. * BitBang MII support for ethernet ports
  87. *
  88. * Based from MPC8560ADS implementation
  89. *--------------------------------------------------------------------
  90. *
  91. * Example board header file to define bitbang ethernet ports:
  92. *
  93. * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
  94. * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
  95. */
  96. #ifndef CONFIG_SYS_BITBANG_PHY_PORTS
  97. #define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
  98. #endif
  99. #if defined(CONFIG_BITBANGMII)
  100. static const char * const bitbang_phy_port[] = {
  101. CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
  102. };
  103. #endif /* CONFIG_BITBANGMII */
  104. static void config_genmii_advert(struct uec_mii_info *mii_info);
  105. static void genmii_setup_forced(struct uec_mii_info *mii_info);
  106. static void genmii_restart_aneg(struct uec_mii_info *mii_info);
  107. static int gbit_config_aneg(struct uec_mii_info *mii_info);
  108. static int genmii_config_aneg(struct uec_mii_info *mii_info);
  109. static int genmii_update_link(struct uec_mii_info *mii_info);
  110. static int genmii_read_status(struct uec_mii_info *mii_info);
  111. static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
  112. static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum,
  113. u16 val);
  114. /*
  115. * Write value to the PHY for this device to the register at regnum,
  116. * waiting until the write is done before it returns. All PHY
  117. * configuration has to be done through the TSEC1 MIIM regs
  118. */
  119. void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
  120. int value)
  121. {
  122. struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
  123. uec_mii_t *ug_regs;
  124. enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
  125. u32 tmp_reg;
  126. #if defined(CONFIG_BITBANGMII)
  127. u32 i = 0;
  128. for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
  129. if (strncmp(dev->name, bitbang_phy_port[i],
  130. sizeof(dev->name)) == 0) {
  131. (void)bb_miiphy_write(NULL, mii_id, regnum, value);
  132. return;
  133. }
  134. }
  135. #endif /* CONFIG_BITBANGMII */
  136. ug_regs = ugeth->uec_mii_regs;
  137. /* Stop the MII management read cycle */
  138. out_be32 (&ug_regs->miimcom, 0);
  139. /* Setting up the MII Management Address Register */
  140. tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  141. out_be32 (&ug_regs->miimadd, tmp_reg);
  142. /* Setting up the MII Management Control Register with the value */
  143. out_be32 (&ug_regs->miimcon, (u32)value);
  144. sync();
  145. /* Wait till MII management write is complete */
  146. while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY)
  147. ;
  148. }
  149. /*
  150. * Reads from register regnum in the PHY for device dev,
  151. * returning the value. Clears miimcom first. All PHY
  152. * configuration has to be done through the TSEC1 MIIM regs
  153. */
  154. int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
  155. {
  156. struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
  157. uec_mii_t *ug_regs;
  158. enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
  159. u32 tmp_reg;
  160. u16 value;
  161. #if defined(CONFIG_BITBANGMII)
  162. u32 i = 0;
  163. for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
  164. if (strncmp(dev->name, bitbang_phy_port[i],
  165. sizeof(dev->name)) == 0) {
  166. (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
  167. return value;
  168. }
  169. }
  170. #endif /* CONFIG_BITBANGMII */
  171. ug_regs = ugeth->uec_mii_regs;
  172. /* Setting up the MII Management Address Register */
  173. tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  174. out_be32 (&ug_regs->miimadd, tmp_reg);
  175. /* clear MII management command cycle */
  176. out_be32 (&ug_regs->miimcom, 0);
  177. sync();
  178. /* Perform an MII management read cycle */
  179. out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
  180. /* Wait till MII management write is complete */
  181. while ((in_be32 (&ug_regs->miimind)) &
  182. (MIIMIND_NOT_VALID | MIIMIND_BUSY))
  183. ;
  184. /* Read MII management status */
  185. value = (u16)in_be32 (&ug_regs->miimstat);
  186. if (value == 0xffff)
  187. ugphy_vdbg
  188. ("read wrong value : mii_id %d,mii_reg %d, base %08x",
  189. mii_id, mii_reg, (u32)&ug_regs->miimcfg);
  190. return value;
  191. }
  192. void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
  193. {
  194. if (mii_info->phyinfo->ack_interrupt)
  195. mii_info->phyinfo->ack_interrupt(mii_info);
  196. }
  197. void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
  198. u32 interrupts)
  199. {
  200. mii_info->interrupts = interrupts;
  201. if (mii_info->phyinfo->config_intr)
  202. mii_info->phyinfo->config_intr(mii_info);
  203. }
  204. /* Writes MII_ADVERTISE with the appropriate values, after
  205. * sanitizing advertise to make sure only supported features
  206. * are advertised
  207. */
  208. static void config_genmii_advert(struct uec_mii_info *mii_info)
  209. {
  210. u32 advertise;
  211. u16 adv;
  212. /* Only allow advertising what this PHY supports */
  213. mii_info->advertising &= mii_info->phyinfo->features;
  214. advertise = mii_info->advertising;
  215. /* Setup standard advertisement */
  216. adv = uec_phy_read(mii_info, MII_ADVERTISE);
  217. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  218. if (advertise & ADVERTISED_10baseT_Half)
  219. adv |= ADVERTISE_10HALF;
  220. if (advertise & ADVERTISED_10baseT_Full)
  221. adv |= ADVERTISE_10FULL;
  222. if (advertise & ADVERTISED_100baseT_Half)
  223. adv |= ADVERTISE_100HALF;
  224. if (advertise & ADVERTISED_100baseT_Full)
  225. adv |= ADVERTISE_100FULL;
  226. uec_phy_write(mii_info, MII_ADVERTISE, adv);
  227. }
  228. static void genmii_setup_forced(struct uec_mii_info *mii_info)
  229. {
  230. u16 ctrl;
  231. u32 features = mii_info->phyinfo->features;
  232. ctrl = uec_phy_read(mii_info, MII_BMCR);
  233. ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
  234. BMCR_SPEED1000 | BMCR_ANENABLE);
  235. ctrl |= BMCR_RESET;
  236. switch (mii_info->speed) {
  237. case SPEED_1000:
  238. if (features & (SUPPORTED_1000baseT_Half
  239. | SUPPORTED_1000baseT_Full)) {
  240. ctrl |= BMCR_SPEED1000;
  241. break;
  242. }
  243. mii_info->speed = SPEED_100;
  244. case SPEED_100:
  245. if (features & (SUPPORTED_100baseT_Half
  246. | SUPPORTED_100baseT_Full)) {
  247. ctrl |= BMCR_SPEED100;
  248. break;
  249. }
  250. mii_info->speed = SPEED_10;
  251. case SPEED_10:
  252. if (features & (SUPPORTED_10baseT_Half
  253. | SUPPORTED_10baseT_Full))
  254. break;
  255. default: /* Unsupported speed! */
  256. ugphy_err("%s: Bad speed!", mii_info->dev->name);
  257. break;
  258. }
  259. uec_phy_write(mii_info, MII_BMCR, ctrl);
  260. }
  261. /* Enable and Restart Autonegotiation */
  262. static void genmii_restart_aneg(struct uec_mii_info *mii_info)
  263. {
  264. u16 ctl;
  265. ctl = uec_phy_read(mii_info, MII_BMCR);
  266. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  267. uec_phy_write(mii_info, MII_BMCR, ctl);
  268. }
  269. static int gbit_config_aneg(struct uec_mii_info *mii_info)
  270. {
  271. u16 adv;
  272. u32 advertise;
  273. if (mii_info->autoneg) {
  274. /* Configure the ADVERTISE register */
  275. config_genmii_advert(mii_info);
  276. advertise = mii_info->advertising;
  277. adv = uec_phy_read(mii_info, MII_CTRL1000);
  278. adv &= ~(ADVERTISE_1000FULL |
  279. ADVERTISE_1000HALF);
  280. if (advertise & SUPPORTED_1000baseT_Half)
  281. adv |= ADVERTISE_1000HALF;
  282. if (advertise & SUPPORTED_1000baseT_Full)
  283. adv |= ADVERTISE_1000FULL;
  284. uec_phy_write(mii_info, MII_CTRL1000, adv);
  285. /* Start/Restart aneg */
  286. genmii_restart_aneg(mii_info);
  287. } else {
  288. genmii_setup_forced(mii_info);
  289. }
  290. return 0;
  291. }
  292. static int marvell_config_aneg(struct uec_mii_info *mii_info)
  293. {
  294. /*
  295. * The Marvell PHY has an errata which requires
  296. * that certain registers get written in order
  297. * to restart autonegotiation
  298. */
  299. uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
  300. uec_phy_write(mii_info, 0x1d, 0x1f);
  301. uec_phy_write(mii_info, 0x1e, 0x200c);
  302. uec_phy_write(mii_info, 0x1d, 0x5);
  303. uec_phy_write(mii_info, 0x1e, 0);
  304. uec_phy_write(mii_info, 0x1e, 0x100);
  305. gbit_config_aneg(mii_info);
  306. return 0;
  307. }
  308. static int genmii_config_aneg(struct uec_mii_info *mii_info)
  309. {
  310. if (mii_info->autoneg) {
  311. /*
  312. * Speed up the common case, if link is already up, speed and
  313. * duplex match, skip auto neg as it already matches
  314. */
  315. if (!genmii_read_status(mii_info) && mii_info->link)
  316. if (mii_info->duplex == DUPLEX_FULL &&
  317. mii_info->speed == SPEED_100)
  318. if (mii_info->advertising &
  319. ADVERTISED_100baseT_Full)
  320. return 0;
  321. config_genmii_advert(mii_info);
  322. genmii_restart_aneg(mii_info);
  323. } else {
  324. genmii_setup_forced(mii_info);
  325. }
  326. return 0;
  327. }
  328. static int genmii_update_link(struct uec_mii_info *mii_info)
  329. {
  330. u16 status;
  331. /* Status is read once to clear old link state */
  332. uec_phy_read(mii_info, MII_BMSR);
  333. /*
  334. * Wait if the link is up, and autonegotiation is in progress
  335. * (ie - we're capable and it's not done)
  336. */
  337. status = uec_phy_read(mii_info, MII_BMSR);
  338. if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) &&
  339. !(status & BMSR_ANEGCOMPLETE)) {
  340. int i = 0;
  341. while (!(status & BMSR_ANEGCOMPLETE)) {
  342. /*
  343. * Timeout reached ?
  344. */
  345. if (i > UGETH_AN_TIMEOUT) {
  346. mii_info->link = 0;
  347. return 0;
  348. }
  349. i++;
  350. udelay(1000); /* 1 ms */
  351. status = uec_phy_read(mii_info, MII_BMSR);
  352. }
  353. mii_info->link = 1;
  354. } else {
  355. if (status & BMSR_LSTATUS)
  356. mii_info->link = 1;
  357. else
  358. mii_info->link = 0;
  359. }
  360. return 0;
  361. }
  362. static int genmii_read_status(struct uec_mii_info *mii_info)
  363. {
  364. u16 status;
  365. int err;
  366. /* Update the link, but return if there was an error */
  367. err = genmii_update_link(mii_info);
  368. if (err)
  369. return err;
  370. if (mii_info->autoneg) {
  371. status = uec_phy_read(mii_info, MII_STAT1000);
  372. if (status & (LPA_1000FULL | LPA_1000HALF)) {
  373. mii_info->speed = SPEED_1000;
  374. if (status & LPA_1000FULL)
  375. mii_info->duplex = DUPLEX_FULL;
  376. else
  377. mii_info->duplex = DUPLEX_HALF;
  378. } else {
  379. status = uec_phy_read(mii_info, MII_LPA);
  380. if (status & (LPA_10FULL | LPA_100FULL))
  381. mii_info->duplex = DUPLEX_FULL;
  382. else
  383. mii_info->duplex = DUPLEX_HALF;
  384. if (status & (LPA_100FULL | LPA_100HALF))
  385. mii_info->speed = SPEED_100;
  386. else
  387. mii_info->speed = SPEED_10;
  388. }
  389. mii_info->pause = 0;
  390. }
  391. /* On non-aneg, we assume what we put in BMCR is the speed,
  392. * though magic-aneg shouldn't prevent this case from occurring
  393. */
  394. return 0;
  395. }
  396. static int bcm_init(struct uec_mii_info *mii_info)
  397. {
  398. struct eth_device *edev = mii_info->dev;
  399. struct uec_priv *uec = edev->priv;
  400. gbit_config_aneg(mii_info);
  401. if (uec->uec_info->enet_interface_type ==
  402. PHY_INTERFACE_MODE_RGMII_RXID &&
  403. uec->uec_info->speed == SPEED_1000) {
  404. u16 val;
  405. int cnt = 50;
  406. /* Wait for aneg to complete. */
  407. do
  408. val = uec_phy_read(mii_info, MII_BMSR);
  409. while (--cnt && !(val & BMSR_ANEGCOMPLETE));
  410. /* Set RDX clk delay. */
  411. uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
  412. val = uec_phy_read(mii_info, 0x18);
  413. /* Set RDX-RXC skew. */
  414. val |= (1 << 8);
  415. val |= (7 | (7 << 12));
  416. /* Write bits 14:0. */
  417. val |= (1 << 15);
  418. uec_phy_write(mii_info, 0x18, val);
  419. }
  420. return 0;
  421. }
  422. static int uec_marvell_init(struct uec_mii_info *mii_info)
  423. {
  424. struct eth_device *edev = mii_info->dev;
  425. struct uec_priv *uec = edev->priv;
  426. phy_interface_t iface = uec->uec_info->enet_interface_type;
  427. int speed = uec->uec_info->speed;
  428. if (speed == SPEED_1000 &&
  429. (iface == PHY_INTERFACE_MODE_RGMII_ID ||
  430. iface == PHY_INTERFACE_MODE_RGMII_RXID ||
  431. iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  432. int temp;
  433. temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
  434. if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
  435. temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
  436. } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
  437. temp &= ~MII_M1111_TX_DELAY;
  438. temp |= MII_M1111_RX_DELAY;
  439. } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
  440. temp &= ~MII_M1111_RX_DELAY;
  441. temp |= MII_M1111_TX_DELAY;
  442. }
  443. uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
  444. temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
  445. temp &= ~MII_M1111_HWCFG_MODE_MASK;
  446. temp |= MII_M1111_HWCFG_MODE_RGMII;
  447. uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
  448. uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
  449. }
  450. return 0;
  451. }
  452. static int marvell_read_status(struct uec_mii_info *mii_info)
  453. {
  454. u16 status;
  455. int err;
  456. /* Update the link, but return if there was an error */
  457. err = genmii_update_link(mii_info);
  458. if (err)
  459. return err;
  460. /*
  461. * If the link is up, read the speed and duplex
  462. * If we aren't autonegotiating, assume speeds
  463. * are as set
  464. */
  465. if (mii_info->autoneg && mii_info->link) {
  466. int speed;
  467. status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
  468. /* Get the duplexity */
  469. if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
  470. mii_info->duplex = DUPLEX_FULL;
  471. else
  472. mii_info->duplex = DUPLEX_HALF;
  473. /* Get the speed */
  474. speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
  475. switch (speed) {
  476. case MII_M1011_PHY_SPEC_STATUS_1000:
  477. mii_info->speed = SPEED_1000;
  478. break;
  479. case MII_M1011_PHY_SPEC_STATUS_100:
  480. mii_info->speed = SPEED_100;
  481. break;
  482. default:
  483. mii_info->speed = SPEED_10;
  484. break;
  485. }
  486. mii_info->pause = 0;
  487. }
  488. return 0;
  489. }
  490. static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
  491. {
  492. /* Clear the interrupts by reading the reg */
  493. uec_phy_read(mii_info, MII_M1011_IEVENT);
  494. return 0;
  495. }
  496. static int marvell_config_intr(struct uec_mii_info *mii_info)
  497. {
  498. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  499. uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  500. else
  501. uec_phy_write(mii_info, MII_M1011_IMASK,
  502. MII_M1011_IMASK_CLEAR);
  503. return 0;
  504. }
  505. static int dm9161_init(struct uec_mii_info *mii_info)
  506. {
  507. /* Reset the PHY */
  508. uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
  509. BMCR_RESET);
  510. /* PHY and MAC connect */
  511. uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
  512. ~BMCR_ISOLATE);
  513. uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
  514. config_genmii_advert(mii_info);
  515. /* Start/restart aneg */
  516. genmii_config_aneg(mii_info);
  517. return 0;
  518. }
  519. static int dm9161_config_aneg(struct uec_mii_info *mii_info)
  520. {
  521. return 0;
  522. }
  523. static int dm9161_read_status(struct uec_mii_info *mii_info)
  524. {
  525. u16 status;
  526. int err;
  527. /* Update the link, but return if there was an error */
  528. err = genmii_update_link(mii_info);
  529. if (err)
  530. return err;
  531. /*
  532. * If the link is up, read the speed and duplex
  533. * If we aren't autonegotiating assume speeds are as set
  534. */
  535. if (mii_info->autoneg && mii_info->link) {
  536. status = uec_phy_read(mii_info, MII_DM9161_SCSR);
  537. if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
  538. mii_info->speed = SPEED_100;
  539. else
  540. mii_info->speed = SPEED_10;
  541. if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
  542. mii_info->duplex = DUPLEX_FULL;
  543. else
  544. mii_info->duplex = DUPLEX_HALF;
  545. }
  546. return 0;
  547. }
  548. static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
  549. {
  550. /* Clear the interrupt by reading the reg */
  551. uec_phy_read(mii_info, MII_DM9161_INTR);
  552. return 0;
  553. }
  554. static int dm9161_config_intr(struct uec_mii_info *mii_info)
  555. {
  556. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  557. uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
  558. else
  559. uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
  560. return 0;
  561. }
  562. static void dm9161_close(struct uec_mii_info *mii_info)
  563. {
  564. }
  565. static int fixed_phy_aneg(struct uec_mii_info *mii_info)
  566. {
  567. mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
  568. return 0;
  569. }
  570. static int fixed_phy_read_status(struct uec_mii_info *mii_info)
  571. {
  572. int i = 0;
  573. for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
  574. if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
  575. strlen(mii_info->dev->name)) == 0) {
  576. mii_info->speed = fixed_phy_port[i].speed;
  577. mii_info->duplex = fixed_phy_port[i].duplex;
  578. mii_info->link = 1; /* Link is always UP */
  579. mii_info->pause = 0;
  580. break;
  581. }
  582. }
  583. return 0;
  584. }
  585. static int smsc_config_aneg(struct uec_mii_info *mii_info)
  586. {
  587. return 0;
  588. }
  589. static int smsc_read_status(struct uec_mii_info *mii_info)
  590. {
  591. u16 status;
  592. int err;
  593. /* Update the link, but return if there was an error */
  594. err = genmii_update_link(mii_info);
  595. if (err)
  596. return err;
  597. /*
  598. * If the link is up, read the speed and duplex
  599. * If we aren't autonegotiating, assume speeds
  600. * are as set
  601. */
  602. if (mii_info->autoneg && mii_info->link) {
  603. int val;
  604. status = uec_phy_read(mii_info, 0x1f);
  605. val = (status & 0x1c) >> 2;
  606. switch (val) {
  607. case 1:
  608. mii_info->duplex = DUPLEX_HALF;
  609. mii_info->speed = SPEED_10;
  610. break;
  611. case 5:
  612. mii_info->duplex = DUPLEX_FULL;
  613. mii_info->speed = SPEED_10;
  614. break;
  615. case 2:
  616. mii_info->duplex = DUPLEX_HALF;
  617. mii_info->speed = SPEED_100;
  618. break;
  619. case 6:
  620. mii_info->duplex = DUPLEX_FULL;
  621. mii_info->speed = SPEED_100;
  622. break;
  623. }
  624. mii_info->pause = 0;
  625. }
  626. return 0;
  627. }
  628. static struct phy_info phy_info_dm9161 = {
  629. .phy_id = 0x0181b880,
  630. .phy_id_mask = 0x0ffffff0,
  631. .name = "Davicom DM9161E",
  632. .init = dm9161_init,
  633. .config_aneg = dm9161_config_aneg,
  634. .read_status = dm9161_read_status,
  635. .close = dm9161_close,
  636. };
  637. static struct phy_info phy_info_dm9161a = {
  638. .phy_id = 0x0181b8a0,
  639. .phy_id_mask = 0x0ffffff0,
  640. .name = "Davicom DM9161A",
  641. .features = MII_BASIC_FEATURES,
  642. .init = dm9161_init,
  643. .config_aneg = dm9161_config_aneg,
  644. .read_status = dm9161_read_status,
  645. .ack_interrupt = dm9161_ack_interrupt,
  646. .config_intr = dm9161_config_intr,
  647. .close = dm9161_close,
  648. };
  649. static struct phy_info phy_info_marvell = {
  650. .phy_id = 0x01410c00,
  651. .phy_id_mask = 0xffffff00,
  652. .name = "Marvell 88E11x1",
  653. .features = MII_GBIT_FEATURES,
  654. .init = &uec_marvell_init,
  655. .config_aneg = &marvell_config_aneg,
  656. .read_status = &marvell_read_status,
  657. .ack_interrupt = &marvell_ack_interrupt,
  658. .config_intr = &marvell_config_intr,
  659. };
  660. static struct phy_info phy_info_bcm5481 = {
  661. .phy_id = 0x0143bca0,
  662. .phy_id_mask = 0xffffff0,
  663. .name = "Broadcom 5481",
  664. .features = MII_GBIT_FEATURES,
  665. .read_status = genmii_read_status,
  666. .init = bcm_init,
  667. };
  668. static struct phy_info phy_info_fixedphy = {
  669. .phy_id = CONFIG_FIXED_PHY,
  670. .phy_id_mask = CONFIG_FIXED_PHY,
  671. .name = "Fixed PHY",
  672. .config_aneg = fixed_phy_aneg,
  673. .read_status = fixed_phy_read_status,
  674. };
  675. static struct phy_info phy_info_smsclan8700 = {
  676. .phy_id = 0x0007c0c0,
  677. .phy_id_mask = 0xfffffff0,
  678. .name = "SMSC LAN8700",
  679. .features = MII_BASIC_FEATURES,
  680. .config_aneg = smsc_config_aneg,
  681. .read_status = smsc_read_status,
  682. };
  683. static struct phy_info phy_info_genmii = {
  684. .phy_id = 0x00000000,
  685. .phy_id_mask = 0x00000000,
  686. .name = "Generic MII",
  687. .features = MII_BASIC_FEATURES,
  688. .config_aneg = genmii_config_aneg,
  689. .read_status = genmii_read_status,
  690. };
  691. static struct phy_info *phy_info[] = {
  692. &phy_info_dm9161,
  693. &phy_info_dm9161a,
  694. &phy_info_marvell,
  695. &phy_info_bcm5481,
  696. &phy_info_smsclan8700,
  697. &phy_info_fixedphy,
  698. &phy_info_genmii,
  699. NULL
  700. };
  701. static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
  702. {
  703. return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
  704. }
  705. static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
  706. {
  707. mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
  708. }
  709. /* Use the PHY ID registers to determine what type of PHY is attached
  710. * to device dev. return a struct phy_info structure describing that PHY
  711. */
  712. struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info)
  713. {
  714. u16 phy_reg;
  715. u32 phy_ID;
  716. int i;
  717. struct phy_info *info = NULL;
  718. /* Grab the bits from PHYIR1, and put them in the upper half */
  719. phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
  720. phy_ID = (phy_reg & 0xffff) << 16;
  721. /* Grab the bits from PHYIR2, and put them in the lower half */
  722. phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
  723. phy_ID |= (phy_reg & 0xffff);
  724. /* loop through all the known PHY types, and find one that */
  725. /* matches the ID we read from the PHY. */
  726. for (i = 0; phy_info[i]; i++)
  727. if (phy_info[i]->phy_id ==
  728. (phy_ID & phy_info[i]->phy_id_mask)) {
  729. info = phy_info[i];
  730. break;
  731. }
  732. /* This shouldn't happen, as we have generic PHY support */
  733. if (!info) {
  734. ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
  735. return NULL;
  736. }
  737. ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID);
  738. return info;
  739. }
  740. void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
  741. int speed)
  742. {
  743. struct uec_priv *uec = (struct uec_priv *)dev->priv;
  744. struct uec_mii_info *mii_info;
  745. u16 status;
  746. if (!uec->mii_info) {
  747. printf("%s: the PHY not initialized\n", __func__);
  748. return;
  749. }
  750. mii_info = uec->mii_info;
  751. if (type == PHY_INTERFACE_MODE_RGMII) {
  752. if (speed == SPEED_100) {
  753. uec_phy_write(mii_info, 0x00, 0x9140);
  754. uec_phy_write(mii_info, 0x1d, 0x001f);
  755. uec_phy_write(mii_info, 0x1e, 0x200c);
  756. uec_phy_write(mii_info, 0x1d, 0x0005);
  757. uec_phy_write(mii_info, 0x1e, 0x0000);
  758. uec_phy_write(mii_info, 0x1e, 0x0100);
  759. uec_phy_write(mii_info, 0x09, 0x0e00);
  760. uec_phy_write(mii_info, 0x04, 0x01e1);
  761. uec_phy_write(mii_info, 0x00, 0x9140);
  762. uec_phy_write(mii_info, 0x00, 0x1000);
  763. mdelay(100);
  764. uec_phy_write(mii_info, 0x00, 0x2900);
  765. uec_phy_write(mii_info, 0x14, 0x0cd2);
  766. uec_phy_write(mii_info, 0x00, 0xa100);
  767. uec_phy_write(mii_info, 0x09, 0x0000);
  768. uec_phy_write(mii_info, 0x1b, 0x800b);
  769. uec_phy_write(mii_info, 0x04, 0x05e1);
  770. uec_phy_write(mii_info, 0x00, 0xa100);
  771. uec_phy_write(mii_info, 0x00, 0x2100);
  772. mdelay(1000);
  773. } else if (speed == SPEED_10) {
  774. uec_phy_write(mii_info, 0x14, 0x8e40);
  775. uec_phy_write(mii_info, 0x1b, 0x800b);
  776. uec_phy_write(mii_info, 0x14, 0x0c82);
  777. uec_phy_write(mii_info, 0x00, 0x8100);
  778. mdelay(1000);
  779. }
  780. }
  781. /* handle 88e1111 rev.B2 erratum 5.6 */
  782. if (mii_info->autoneg) {
  783. status = uec_phy_read(mii_info, MII_BMCR);
  784. uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
  785. }
  786. /* now the B2 will correctly report autoneg completion status */
  787. }
  788. void change_phy_interface_mode(struct eth_device *dev,
  789. phy_interface_t type, int speed)
  790. {
  791. #ifdef CONFIG_PHY_MODE_NEED_CHANGE
  792. marvell_phy_interface_mode(dev, type, speed);
  793. #endif
  794. }
  795. #endif