uec.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <net.h>
  10. #include <malloc.h>
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <linux/immap_qe.h>
  15. #include "uccf.h"
  16. #include "uec.h"
  17. #include "uec_phy.h"
  18. #include "miiphy.h"
  19. #include <fsl_qe.h>
  20. #include <phy.h>
  21. #if !defined(CONFIG_DM_ETH)
  22. /* Default UTBIPAR SMI address */
  23. #ifndef CONFIG_UTBIPAR_INIT_TBIPA
  24. #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
  25. #endif
  26. static struct uec_inf uec_info[] = {
  27. #ifdef CONFIG_UEC_ETH1
  28. STD_UEC_INFO(1), /* UEC1 */
  29. #endif
  30. #ifdef CONFIG_UEC_ETH2
  31. STD_UEC_INFO(2), /* UEC2 */
  32. #endif
  33. #ifdef CONFIG_UEC_ETH3
  34. STD_UEC_INFO(3), /* UEC3 */
  35. #endif
  36. #ifdef CONFIG_UEC_ETH4
  37. STD_UEC_INFO(4), /* UEC4 */
  38. #endif
  39. #ifdef CONFIG_UEC_ETH5
  40. STD_UEC_INFO(5), /* UEC5 */
  41. #endif
  42. #ifdef CONFIG_UEC_ETH6
  43. STD_UEC_INFO(6), /* UEC6 */
  44. #endif
  45. #ifdef CONFIG_UEC_ETH7
  46. STD_UEC_INFO(7), /* UEC7 */
  47. #endif
  48. #ifdef CONFIG_UEC_ETH8
  49. STD_UEC_INFO(8), /* UEC8 */
  50. #endif
  51. };
  52. #define MAXCONTROLLERS (8)
  53. static struct eth_device *devlist[MAXCONTROLLERS];
  54. static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
  55. {
  56. uec_t *uec_regs;
  57. u32 maccfg1;
  58. if (!uec) {
  59. printf("%s: uec not initial\n", __func__);
  60. return -EINVAL;
  61. }
  62. uec_regs = uec->uec_regs;
  63. maccfg1 = in_be32(&uec_regs->maccfg1);
  64. if (mode & COMM_DIR_TX) {
  65. maccfg1 |= MACCFG1_ENABLE_TX;
  66. out_be32(&uec_regs->maccfg1, maccfg1);
  67. uec->mac_tx_enabled = 1;
  68. }
  69. if (mode & COMM_DIR_RX) {
  70. maccfg1 |= MACCFG1_ENABLE_RX;
  71. out_be32(&uec_regs->maccfg1, maccfg1);
  72. uec->mac_rx_enabled = 1;
  73. }
  74. return 0;
  75. }
  76. static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
  77. {
  78. uec_t *uec_regs;
  79. u32 maccfg1;
  80. if (!uec) {
  81. printf("%s: uec not initial\n", __func__);
  82. return -EINVAL;
  83. }
  84. uec_regs = uec->uec_regs;
  85. maccfg1 = in_be32(&uec_regs->maccfg1);
  86. if (mode & COMM_DIR_TX) {
  87. maccfg1 &= ~MACCFG1_ENABLE_TX;
  88. out_be32(&uec_regs->maccfg1, maccfg1);
  89. uec->mac_tx_enabled = 0;
  90. }
  91. if (mode & COMM_DIR_RX) {
  92. maccfg1 &= ~MACCFG1_ENABLE_RX;
  93. out_be32(&uec_regs->maccfg1, maccfg1);
  94. uec->mac_rx_enabled = 0;
  95. }
  96. return 0;
  97. }
  98. static int uec_graceful_stop_tx(struct uec_priv *uec)
  99. {
  100. ucc_fast_t *uf_regs;
  101. u32 cecr_subblock;
  102. u32 ucce;
  103. if (!uec || !uec->uccf) {
  104. printf("%s: No handle passed.\n", __func__);
  105. return -EINVAL;
  106. }
  107. uf_regs = uec->uccf->uf_regs;
  108. /* Clear the grace stop event */
  109. out_be32(&uf_regs->ucce, UCCE_GRA);
  110. /* Issue host command */
  111. cecr_subblock =
  112. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  113. qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
  114. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  115. /* Wait for command to complete */
  116. do {
  117. ucce = in_be32(&uf_regs->ucce);
  118. } while (!(ucce & UCCE_GRA));
  119. uec->grace_stopped_tx = 1;
  120. return 0;
  121. }
  122. static int uec_graceful_stop_rx(struct uec_priv *uec)
  123. {
  124. u32 cecr_subblock;
  125. u8 ack;
  126. if (!uec) {
  127. printf("%s: No handle passed.\n", __func__);
  128. return -EINVAL;
  129. }
  130. if (!uec->p_rx_glbl_pram) {
  131. printf("%s: No init rx global parameter\n", __func__);
  132. return -EINVAL;
  133. }
  134. /* Clear acknowledge bit */
  135. ack = uec->p_rx_glbl_pram->rxgstpack;
  136. ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
  137. uec->p_rx_glbl_pram->rxgstpack = ack;
  138. /* Keep issuing cmd and checking ack bit until it is asserted */
  139. do {
  140. /* Issue host command */
  141. cecr_subblock =
  142. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  143. qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
  144. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  145. ack = uec->p_rx_glbl_pram->rxgstpack;
  146. } while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
  147. uec->grace_stopped_rx = 1;
  148. return 0;
  149. }
  150. static int uec_restart_tx(struct uec_priv *uec)
  151. {
  152. u32 cecr_subblock;
  153. if (!uec || !uec->uec_info) {
  154. printf("%s: No handle passed.\n", __func__);
  155. return -EINVAL;
  156. }
  157. cecr_subblock =
  158. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  159. qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
  160. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  161. uec->grace_stopped_tx = 0;
  162. return 0;
  163. }
  164. static int uec_restart_rx(struct uec_priv *uec)
  165. {
  166. u32 cecr_subblock;
  167. if (!uec || !uec->uec_info) {
  168. printf("%s: No handle passed.\n", __func__);
  169. return -EINVAL;
  170. }
  171. cecr_subblock =
  172. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  173. qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
  174. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  175. uec->grace_stopped_rx = 0;
  176. return 0;
  177. }
  178. static int uec_open(struct uec_priv *uec, comm_dir_e mode)
  179. {
  180. struct ucc_fast_priv *uccf;
  181. if (!uec || !uec->uccf) {
  182. printf("%s: No handle passed.\n", __func__);
  183. return -EINVAL;
  184. }
  185. uccf = uec->uccf;
  186. /* check if the UCC number is in range. */
  187. if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
  188. printf("%s: ucc_num out of range.\n", __func__);
  189. return -EINVAL;
  190. }
  191. /* Enable MAC */
  192. uec_mac_enable(uec, mode);
  193. /* Enable UCC fast */
  194. ucc_fast_enable(uccf, mode);
  195. /* RISC microcode start */
  196. if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
  197. uec_restart_tx(uec);
  198. if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
  199. uec_restart_rx(uec);
  200. return 0;
  201. }
  202. static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
  203. {
  204. if (!uec || !uec->uccf) {
  205. printf("%s: No handle passed.\n", __func__);
  206. return -EINVAL;
  207. }
  208. /* check if the UCC number is in range. */
  209. if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
  210. printf("%s: ucc_num out of range.\n", __func__);
  211. return -EINVAL;
  212. }
  213. /* Stop any transmissions */
  214. if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
  215. uec_graceful_stop_tx(uec);
  216. /* Stop any receptions */
  217. if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
  218. uec_graceful_stop_rx(uec);
  219. /* Disable the UCC fast */
  220. ucc_fast_disable(uec->uccf, mode);
  221. /* Disable the MAC */
  222. uec_mac_disable(uec, mode);
  223. return 0;
  224. }
  225. static int uec_set_mac_duplex(struct uec_priv *uec, int duplex)
  226. {
  227. uec_t *uec_regs;
  228. u32 maccfg2;
  229. if (!uec) {
  230. printf("%s: uec not initial\n", __func__);
  231. return -EINVAL;
  232. }
  233. uec_regs = uec->uec_regs;
  234. if (duplex == DUPLEX_HALF) {
  235. maccfg2 = in_be32(&uec_regs->maccfg2);
  236. maccfg2 &= ~MACCFG2_FDX;
  237. out_be32(&uec_regs->maccfg2, maccfg2);
  238. }
  239. if (duplex == DUPLEX_FULL) {
  240. maccfg2 = in_be32(&uec_regs->maccfg2);
  241. maccfg2 |= MACCFG2_FDX;
  242. out_be32(&uec_regs->maccfg2, maccfg2);
  243. }
  244. return 0;
  245. }
  246. static int uec_set_mac_if_mode(struct uec_priv *uec,
  247. phy_interface_t if_mode, int speed)
  248. {
  249. phy_interface_t enet_if_mode;
  250. uec_t *uec_regs;
  251. u32 upsmr;
  252. u32 maccfg2;
  253. if (!uec) {
  254. printf("%s: uec not initial\n", __func__);
  255. return -EINVAL;
  256. }
  257. uec_regs = uec->uec_regs;
  258. enet_if_mode = if_mode;
  259. maccfg2 = in_be32(&uec_regs->maccfg2);
  260. maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
  261. upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
  262. upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
  263. switch (speed) {
  264. case SPEED_10:
  265. maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
  266. switch (enet_if_mode) {
  267. case PHY_INTERFACE_MODE_MII:
  268. break;
  269. case PHY_INTERFACE_MODE_RGMII:
  270. upsmr |= (UPSMR_RPM | UPSMR_R10M);
  271. break;
  272. case PHY_INTERFACE_MODE_RMII:
  273. upsmr |= (UPSMR_R10M | UPSMR_RMM);
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. break;
  279. case SPEED_100:
  280. maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
  281. switch (enet_if_mode) {
  282. case PHY_INTERFACE_MODE_MII:
  283. break;
  284. case PHY_INTERFACE_MODE_RGMII:
  285. upsmr |= UPSMR_RPM;
  286. break;
  287. case PHY_INTERFACE_MODE_RMII:
  288. upsmr |= UPSMR_RMM;
  289. break;
  290. default:
  291. return -EINVAL;
  292. }
  293. break;
  294. case SPEED_1000:
  295. maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
  296. switch (enet_if_mode) {
  297. case PHY_INTERFACE_MODE_GMII:
  298. break;
  299. case PHY_INTERFACE_MODE_TBI:
  300. upsmr |= UPSMR_TBIM;
  301. break;
  302. case PHY_INTERFACE_MODE_RTBI:
  303. upsmr |= (UPSMR_RPM | UPSMR_TBIM);
  304. break;
  305. case PHY_INTERFACE_MODE_RGMII_RXID:
  306. case PHY_INTERFACE_MODE_RGMII_TXID:
  307. case PHY_INTERFACE_MODE_RGMII_ID:
  308. case PHY_INTERFACE_MODE_RGMII:
  309. upsmr |= UPSMR_RPM;
  310. break;
  311. case PHY_INTERFACE_MODE_SGMII:
  312. upsmr |= UPSMR_SGMM;
  313. break;
  314. default:
  315. return -EINVAL;
  316. }
  317. break;
  318. default:
  319. return -EINVAL;
  320. }
  321. out_be32(&uec_regs->maccfg2, maccfg2);
  322. out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
  323. return 0;
  324. }
  325. static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
  326. {
  327. uint timeout = 0x1000;
  328. u32 miimcfg = 0;
  329. miimcfg = in_be32(&uec_mii_regs->miimcfg);
  330. miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
  331. out_be32(&uec_mii_regs->miimcfg, miimcfg);
  332. /* Wait until the bus is free */
  333. while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--)
  334. ;
  335. if (timeout <= 0) {
  336. printf("%s: The MII Bus is stuck!", __func__);
  337. return -ETIMEDOUT;
  338. }
  339. return 0;
  340. }
  341. static int init_phy(struct eth_device *dev)
  342. {
  343. struct uec_priv *uec;
  344. uec_mii_t *umii_regs;
  345. struct uec_mii_info *mii_info;
  346. struct phy_info *curphy;
  347. int err;
  348. uec = (struct uec_priv *)dev->priv;
  349. umii_regs = uec->uec_mii_regs;
  350. uec->oldlink = 0;
  351. uec->oldspeed = 0;
  352. uec->oldduplex = -1;
  353. mii_info = malloc(sizeof(*mii_info));
  354. if (!mii_info) {
  355. printf("%s: Could not allocate mii_info", dev->name);
  356. return -ENOMEM;
  357. }
  358. memset(mii_info, 0, sizeof(*mii_info));
  359. if (uec->uec_info->uf_info.eth_type == GIGA_ETH)
  360. mii_info->speed = SPEED_1000;
  361. else
  362. mii_info->speed = SPEED_100;
  363. mii_info->duplex = DUPLEX_FULL;
  364. mii_info->pause = 0;
  365. mii_info->link = 1;
  366. mii_info->advertising = (ADVERTISED_10baseT_Half |
  367. ADVERTISED_10baseT_Full |
  368. ADVERTISED_100baseT_Half |
  369. ADVERTISED_100baseT_Full |
  370. ADVERTISED_1000baseT_Full);
  371. mii_info->autoneg = 1;
  372. mii_info->mii_id = uec->uec_info->phy_address;
  373. mii_info->dev = dev;
  374. mii_info->mdio_read = &uec_read_phy_reg;
  375. mii_info->mdio_write = &uec_write_phy_reg;
  376. uec->mii_info = mii_info;
  377. qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
  378. if (init_mii_management_configuration(umii_regs)) {
  379. printf("%s: The MII Bus is stuck!", dev->name);
  380. err = -1;
  381. goto bus_fail;
  382. }
  383. /* get info for this PHY */
  384. curphy = uec_get_phy_info(uec->mii_info);
  385. if (!curphy) {
  386. printf("%s: No PHY found", dev->name);
  387. err = -1;
  388. goto no_phy;
  389. }
  390. mii_info->phyinfo = curphy;
  391. /* Run the commands which initialize the PHY */
  392. if (curphy->init) {
  393. err = curphy->init(uec->mii_info);
  394. if (err)
  395. goto phy_init_fail;
  396. }
  397. return 0;
  398. phy_init_fail:
  399. no_phy:
  400. bus_fail:
  401. free(mii_info);
  402. return err;
  403. }
  404. static void adjust_link(struct eth_device *dev)
  405. {
  406. struct uec_priv *uec = (struct uec_priv *)dev->priv;
  407. struct uec_mii_info *mii_info = uec->mii_info;
  408. if (mii_info->link) {
  409. /*
  410. * Now we make sure that we can be in full duplex mode.
  411. * If not, we operate in half-duplex mode.
  412. */
  413. if (mii_info->duplex != uec->oldduplex) {
  414. if (!(mii_info->duplex)) {
  415. uec_set_mac_duplex(uec, DUPLEX_HALF);
  416. printf("%s: Half Duplex\n", dev->name);
  417. } else {
  418. uec_set_mac_duplex(uec, DUPLEX_FULL);
  419. printf("%s: Full Duplex\n", dev->name);
  420. }
  421. uec->oldduplex = mii_info->duplex;
  422. }
  423. if (mii_info->speed != uec->oldspeed) {
  424. phy_interface_t mode =
  425. uec->uec_info->enet_interface_type;
  426. if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
  427. switch (mii_info->speed) {
  428. case SPEED_1000:
  429. break;
  430. case SPEED_100:
  431. printf("switching to rgmii 100\n");
  432. mode = PHY_INTERFACE_MODE_RGMII;
  433. break;
  434. case SPEED_10:
  435. printf("switching to rgmii 10\n");
  436. mode = PHY_INTERFACE_MODE_RGMII;
  437. break;
  438. default:
  439. printf("%s: Ack,Speed(%d)is illegal\n",
  440. dev->name, mii_info->speed);
  441. break;
  442. }
  443. }
  444. /* change phy */
  445. change_phy_interface_mode(dev, mode, mii_info->speed);
  446. /* change the MAC interface mode */
  447. uec_set_mac_if_mode(uec, mode, mii_info->speed);
  448. printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
  449. uec->oldspeed = mii_info->speed;
  450. }
  451. if (!uec->oldlink) {
  452. printf("%s: Link is up\n", dev->name);
  453. uec->oldlink = 1;
  454. }
  455. } else { /* if (mii_info->link) */
  456. if (uec->oldlink) {
  457. printf("%s: Link is down\n", dev->name);
  458. uec->oldlink = 0;
  459. uec->oldspeed = 0;
  460. uec->oldduplex = -1;
  461. }
  462. }
  463. }
  464. static void phy_change(struct eth_device *dev)
  465. {
  466. struct uec_priv *uec = (struct uec_priv *)dev->priv;
  467. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  468. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  469. /* QE9 and QE12 need to be set for enabling QE MII management signals */
  470. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
  471. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  472. #endif
  473. /* Update the link, speed, duplex */
  474. uec->mii_info->phyinfo->read_status(uec->mii_info);
  475. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  476. /*
  477. * QE12 is muxed with LBCTL, it needs to be released for enabling
  478. * LBCTL signal for LBC usage.
  479. */
  480. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  481. #endif
  482. /* Adjust the interface according to speed */
  483. adjust_link(dev);
  484. }
  485. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  486. /*
  487. * Find a device index from the devlist by name
  488. *
  489. * Returns:
  490. * The index where the device is located, -1 on error
  491. */
  492. static int uec_miiphy_find_dev_by_name(const char *devname)
  493. {
  494. int i;
  495. for (i = 0; i < MAXCONTROLLERS; i++) {
  496. if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0)
  497. break;
  498. }
  499. /* If device cannot be found, returns -1 */
  500. if (i == MAXCONTROLLERS) {
  501. debug("%s: device %s not found in devlist\n", __func__,
  502. devname);
  503. i = -1;
  504. }
  505. return i;
  506. }
  507. /*
  508. * Read a MII PHY register.
  509. *
  510. * Returns:
  511. * 0 on success
  512. */
  513. static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  514. {
  515. unsigned short value = 0;
  516. int devindex = 0;
  517. if (!bus->name) {
  518. debug("%s: NULL pointer given\n", __func__);
  519. } else {
  520. devindex = uec_miiphy_find_dev_by_name(bus->name);
  521. if (devindex >= 0)
  522. value = uec_read_phy_reg(devlist[devindex], addr, reg);
  523. }
  524. return value;
  525. }
  526. /*
  527. * Write a MII PHY register.
  528. *
  529. * Returns:
  530. * 0 on success
  531. */
  532. static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  533. u16 value)
  534. {
  535. int devindex = 0;
  536. if (!bus->name) {
  537. debug("%s: NULL pointer given\n", __func__);
  538. } else {
  539. devindex = uec_miiphy_find_dev_by_name(bus->name);
  540. if (devindex >= 0)
  541. uec_write_phy_reg(devlist[devindex], addr, reg, value);
  542. }
  543. return 0;
  544. }
  545. #endif
  546. static int uec_set_mac_address(struct uec_priv *uec, u8 *mac_addr)
  547. {
  548. uec_t *uec_regs;
  549. u32 mac_addr1;
  550. u32 mac_addr2;
  551. if (!uec) {
  552. printf("%s: uec not initial\n", __func__);
  553. return -EINVAL;
  554. }
  555. uec_regs = uec->uec_regs;
  556. /*
  557. * if a station address of 0x12345678ABCD, perform a write to
  558. * MACSTNADDR1 of 0xCDAB7856,
  559. * MACSTNADDR2 of 0x34120000
  560. */
  561. mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) |
  562. (mac_addr[3] << 8) | (mac_addr[2]);
  563. out_be32(&uec_regs->macstnaddr1, mac_addr1);
  564. mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
  565. out_be32(&uec_regs->macstnaddr2, mac_addr2);
  566. return 0;
  567. }
  568. static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
  569. int *threads_num_ret)
  570. {
  571. int num_threads_numerica;
  572. switch (threads_num) {
  573. case UEC_NUM_OF_THREADS_1:
  574. num_threads_numerica = 1;
  575. break;
  576. case UEC_NUM_OF_THREADS_2:
  577. num_threads_numerica = 2;
  578. break;
  579. case UEC_NUM_OF_THREADS_4:
  580. num_threads_numerica = 4;
  581. break;
  582. case UEC_NUM_OF_THREADS_6:
  583. num_threads_numerica = 6;
  584. break;
  585. case UEC_NUM_OF_THREADS_8:
  586. num_threads_numerica = 8;
  587. break;
  588. default:
  589. printf("%s: Bad number of threads value.",
  590. __func__);
  591. return -EINVAL;
  592. }
  593. *threads_num_ret = num_threads_numerica;
  594. return 0;
  595. }
  596. static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
  597. {
  598. struct uec_inf *uec_info;
  599. u32 end_bd;
  600. u8 bmrx = 0;
  601. int i;
  602. uec_info = uec->uec_info;
  603. /* Alloc global Tx parameter RAM page */
  604. uec->tx_glbl_pram_offset =
  605. qe_muram_alloc(sizeof(struct uec_tx_global_pram),
  606. UEC_TX_GLOBAL_PRAM_ALIGNMENT);
  607. uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
  608. qe_muram_addr(uec->tx_glbl_pram_offset);
  609. /* Zero the global Tx prameter RAM */
  610. memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
  611. /* Init global Tx parameter RAM */
  612. /* TEMODER, RMON statistics disable, one Tx queue */
  613. out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
  614. /* SQPTR */
  615. uec->send_q_mem_reg_offset =
  616. qe_muram_alloc(sizeof(struct uec_send_queue_qd),
  617. UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
  618. uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
  619. qe_muram_addr(uec->send_q_mem_reg_offset);
  620. out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
  621. /* Setup the table with TxBDs ring */
  622. end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
  623. * SIZEOFBD;
  624. out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
  625. (u32)(uec->p_tx_bd_ring));
  626. out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
  627. end_bd);
  628. /* Scheduler Base Pointer, we have only one Tx queue, no need it */
  629. out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
  630. /* TxRMON Base Pointer, TxRMON disable, we don't need it */
  631. out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
  632. /* TSTATE, global snooping, big endian, the CSB bus selected */
  633. bmrx = BMR_INIT_VALUE;
  634. out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
  635. /* IPH_Offset */
  636. for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
  637. out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
  638. /* VTAG table */
  639. for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
  640. out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
  641. /* TQPTR */
  642. uec->thread_dat_tx_offset =
  643. qe_muram_alloc(num_threads_tx *
  644. sizeof(struct uec_thread_data_tx) +
  645. 32 * (num_threads_tx == 1),
  646. UEC_THREAD_DATA_ALIGNMENT);
  647. uec->p_thread_data_tx = (struct uec_thread_data_tx *)
  648. qe_muram_addr(uec->thread_dat_tx_offset);
  649. out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
  650. }
  651. static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
  652. {
  653. u8 bmrx = 0;
  654. int i;
  655. struct uec_82xx_add_filtering_pram *p_af_pram;
  656. /* Allocate global Rx parameter RAM page */
  657. uec->rx_glbl_pram_offset =
  658. qe_muram_alloc(sizeof(struct uec_rx_global_pram),
  659. UEC_RX_GLOBAL_PRAM_ALIGNMENT);
  660. uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
  661. qe_muram_addr(uec->rx_glbl_pram_offset);
  662. /* Zero Global Rx parameter RAM */
  663. memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
  664. /* Init global Rx parameter RAM */
  665. /*
  666. * REMODER, Extended feature mode disable, VLAN disable,
  667. * LossLess flow control disable, Receive firmware statisic disable,
  668. * Extended address parsing mode disable, One Rx queues,
  669. * Dynamic maximum/minimum frame length disable, IP checksum check
  670. * disable, IP address alignment disable
  671. */
  672. out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
  673. /* RQPTR */
  674. uec->thread_dat_rx_offset =
  675. qe_muram_alloc(num_threads_rx *
  676. sizeof(struct uec_thread_data_rx),
  677. UEC_THREAD_DATA_ALIGNMENT);
  678. uec->p_thread_data_rx = (struct uec_thread_data_rx *)
  679. qe_muram_addr(uec->thread_dat_rx_offset);
  680. out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
  681. /* Type_or_Len */
  682. out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
  683. /* RxRMON base pointer, we don't need it */
  684. out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
  685. /* IntCoalescingPTR, we don't need it, no interrupt */
  686. out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
  687. /* RSTATE, global snooping, big endian, the CSB bus selected */
  688. bmrx = BMR_INIT_VALUE;
  689. out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
  690. /* MRBLR */
  691. out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
  692. /* RBDQPTR */
  693. uec->rx_bd_qs_tbl_offset =
  694. qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
  695. sizeof(struct uec_rx_pref_bds),
  696. UEC_RX_BD_QUEUES_ALIGNMENT);
  697. uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
  698. qe_muram_addr(uec->rx_bd_qs_tbl_offset);
  699. /* Zero it */
  700. memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
  701. sizeof(struct uec_rx_pref_bds));
  702. out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
  703. out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
  704. (u32)uec->p_rx_bd_ring);
  705. /* MFLR */
  706. out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
  707. /* MINFLR */
  708. out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
  709. /* MAXD1 */
  710. out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
  711. /* MAXD2 */
  712. out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
  713. /* ECAM_PTR */
  714. out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
  715. /* L2QT */
  716. out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
  717. /* L3QT */
  718. for (i = 0; i < 8; i++)
  719. out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
  720. /* VLAN_TYPE */
  721. out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
  722. /* TCI */
  723. out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
  724. /* Clear PQ2 style address filtering hash table */
  725. p_af_pram = (struct uec_82xx_add_filtering_pram *)
  726. uec->p_rx_glbl_pram->addressfiltering;
  727. p_af_pram->iaddr_h = 0;
  728. p_af_pram->iaddr_l = 0;
  729. p_af_pram->gaddr_h = 0;
  730. p_af_pram->gaddr_l = 0;
  731. }
  732. static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
  733. int thread_tx, int thread_rx)
  734. {
  735. struct uec_init_cmd_pram *p_init_enet_param;
  736. u32 init_enet_param_offset;
  737. struct uec_inf *uec_info;
  738. struct ucc_fast_inf *uf_info;
  739. int i;
  740. int snum;
  741. u32 off;
  742. u32 entry_val;
  743. u32 command;
  744. u32 cecr_subblock;
  745. uec_info = uec->uec_info;
  746. uf_info = &uec_info->uf_info;
  747. /* Allocate init enet command parameter */
  748. uec->init_enet_param_offset =
  749. qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
  750. init_enet_param_offset = uec->init_enet_param_offset;
  751. uec->p_init_enet_param = (struct uec_init_cmd_pram *)
  752. qe_muram_addr(uec->init_enet_param_offset);
  753. /* Zero init enet command struct */
  754. memset((void *)uec->p_init_enet_param, 0,
  755. sizeof(struct uec_init_cmd_pram));
  756. /* Init the command struct */
  757. p_init_enet_param = uec->p_init_enet_param;
  758. p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
  759. p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
  760. p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
  761. p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
  762. p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
  763. p_init_enet_param->largestexternallookupkeysize = 0;
  764. p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
  765. << ENET_INIT_PARAM_RGF_SHIFT;
  766. p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
  767. << ENET_INIT_PARAM_TGF_SHIFT;
  768. /* Init Rx global parameter pointer */
  769. p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
  770. (u32)uec_info->risc_rx;
  771. /* Init Rx threads */
  772. for (i = 0; i < (thread_rx + 1); i++) {
  773. snum = qe_get_snum();
  774. if (snum < 0) {
  775. printf("%s can not get snum\n", __func__);
  776. return -ENOMEM;
  777. }
  778. if (i == 0) {
  779. off = 0;
  780. } else {
  781. off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
  782. UEC_THREAD_RX_PRAM_ALIGNMENT);
  783. }
  784. entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
  785. off | (u32)uec_info->risc_rx;
  786. p_init_enet_param->rxthread[i] = entry_val;
  787. }
  788. /* Init Tx global parameter pointer */
  789. p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
  790. (u32)uec_info->risc_tx;
  791. /* Init Tx threads */
  792. for (i = 0; i < thread_tx; i++) {
  793. snum = qe_get_snum();
  794. if (snum < 0) {
  795. printf("%s can not get snum\n", __func__);
  796. return -ENOMEM;
  797. }
  798. off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
  799. UEC_THREAD_TX_PRAM_ALIGNMENT);
  800. entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
  801. off | (u32)uec_info->risc_tx;
  802. p_init_enet_param->txthread[i] = entry_val;
  803. }
  804. __asm__ __volatile__("sync");
  805. /* Issue QE command */
  806. command = QE_INIT_TX_RX;
  807. cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
  808. qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
  809. init_enet_param_offset);
  810. return 0;
  811. }
  812. static int uec_startup(struct uec_priv *uec)
  813. {
  814. struct uec_inf *uec_info;
  815. struct ucc_fast_inf *uf_info;
  816. struct ucc_fast_priv *uccf;
  817. ucc_fast_t *uf_regs;
  818. uec_t *uec_regs;
  819. int num_threads_tx;
  820. int num_threads_rx;
  821. u32 utbipar;
  822. u32 length;
  823. u32 align;
  824. struct buffer_descriptor *bd;
  825. u8 *buf;
  826. int i;
  827. if (!uec || !uec->uec_info) {
  828. printf("%s: uec or uec_info not initial\n", __func__);
  829. return -EINVAL;
  830. }
  831. uec_info = uec->uec_info;
  832. uf_info = &uec_info->uf_info;
  833. /* Check if Rx BD ring len is illegal */
  834. if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
  835. (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
  836. printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
  837. __func__);
  838. return -EINVAL;
  839. }
  840. /* Check if Tx BD ring len is illegal */
  841. if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
  842. printf("%s: Tx BD ring length must not be smaller than 2.\n",
  843. __func__);
  844. return -EINVAL;
  845. }
  846. /* Check if MRBLR is illegal */
  847. if (MAX_RXBUF_LEN == 0 || MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT) {
  848. printf("%s: max rx buffer length must be mutliple of 128.\n",
  849. __func__);
  850. return -EINVAL;
  851. }
  852. /* Both Rx and Tx are stopped */
  853. uec->grace_stopped_rx = 1;
  854. uec->grace_stopped_tx = 1;
  855. /* Init UCC fast */
  856. if (ucc_fast_init(uf_info, &uccf)) {
  857. printf("%s: failed to init ucc fast\n", __func__);
  858. return -ENOMEM;
  859. }
  860. /* Save uccf */
  861. uec->uccf = uccf;
  862. /* Convert the Tx threads number */
  863. if (uec_convert_threads_num(uec_info->num_threads_tx,
  864. &num_threads_tx)) {
  865. return -EINVAL;
  866. }
  867. /* Convert the Rx threads number */
  868. if (uec_convert_threads_num(uec_info->num_threads_rx,
  869. &num_threads_rx)) {
  870. return -EINVAL;
  871. }
  872. uf_regs = uccf->uf_regs;
  873. /* UEC register is following UCC fast registers */
  874. uec_regs = (uec_t *)(&uf_regs->ucc_eth);
  875. /* Save the UEC register pointer to UEC private struct */
  876. uec->uec_regs = uec_regs;
  877. /* Init UPSMR, enable hardware statistics (UCC) */
  878. out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
  879. /* Init MACCFG1, flow control disable, disable Tx and Rx */
  880. out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
  881. /* Init MACCFG2, length check, MAC PAD and CRC enable */
  882. out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
  883. /* Setup MAC interface mode */
  884. uec_set_mac_if_mode(uec, uec_info->enet_interface_type,
  885. uec_info->speed);
  886. /* Setup MII management base */
  887. #ifndef CONFIG_eTSEC_MDIO_BUS
  888. uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
  889. #else
  890. uec->uec_mii_regs = (uec_mii_t *)CONFIG_MIIM_ADDRESS;
  891. #endif
  892. /* Setup MII master clock source */
  893. qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
  894. /* Setup UTBIPAR */
  895. utbipar = in_be32(&uec_regs->utbipar);
  896. utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
  897. /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
  898. * This frees up the remaining SMI addresses for use.
  899. */
  900. utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
  901. out_be32(&uec_regs->utbipar, utbipar);
  902. /* Configure the TBI for SGMII operation */
  903. if (uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII &&
  904. uec->uec_info->speed == SPEED_1000) {
  905. uec_write_phy_reg(uec->dev, uec_regs->utbipar,
  906. ENET_TBI_MII_ANA, TBIANA_SETTINGS);
  907. uec_write_phy_reg(uec->dev, uec_regs->utbipar,
  908. ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
  909. uec_write_phy_reg(uec->dev, uec_regs->utbipar,
  910. ENET_TBI_MII_CR, TBICR_SETTINGS);
  911. }
  912. /* Allocate Tx BDs */
  913. length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
  914. UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
  915. UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
  916. if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
  917. UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
  918. length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
  919. }
  920. align = UEC_TX_BD_RING_ALIGNMENT;
  921. uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
  922. if (uec->tx_bd_ring_offset != 0) {
  923. uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
  924. & ~(align - 1));
  925. }
  926. /* Zero all of Tx BDs */
  927. memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
  928. /* Allocate Rx BDs */
  929. length = uec_info->rx_bd_ring_len * SIZEOFBD;
  930. align = UEC_RX_BD_RING_ALIGNMENT;
  931. uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
  932. if (uec->rx_bd_ring_offset != 0) {
  933. uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
  934. & ~(align - 1));
  935. }
  936. /* Zero all of Rx BDs */
  937. memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
  938. /* Allocate Rx buffer */
  939. length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
  940. align = UEC_RX_DATA_BUF_ALIGNMENT;
  941. uec->rx_buf_offset = (u32)malloc(length + align);
  942. if (uec->rx_buf_offset != 0) {
  943. uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
  944. & ~(align - 1));
  945. }
  946. /* Zero all of the Rx buffer */
  947. memset((void *)(uec->rx_buf_offset), 0, length + align);
  948. /* Init TxBD ring */
  949. bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
  950. uec->tx_bd = bd;
  951. for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
  952. BD_DATA_CLEAR(bd);
  953. BD_STATUS_SET(bd, 0);
  954. BD_LENGTH_SET(bd, 0);
  955. bd++;
  956. }
  957. BD_STATUS_SET((--bd), TX_BD_WRAP);
  958. /* Init RxBD ring */
  959. bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
  960. uec->rx_bd = bd;
  961. buf = uec->p_rx_buf;
  962. for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
  963. BD_DATA_SET(bd, buf);
  964. BD_LENGTH_SET(bd, 0);
  965. BD_STATUS_SET(bd, RX_BD_EMPTY);
  966. buf += MAX_RXBUF_LEN;
  967. bd++;
  968. }
  969. BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
  970. /* Init global Tx parameter RAM */
  971. uec_init_tx_parameter(uec, num_threads_tx);
  972. /* Init global Rx parameter RAM */
  973. uec_init_rx_parameter(uec, num_threads_rx);
  974. /* Init ethernet Tx and Rx parameter command */
  975. if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
  976. num_threads_rx)) {
  977. printf("%s issue init enet cmd failed\n", __func__);
  978. return -ENOMEM;
  979. }
  980. return 0;
  981. }
  982. static int uec_init(struct eth_device *dev, struct bd_info *bd)
  983. {
  984. struct uec_priv *uec;
  985. int err, i;
  986. struct phy_info *curphy;
  987. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  988. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  989. #endif
  990. uec = (struct uec_priv *)dev->priv;
  991. if (!uec->the_first_run) {
  992. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  993. /*
  994. * QE9 and QE12 need to be set for enabling QE MII
  995. * management signals
  996. */
  997. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
  998. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  999. #endif
  1000. err = init_phy(dev);
  1001. if (err) {
  1002. printf("%s: Cannot initialize PHY, aborting.\n",
  1003. dev->name);
  1004. return err;
  1005. }
  1006. curphy = uec->mii_info->phyinfo;
  1007. if (curphy->config_aneg) {
  1008. err = curphy->config_aneg(uec->mii_info);
  1009. if (err) {
  1010. printf("%s: Can't negotiate PHY\n", dev->name);
  1011. return err;
  1012. }
  1013. }
  1014. /* Give PHYs up to 5 sec to report a link */
  1015. i = 50;
  1016. do {
  1017. err = curphy->read_status(uec->mii_info);
  1018. if (!(((i-- > 0) && !uec->mii_info->link) || err))
  1019. break;
  1020. mdelay(100);
  1021. } while (1);
  1022. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  1023. /* QE12 needs to be released for enabling LBCTL signal*/
  1024. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  1025. #endif
  1026. if (err || i <= 0)
  1027. printf("warning: %s: timeout on PHY link\n", dev->name);
  1028. adjust_link(dev);
  1029. uec->the_first_run = 1;
  1030. }
  1031. /* Set up the MAC address */
  1032. if (dev->enetaddr[0] & 0x01) {
  1033. printf("%s: MacAddress is multcast address\n",
  1034. __func__);
  1035. return -1;
  1036. }
  1037. uec_set_mac_address(uec, dev->enetaddr);
  1038. err = uec_open(uec, COMM_DIR_RX_AND_TX);
  1039. if (err) {
  1040. printf("%s: cannot enable UEC device\n", dev->name);
  1041. return -1;
  1042. }
  1043. phy_change(dev);
  1044. return uec->mii_info->link ? 0 : -1;
  1045. }
  1046. static void uec_halt(struct eth_device *dev)
  1047. {
  1048. struct uec_priv *uec = (struct uec_priv *)dev->priv;
  1049. uec_stop(uec, COMM_DIR_RX_AND_TX);
  1050. }
  1051. static int uec_send(struct eth_device *dev, void *buf, int len)
  1052. {
  1053. struct uec_priv *uec;
  1054. struct ucc_fast_priv *uccf;
  1055. struct buffer_descriptor *bd;
  1056. u16 status;
  1057. int i;
  1058. int result = 0;
  1059. uec = (struct uec_priv *)dev->priv;
  1060. uccf = uec->uccf;
  1061. bd = uec->tx_bd;
  1062. /* Find an empty TxBD */
  1063. for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
  1064. if (i > 0x100000) {
  1065. printf("%s: tx buffer not ready\n", dev->name);
  1066. return result;
  1067. }
  1068. }
  1069. /* Init TxBD */
  1070. BD_DATA_SET(bd, buf);
  1071. BD_LENGTH_SET(bd, len);
  1072. status = BD_STATUS(bd);
  1073. status &= BD_WRAP;
  1074. status |= (TX_BD_READY | TX_BD_LAST);
  1075. BD_STATUS_SET(bd, status);
  1076. /* Tell UCC to transmit the buffer */
  1077. ucc_fast_transmit_on_demand(uccf);
  1078. /* Wait for buffer to be transmitted */
  1079. for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
  1080. if (i > 0x100000) {
  1081. printf("%s: tx error\n", dev->name);
  1082. return result;
  1083. }
  1084. }
  1085. /* Ok, the buffer be transimitted */
  1086. BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
  1087. uec->tx_bd = bd;
  1088. result = 1;
  1089. return result;
  1090. }
  1091. static int uec_recv(struct eth_device *dev)
  1092. {
  1093. struct uec_priv *uec = dev->priv;
  1094. struct buffer_descriptor *bd;
  1095. u16 status;
  1096. u16 len;
  1097. u8 *data;
  1098. bd = uec->rx_bd;
  1099. status = BD_STATUS(bd);
  1100. while (!(status & RX_BD_EMPTY)) {
  1101. if (!(status & RX_BD_ERROR)) {
  1102. data = BD_DATA(bd);
  1103. len = BD_LENGTH(bd);
  1104. net_process_received_packet(data, len);
  1105. } else {
  1106. printf("%s: Rx error\n", dev->name);
  1107. }
  1108. status &= BD_CLEAN;
  1109. BD_LENGTH_SET(bd, 0);
  1110. BD_STATUS_SET(bd, status | RX_BD_EMPTY);
  1111. BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
  1112. status = BD_STATUS(bd);
  1113. }
  1114. uec->rx_bd = bd;
  1115. return 1;
  1116. }
  1117. int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info)
  1118. {
  1119. struct eth_device *dev;
  1120. int i;
  1121. struct uec_priv *uec;
  1122. int err;
  1123. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  1124. if (!dev)
  1125. return 0;
  1126. memset(dev, 0, sizeof(struct eth_device));
  1127. /* Allocate the UEC private struct */
  1128. uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
  1129. if (!uec)
  1130. return -ENOMEM;
  1131. memset(uec, 0, sizeof(struct uec_priv));
  1132. /* Adjust uec_info */
  1133. #if (MAX_QE_RISC == 4)
  1134. uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
  1135. uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
  1136. #endif
  1137. devlist[uec_info->uf_info.ucc_num] = dev;
  1138. uec->uec_info = uec_info;
  1139. uec->dev = dev;
  1140. sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
  1141. dev->iobase = 0;
  1142. dev->priv = (void *)uec;
  1143. dev->init = uec_init;
  1144. dev->halt = uec_halt;
  1145. dev->send = uec_send;
  1146. dev->recv = uec_recv;
  1147. /* Clear the ethnet address */
  1148. for (i = 0; i < 6; i++)
  1149. dev->enetaddr[i] = 0;
  1150. eth_register(dev);
  1151. err = uec_startup(uec);
  1152. if (err) {
  1153. printf("%s: Cannot configure net device, aborting.", dev->name);
  1154. return err;
  1155. }
  1156. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  1157. int retval;
  1158. struct mii_dev *mdiodev = mdio_alloc();
  1159. if (!mdiodev)
  1160. return -ENOMEM;
  1161. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  1162. mdiodev->read = uec_miiphy_read;
  1163. mdiodev->write = uec_miiphy_write;
  1164. retval = mdio_register(mdiodev);
  1165. if (retval < 0)
  1166. return retval;
  1167. #endif
  1168. return 1;
  1169. }
  1170. int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num)
  1171. {
  1172. int i;
  1173. for (i = 0; i < num; i++)
  1174. uec_initialize(bis, &uecs[i]);
  1175. return 0;
  1176. }
  1177. int uec_standard_init(struct bd_info *bis)
  1178. {
  1179. return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
  1180. }
  1181. #endif