uccf.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <linux/errno.h>
  11. #include <asm/io.h>
  12. #include <linux/immap_qe.h>
  13. #include "uccf.h"
  14. #include <fsl_qe.h>
  15. #if !defined(CONFIG_DM_ETH)
  16. void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
  17. {
  18. out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
  19. }
  20. u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
  21. {
  22. switch (ucc_num) {
  23. case 0:
  24. return QE_CR_SUBBLOCK_UCCFAST1;
  25. case 1:
  26. return QE_CR_SUBBLOCK_UCCFAST2;
  27. case 2:
  28. return QE_CR_SUBBLOCK_UCCFAST3;
  29. case 3:
  30. return QE_CR_SUBBLOCK_UCCFAST4;
  31. case 4:
  32. return QE_CR_SUBBLOCK_UCCFAST5;
  33. case 5:
  34. return QE_CR_SUBBLOCK_UCCFAST6;
  35. case 6:
  36. return QE_CR_SUBBLOCK_UCCFAST7;
  37. case 7:
  38. return QE_CR_SUBBLOCK_UCCFAST8;
  39. default:
  40. return QE_CR_SUBBLOCK_INVALID;
  41. }
  42. }
  43. static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
  44. u8 *reg_num, u8 *shift)
  45. {
  46. switch (ucc_num) {
  47. case 0: /* UCC1 */
  48. *p_cmxucr = &qe_immr->qmx.cmxucr1;
  49. *reg_num = 1;
  50. *shift = 16;
  51. break;
  52. case 2: /* UCC3 */
  53. *p_cmxucr = &qe_immr->qmx.cmxucr1;
  54. *reg_num = 1;
  55. *shift = 0;
  56. break;
  57. case 4: /* UCC5 */
  58. *p_cmxucr = &qe_immr->qmx.cmxucr2;
  59. *reg_num = 2;
  60. *shift = 16;
  61. break;
  62. case 6: /* UCC7 */
  63. *p_cmxucr = &qe_immr->qmx.cmxucr2;
  64. *reg_num = 2;
  65. *shift = 0;
  66. break;
  67. case 1: /* UCC2 */
  68. *p_cmxucr = &qe_immr->qmx.cmxucr3;
  69. *reg_num = 3;
  70. *shift = 16;
  71. break;
  72. case 3: /* UCC4 */
  73. *p_cmxucr = &qe_immr->qmx.cmxucr3;
  74. *reg_num = 3;
  75. *shift = 0;
  76. break;
  77. case 5: /* UCC6 */
  78. *p_cmxucr = &qe_immr->qmx.cmxucr4;
  79. *reg_num = 4;
  80. *shift = 16;
  81. break;
  82. case 7: /* UCC8 */
  83. *p_cmxucr = &qe_immr->qmx.cmxucr4;
  84. *reg_num = 4;
  85. *shift = 0;
  86. break;
  87. default:
  88. break;
  89. }
  90. }
  91. static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
  92. {
  93. u32 *p_cmxucr = NULL;
  94. u8 reg_num = 0;
  95. u8 shift = 0;
  96. u32 clk_bits;
  97. u32 clk_mask;
  98. int source = -1;
  99. /* check if the UCC number is in range. */
  100. if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
  101. return -EINVAL;
  102. if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
  103. printf("%s: bad comm mode type passed\n", __func__);
  104. return -EINVAL;
  105. }
  106. ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
  107. switch (reg_num) {
  108. case 1:
  109. switch (clock) {
  110. case QE_BRG1:
  111. source = 1;
  112. break;
  113. case QE_BRG2:
  114. source = 2;
  115. break;
  116. case QE_BRG7:
  117. source = 3;
  118. break;
  119. case QE_BRG8:
  120. source = 4;
  121. break;
  122. case QE_CLK9:
  123. source = 5;
  124. break;
  125. case QE_CLK10:
  126. source = 6;
  127. break;
  128. case QE_CLK11:
  129. source = 7;
  130. break;
  131. case QE_CLK12:
  132. source = 8;
  133. break;
  134. case QE_CLK15:
  135. source = 9;
  136. break;
  137. case QE_CLK16:
  138. source = 10;
  139. break;
  140. default:
  141. source = -1;
  142. break;
  143. }
  144. break;
  145. case 2:
  146. switch (clock) {
  147. case QE_BRG5:
  148. source = 1;
  149. break;
  150. case QE_BRG6:
  151. source = 2;
  152. break;
  153. case QE_BRG7:
  154. source = 3;
  155. break;
  156. case QE_BRG8:
  157. source = 4;
  158. break;
  159. case QE_CLK13:
  160. source = 5;
  161. break;
  162. case QE_CLK14:
  163. source = 6;
  164. break;
  165. case QE_CLK19:
  166. source = 7;
  167. break;
  168. case QE_CLK20:
  169. source = 8;
  170. break;
  171. case QE_CLK15:
  172. source = 9;
  173. break;
  174. case QE_CLK16:
  175. source = 10;
  176. break;
  177. default:
  178. source = -1;
  179. break;
  180. }
  181. break;
  182. case 3:
  183. switch (clock) {
  184. case QE_BRG9:
  185. source = 1;
  186. break;
  187. case QE_BRG10:
  188. source = 2;
  189. break;
  190. case QE_BRG15:
  191. source = 3;
  192. break;
  193. case QE_BRG16:
  194. source = 4;
  195. break;
  196. case QE_CLK3:
  197. source = 5;
  198. break;
  199. case QE_CLK4:
  200. source = 6;
  201. break;
  202. case QE_CLK17:
  203. source = 7;
  204. break;
  205. case QE_CLK18:
  206. source = 8;
  207. break;
  208. case QE_CLK7:
  209. source = 9;
  210. break;
  211. case QE_CLK8:
  212. source = 10;
  213. break;
  214. case QE_CLK16:
  215. source = 11;
  216. break;
  217. default:
  218. source = -1;
  219. break;
  220. }
  221. break;
  222. case 4:
  223. switch (clock) {
  224. case QE_BRG13:
  225. source = 1;
  226. break;
  227. case QE_BRG14:
  228. source = 2;
  229. break;
  230. case QE_BRG15:
  231. source = 3;
  232. break;
  233. case QE_BRG16:
  234. source = 4;
  235. break;
  236. case QE_CLK5:
  237. source = 5;
  238. break;
  239. case QE_CLK6:
  240. source = 6;
  241. break;
  242. case QE_CLK21:
  243. source = 7;
  244. break;
  245. case QE_CLK22:
  246. source = 8;
  247. break;
  248. case QE_CLK7:
  249. source = 9;
  250. break;
  251. case QE_CLK8:
  252. source = 10;
  253. break;
  254. case QE_CLK16:
  255. source = 11;
  256. break;
  257. default:
  258. source = -1;
  259. break;
  260. }
  261. break;
  262. default:
  263. source = -1;
  264. break;
  265. }
  266. if (source == -1) {
  267. printf("%s: Bad combination of clock and UCC\n", __func__);
  268. return -ENOENT;
  269. }
  270. clk_bits = (u32)source;
  271. clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
  272. if (mode == COMM_DIR_RX) {
  273. clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
  274. clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
  275. }
  276. clk_bits <<= shift;
  277. clk_mask <<= shift;
  278. out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
  279. return 0;
  280. }
  281. static uint ucc_get_reg_baseaddr(int ucc_num)
  282. {
  283. uint base = 0;
  284. /* check if the UCC number is in range */
  285. if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
  286. printf("%s: the UCC num not in ranges\n", __func__);
  287. return 0;
  288. }
  289. switch (ucc_num) {
  290. case 0:
  291. base = 0x00002000;
  292. break;
  293. case 1:
  294. base = 0x00003000;
  295. break;
  296. case 2:
  297. base = 0x00002200;
  298. break;
  299. case 3:
  300. base = 0x00003200;
  301. break;
  302. case 4:
  303. base = 0x00002400;
  304. break;
  305. case 5:
  306. base = 0x00003400;
  307. break;
  308. case 6:
  309. base = 0x00002600;
  310. break;
  311. case 7:
  312. base = 0x00003600;
  313. break;
  314. default:
  315. break;
  316. }
  317. base = (uint)qe_immr + base;
  318. return base;
  319. }
  320. void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
  321. {
  322. ucc_fast_t *uf_regs;
  323. u32 gumr;
  324. uf_regs = uccf->uf_regs;
  325. /* Enable reception and/or transmission on this UCC. */
  326. gumr = in_be32(&uf_regs->gumr);
  327. if (mode & COMM_DIR_TX) {
  328. gumr |= UCC_FAST_GUMR_ENT;
  329. uccf->enabled_tx = 1;
  330. }
  331. if (mode & COMM_DIR_RX) {
  332. gumr |= UCC_FAST_GUMR_ENR;
  333. uccf->enabled_rx = 1;
  334. }
  335. out_be32(&uf_regs->gumr, gumr);
  336. }
  337. void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
  338. {
  339. ucc_fast_t *uf_regs;
  340. u32 gumr;
  341. uf_regs = uccf->uf_regs;
  342. /* Disable reception and/or transmission on this UCC. */
  343. gumr = in_be32(&uf_regs->gumr);
  344. if (mode & COMM_DIR_TX) {
  345. gumr &= ~UCC_FAST_GUMR_ENT;
  346. uccf->enabled_tx = 0;
  347. }
  348. if (mode & COMM_DIR_RX) {
  349. gumr &= ~UCC_FAST_GUMR_ENR;
  350. uccf->enabled_rx = 0;
  351. }
  352. out_be32(&uf_regs->gumr, gumr);
  353. }
  354. int ucc_fast_init(struct ucc_fast_inf *uf_info,
  355. struct ucc_fast_priv **uccf_ret)
  356. {
  357. struct ucc_fast_priv *uccf;
  358. ucc_fast_t *uf_regs;
  359. if (!uf_info)
  360. return -EINVAL;
  361. if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
  362. printf("%s: Illagal UCC number!\n", __func__);
  363. return -EINVAL;
  364. }
  365. uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
  366. if (!uccf) {
  367. printf("%s: No memory for UCC fast data structure!\n",
  368. __func__);
  369. return -ENOMEM;
  370. }
  371. memset(uccf, 0, sizeof(struct ucc_fast_priv));
  372. /* Save fast UCC structure */
  373. uccf->uf_info = uf_info;
  374. uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
  375. if (!uccf->uf_regs) {
  376. printf("%s: No memory map for UCC fast controller!\n",
  377. __func__);
  378. return -ENOMEM;
  379. }
  380. uccf->enabled_tx = 0;
  381. uccf->enabled_rx = 0;
  382. uf_regs = uccf->uf_regs;
  383. uccf->p_ucce = (u32 *)&uf_regs->ucce;
  384. uccf->p_uccm = (u32 *)&uf_regs->uccm;
  385. /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
  386. out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
  387. | UCC_GUEMR_MODE_FAST_TX);
  388. /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
  389. out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
  390. /* Set the Giga ethernet VFIFO stuff */
  391. if (uf_info->eth_type == GIGA_ETH) {
  392. /* Allocate memory for Tx Virtual Fifo */
  393. uccf->ucc_fast_tx_virtual_fifo_base_offset =
  394. qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
  395. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  396. /* Allocate memory for Rx Virtual Fifo */
  397. uccf->ucc_fast_rx_virtual_fifo_base_offset =
  398. qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
  399. UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
  400. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  401. /* utfb, urfb are offsets from MURAM base */
  402. out_be32(&uf_regs->utfb,
  403. uccf->ucc_fast_tx_virtual_fifo_base_offset);
  404. out_be32(&uf_regs->urfb,
  405. uccf->ucc_fast_rx_virtual_fifo_base_offset);
  406. /* Set Virtual Fifo registers */
  407. out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
  408. out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
  409. out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
  410. out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
  411. out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
  412. out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
  413. }
  414. /* Set the Fast ethernet VFIFO stuff */
  415. if (uf_info->eth_type == FAST_ETH) {
  416. /* Allocate memory for Tx Virtual Fifo */
  417. uccf->ucc_fast_tx_virtual_fifo_base_offset =
  418. qe_muram_alloc(UCC_GETH_UTFS_INIT,
  419. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  420. /* Allocate memory for Rx Virtual Fifo */
  421. uccf->ucc_fast_rx_virtual_fifo_base_offset =
  422. qe_muram_alloc(UCC_GETH_URFS_INIT +
  423. UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
  424. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  425. /* utfb, urfb are offsets from MURAM base */
  426. out_be32(&uf_regs->utfb,
  427. uccf->ucc_fast_tx_virtual_fifo_base_offset);
  428. out_be32(&uf_regs->urfb,
  429. uccf->ucc_fast_rx_virtual_fifo_base_offset);
  430. /* Set Virtual Fifo registers */
  431. out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
  432. out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
  433. out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
  434. out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
  435. out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
  436. out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
  437. }
  438. /* Rx clock routing */
  439. if (uf_info->rx_clock != QE_CLK_NONE) {
  440. if (ucc_set_clk_src(uf_info->ucc_num,
  441. uf_info->rx_clock, COMM_DIR_RX)) {
  442. printf("%s: Illegal value for parameter 'RxClock'.\n",
  443. __func__);
  444. return -EINVAL;
  445. }
  446. }
  447. /* Tx clock routing */
  448. if (uf_info->tx_clock != QE_CLK_NONE) {
  449. if (ucc_set_clk_src(uf_info->ucc_num,
  450. uf_info->tx_clock, COMM_DIR_TX)) {
  451. printf("%s: Illegal value for parameter 'TxClock'.\n",
  452. __func__);
  453. return -EINVAL;
  454. }
  455. }
  456. /* Clear interrupt mask register to disable all of interrupts */
  457. out_be32(&uf_regs->uccm, 0x0);
  458. /* Writing '1' to clear all of envents */
  459. out_be32(&uf_regs->ucce, 0xffffffff);
  460. *uccf_ret = uccf;
  461. return 0;
  462. }
  463. #endif