rk_pwm.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <pwm.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-rockchip/pwm.h>
  17. #include <linux/bitops.h>
  18. #include <power/regulator.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. struct rockchip_pwm_data {
  21. struct rockchip_pwm_regs regs;
  22. unsigned int prescaler;
  23. bool supports_polarity;
  24. bool supports_lock;
  25. u32 enable_conf;
  26. u32 enable_conf_mask;
  27. };
  28. struct rk_pwm_priv {
  29. fdt_addr_t base;
  30. ulong freq;
  31. u32 conf_polarity;
  32. const struct rockchip_pwm_data *data;
  33. };
  34. static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
  35. {
  36. struct rk_pwm_priv *priv = dev_get_priv(dev);
  37. if (!priv->data->supports_polarity) {
  38. debug("%s: Do not support polarity\n", __func__);
  39. return 0;
  40. }
  41. debug("%s: polarity=%u\n", __func__, polarity);
  42. if (polarity)
  43. priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
  44. else
  45. priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  46. return 0;
  47. }
  48. static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  49. uint duty_ns)
  50. {
  51. struct rk_pwm_priv *priv = dev_get_priv(dev);
  52. const struct rockchip_pwm_regs *regs = &priv->data->regs;
  53. unsigned long period, duty;
  54. u32 ctrl;
  55. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  56. ctrl = readl(priv->base + regs->ctrl);
  57. /*
  58. * Lock the period and duty of previous configuration, then
  59. * change the duty and period, that would not be effective.
  60. */
  61. if (priv->data->supports_lock) {
  62. ctrl |= PWM_LOCK;
  63. writel(ctrl, priv->base + regs->ctrl);
  64. }
  65. period = lldiv((uint64_t)priv->freq * period_ns,
  66. priv->data->prescaler * 1000000000);
  67. duty = lldiv((uint64_t)priv->freq * duty_ns,
  68. priv->data->prescaler * 1000000000);
  69. writel(period, priv->base + regs->period);
  70. writel(duty, priv->base + regs->duty);
  71. if (priv->data->supports_polarity) {
  72. ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
  73. ctrl |= priv->conf_polarity;
  74. }
  75. /*
  76. * Unlock and set polarity at the same time,
  77. * the configuration of duty, period and polarity
  78. * would be effective together at next period.
  79. */
  80. if (priv->data->supports_lock)
  81. ctrl &= ~PWM_LOCK;
  82. writel(ctrl, priv->base + regs->ctrl);
  83. debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  84. return 0;
  85. }
  86. static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  87. {
  88. struct rk_pwm_priv *priv = dev_get_priv(dev);
  89. const struct rockchip_pwm_regs *regs = &priv->data->regs;
  90. u32 ctrl;
  91. debug("%s: Enable '%s'\n", __func__, dev->name);
  92. ctrl = readl(priv->base + regs->ctrl);
  93. ctrl &= ~priv->data->enable_conf_mask;
  94. if (enable)
  95. ctrl |= priv->data->enable_conf;
  96. else
  97. ctrl &= ~priv->data->enable_conf;
  98. writel(ctrl, priv->base + regs->ctrl);
  99. return 0;
  100. }
  101. static int rk_pwm_of_to_plat(struct udevice *dev)
  102. {
  103. struct rk_pwm_priv *priv = dev_get_priv(dev);
  104. priv->base = dev_read_addr(dev);
  105. return 0;
  106. }
  107. static int rk_pwm_probe(struct udevice *dev)
  108. {
  109. struct rk_pwm_priv *priv = dev_get_priv(dev);
  110. struct clk clk;
  111. int ret = 0;
  112. ret = clk_get_by_index(dev, 0, &clk);
  113. if (ret < 0) {
  114. debug("%s get clock fail!\n", __func__);
  115. return -EINVAL;
  116. }
  117. priv->freq = clk_get_rate(&clk);
  118. priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
  119. if (priv->data->supports_polarity)
  120. priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  121. return 0;
  122. }
  123. static const struct pwm_ops rk_pwm_ops = {
  124. .set_invert = rk_pwm_set_invert,
  125. .set_config = rk_pwm_set_config,
  126. .set_enable = rk_pwm_set_enable,
  127. };
  128. static const struct rockchip_pwm_data pwm_data_v1 = {
  129. .regs = {
  130. .duty = 0x04,
  131. .period = 0x08,
  132. .cntr = 0x00,
  133. .ctrl = 0x0c,
  134. },
  135. .prescaler = 2,
  136. .supports_polarity = false,
  137. .supports_lock = false,
  138. .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
  139. .enable_conf_mask = BIT(1) | BIT(3),
  140. };
  141. static const struct rockchip_pwm_data pwm_data_v2 = {
  142. .regs = {
  143. .duty = 0x08,
  144. .period = 0x04,
  145. .cntr = 0x00,
  146. .ctrl = 0x0c,
  147. },
  148. .prescaler = 1,
  149. .supports_polarity = true,
  150. .supports_lock = false,
  151. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
  152. PWM_CONTINUOUS,
  153. .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
  154. };
  155. static const struct rockchip_pwm_data pwm_data_v3 = {
  156. .regs = {
  157. .duty = 0x08,
  158. .period = 0x04,
  159. .cntr = 0x00,
  160. .ctrl = 0x0c,
  161. },
  162. .prescaler = 1,
  163. .supports_polarity = true,
  164. .supports_lock = true,
  165. .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
  166. PWM_CONTINUOUS,
  167. .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
  168. };
  169. static const struct udevice_id rk_pwm_ids[] = {
  170. { .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
  171. { .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
  172. { .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
  173. { }
  174. };
  175. U_BOOT_DRIVER(rk_pwm) = {
  176. .name = "rk_pwm",
  177. .id = UCLASS_PWM,
  178. .of_match = rk_pwm_ids,
  179. .ops = &rk_pwm_ops,
  180. .of_to_plat = rk_pwm_of_to_plat,
  181. .probe = rk_pwm_probe,
  182. .priv_auto = sizeof(struct rk_pwm_priv),
  183. };