pwm-ti-ehrpwm.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * EHRPWM PWM driver
  4. *
  5. * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
  6. *
  7. * Based on Linux kernel drivers/pwm/pwm-tiehrpwm.c
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <div64.h>
  12. #include <dm.h>
  13. #include <dm/device_compat.h>
  14. #include <pwm.h>
  15. #include <asm/io.h>
  16. #define NSEC_PER_SEC 1000000000L
  17. /* Time base module registers */
  18. #define TI_EHRPWM_TBCTL 0x00
  19. #define TI_EHRPWM_TBPRD 0x0A
  20. #define TI_EHRPWM_TBCTL_PRDLD_MASK BIT(3)
  21. #define TI_EHRPWM_TBCTL_PRDLD_SHDW 0
  22. #define TI_EHRPWM_TBCTL_PRDLD_IMDT BIT(3)
  23. #define TI_EHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 7)
  24. #define TI_EHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0)
  25. #define TI_EHRPWM_TBCTL_CTRMODE_UP 0
  26. #define TI_EHRPWM_TBCTL_CTRMODE_DOWN BIT(0)
  27. #define TI_EHRPWM_TBCTL_CTRMODE_UPDOWN BIT(1)
  28. #define TI_EHRPWM_TBCTL_CTRMODE_FREEZE GENMASK(1, 0)
  29. #define TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT 7
  30. #define TI_EHRPWM_TBCTL_CLKDIV_SHIFT 10
  31. #define TI_EHRPWM_CLKDIV_MAX 7
  32. #define TI_EHRPWM_HSPCLKDIV_MAX 7
  33. #define TI_EHRPWM_PERIOD_MAX 0xFFFF
  34. /* Counter compare module registers */
  35. #define TI_EHRPWM_CMPA 0x12
  36. #define TI_EHRPWM_CMPB 0x14
  37. /* Action qualifier module registers */
  38. #define TI_EHRPWM_AQCTLA 0x16
  39. #define TI_EHRPWM_AQCTLB 0x18
  40. #define TI_EHRPWM_AQSFRC 0x1A
  41. #define TI_EHRPWM_AQCSFRC 0x1C
  42. #define TI_EHRPWM_AQCTL_CBU_MASK GENMASK(9, 8)
  43. #define TI_EHRPWM_AQCTL_CBU_FRCLOW BIT(8)
  44. #define TI_EHRPWM_AQCTL_CBU_FRCHIGH BIT(9)
  45. #define TI_EHRPWM_AQCTL_CBU_FRCTOGGLE GENMASK(9, 8)
  46. #define TI_EHRPWM_AQCTL_CAU_MASK GENMASK(5, 4)
  47. #define TI_EHRPWM_AQCTL_CAU_FRCLOW BIT(4)
  48. #define TI_EHRPWM_AQCTL_CAU_FRCHIGH BIT(5)
  49. #define TI_EHRPWM_AQCTL_CAU_FRCTOGGLE GENMASK(5, 4)
  50. #define TI_EHRPWM_AQCTL_PRD_MASK GENMASK(3, 2)
  51. #define TI_EHRPWM_AQCTL_PRD_FRCLOW BIT(2)
  52. #define TI_EHRPWM_AQCTL_PRD_FRCHIGH BIT(3)
  53. #define TI_EHRPWM_AQCTL_PRD_FRCTOGGLE GENMASK(3, 2)
  54. #define TI_EHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0)
  55. #define TI_EHRPWM_AQCTL_ZRO_FRCLOW BIT(0)
  56. #define TI_EHRPWM_AQCTL_ZRO_FRCHIGH BIT(1)
  57. #define TI_EHRPWM_AQCTL_ZRO_FRCTOGGLE GENMASK(1, 0)
  58. #define TI_EHRPWM_AQCTL_CHANA_POLNORMAL (TI_EHRPWM_AQCTL_CAU_FRCLOW | \
  59. TI_EHRPWM_AQCTL_PRD_FRCHIGH | \
  60. TI_EHRPWM_AQCTL_ZRO_FRCHIGH)
  61. #define TI_EHRPWM_AQCTL_CHANA_POLINVERSED (TI_EHRPWM_AQCTL_CAU_FRCHIGH | \
  62. TI_EHRPWM_AQCTL_PRD_FRCLOW | \
  63. TI_EHRPWM_AQCTL_ZRO_FRCLOW)
  64. #define TI_EHRPWM_AQCTL_CHANB_POLNORMAL (TI_EHRPWM_AQCTL_CBU_FRCLOW | \
  65. TI_EHRPWM_AQCTL_PRD_FRCHIGH | \
  66. TI_EHRPWM_AQCTL_ZRO_FRCHIGH)
  67. #define TI_EHRPWM_AQCTL_CHANB_POLINVERSED (TI_EHRPWM_AQCTL_CBU_FRCHIGH | \
  68. TI_EHRPWM_AQCTL_PRD_FRCLOW | \
  69. TI_EHRPWM_AQCTL_ZRO_FRCLOW)
  70. #define TI_EHRPWM_AQSFRC_RLDCSF_MASK GENMASK(7, 6)
  71. #define TI_EHRPWM_AQSFRC_RLDCSF_ZRO 0
  72. #define TI_EHRPWM_AQSFRC_RLDCSF_PRD BIT(6)
  73. #define TI_EHRPWM_AQSFRC_RLDCSF_ZROPRD BIT(7)
  74. #define TI_EHRPWM_AQSFRC_RLDCSF_IMDT GENMASK(7, 6)
  75. #define TI_EHRPWM_AQCSFRC_CSFB_MASK GENMASK(3, 2)
  76. #define TI_EHRPWM_AQCSFRC_CSFB_FRCDIS 0
  77. #define TI_EHRPWM_AQCSFRC_CSFB_FRCLOW BIT(2)
  78. #define TI_EHRPWM_AQCSFRC_CSFB_FRCHIGH BIT(3)
  79. #define TI_EHRPWM_AQCSFRC_CSFB_DISSWFRC GENMASK(3, 2)
  80. #define TI_EHRPWM_AQCSFRC_CSFA_MASK GENMASK(1, 0)
  81. #define TI_EHRPWM_AQCSFRC_CSFA_FRCDIS 0
  82. #define TI_EHRPWM_AQCSFRC_CSFA_FRCLOW BIT(0)
  83. #define TI_EHRPWM_AQCSFRC_CSFA_FRCHIGH BIT(1)
  84. #define TI_EHRPWM_AQCSFRC_CSFA_DISSWFRC GENMASK(1, 0)
  85. #define TI_EHRPWM_NUM_CHANNELS 2
  86. struct ti_ehrpwm_priv {
  87. fdt_addr_t regs;
  88. u32 clk_rate;
  89. struct clk tbclk;
  90. unsigned long period_cycles[TI_EHRPWM_NUM_CHANNELS];
  91. bool polarity_reversed[TI_EHRPWM_NUM_CHANNELS];
  92. };
  93. static void ti_ehrpwm_modify(u16 val, u16 mask, fdt_addr_t reg)
  94. {
  95. unsigned short v;
  96. v = readw(reg);
  97. v &= ~mask;
  98. v |= val & mask;
  99. writew(v, reg);
  100. }
  101. static int ti_ehrpwm_set_invert(struct udevice *dev, uint channel,
  102. bool polarity)
  103. {
  104. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  105. if (channel >= TI_EHRPWM_NUM_CHANNELS)
  106. return -ENOSPC;
  107. /* Configuration of polarity in hardware delayed, do at enable */
  108. priv->polarity_reversed[channel] = polarity;
  109. return 0;
  110. }
  111. /**
  112. * set_prescale_div - Set up the prescaler divider function
  113. * @rqst_prescaler: prescaler value min
  114. * @prescale_div: prescaler value set
  115. * @tb_clk_div: Time Base Control prescaler bits
  116. */
  117. static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
  118. u16 *tb_clk_div)
  119. {
  120. unsigned int clkdiv, hspclkdiv;
  121. for (clkdiv = 0; clkdiv <= TI_EHRPWM_CLKDIV_MAX; clkdiv++) {
  122. for (hspclkdiv = 0; hspclkdiv <= TI_EHRPWM_HSPCLKDIV_MAX;
  123. hspclkdiv++) {
  124. /*
  125. * calculations for prescaler value :
  126. * prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
  127. * HSPCLKDIVIDER = 2 ** hspclkdiv
  128. * CLKDIVIDER = (1), if clkdiv == 0 *OR*
  129. * (2 * clkdiv), if clkdiv != 0
  130. *
  131. * Configure prescale_div value such that period
  132. * register value is less than 65535.
  133. */
  134. *prescale_div = (1 << clkdiv) *
  135. (hspclkdiv ? (hspclkdiv * 2) : 1);
  136. if (*prescale_div > rqst_prescaler) {
  137. *tb_clk_div =
  138. (clkdiv << TI_EHRPWM_TBCTL_CLKDIV_SHIFT) |
  139. (hspclkdiv <<
  140. TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT);
  141. return 0;
  142. }
  143. }
  144. }
  145. return 1;
  146. }
  147. static void ti_ehrpwm_configure_polarity(struct udevice *dev, uint channel)
  148. {
  149. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  150. u16 aqctl_val, aqctl_mask;
  151. unsigned int aqctl_reg;
  152. /*
  153. * Configure PWM output to HIGH/LOW level on counter
  154. * reaches compare register value and LOW/HIGH level
  155. * on counter value reaches period register value and
  156. * zero value on counter
  157. */
  158. if (channel == 1) {
  159. aqctl_reg = TI_EHRPWM_AQCTLB;
  160. aqctl_mask = TI_EHRPWM_AQCTL_CBU_MASK;
  161. if (priv->polarity_reversed[channel])
  162. aqctl_val = TI_EHRPWM_AQCTL_CHANB_POLINVERSED;
  163. else
  164. aqctl_val = TI_EHRPWM_AQCTL_CHANB_POLNORMAL;
  165. } else {
  166. aqctl_reg = TI_EHRPWM_AQCTLA;
  167. aqctl_mask = TI_EHRPWM_AQCTL_CAU_MASK;
  168. if (priv->polarity_reversed[channel])
  169. aqctl_val = TI_EHRPWM_AQCTL_CHANA_POLINVERSED;
  170. else
  171. aqctl_val = TI_EHRPWM_AQCTL_CHANA_POLNORMAL;
  172. }
  173. aqctl_mask |= TI_EHRPWM_AQCTL_PRD_MASK | TI_EHRPWM_AQCTL_ZRO_MASK;
  174. ti_ehrpwm_modify(aqctl_val, aqctl_mask, priv->regs + aqctl_reg);
  175. }
  176. /*
  177. * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
  178. * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
  179. */
  180. static int ti_ehrpwm_set_config(struct udevice *dev, uint channel,
  181. uint period_ns, uint duty_ns)
  182. {
  183. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  184. u32 period_cycles, duty_cycles;
  185. u16 ps_divval, tb_divval;
  186. unsigned int i, cmp_reg;
  187. unsigned long long c;
  188. if (channel >= TI_EHRPWM_NUM_CHANNELS)
  189. return -ENOSPC;
  190. if (period_ns > NSEC_PER_SEC)
  191. return -ERANGE;
  192. c = priv->clk_rate;
  193. c = c * period_ns;
  194. do_div(c, NSEC_PER_SEC);
  195. period_cycles = (unsigned long)c;
  196. if (period_cycles < 1) {
  197. period_cycles = 1;
  198. duty_cycles = 1;
  199. } else {
  200. c = priv->clk_rate;
  201. c = c * duty_ns;
  202. do_div(c, NSEC_PER_SEC);
  203. duty_cycles = (unsigned long)c;
  204. }
  205. dev_dbg(dev, "channel=%d, period_ns=%d, duty_ns=%d\n",
  206. channel, period_ns, duty_ns);
  207. /*
  208. * Period values should be same for multiple PWM channels as IP uses
  209. * same period register for multiple channels.
  210. */
  211. for (i = 0; i < TI_EHRPWM_NUM_CHANNELS; i++) {
  212. if (priv->period_cycles[i] &&
  213. priv->period_cycles[i] != period_cycles) {
  214. /*
  215. * Allow channel to reconfigure period if no other
  216. * channels being configured.
  217. */
  218. if (i == channel)
  219. continue;
  220. dev_err(dev, "period value conflicts with channel %u\n",
  221. i);
  222. return -EINVAL;
  223. }
  224. }
  225. priv->period_cycles[channel] = period_cycles;
  226. /* Configure clock prescaler to support Low frequency PWM wave */
  227. if (set_prescale_div(period_cycles / TI_EHRPWM_PERIOD_MAX, &ps_divval,
  228. &tb_divval)) {
  229. dev_err(dev, "unsupported values\n");
  230. return -EINVAL;
  231. }
  232. /* Update clock prescaler values */
  233. ti_ehrpwm_modify(tb_divval, TI_EHRPWM_TBCTL_CLKDIV_MASK,
  234. priv->regs + TI_EHRPWM_TBCTL);
  235. /* Update period & duty cycle with presacler division */
  236. period_cycles = period_cycles / ps_divval;
  237. duty_cycles = duty_cycles / ps_divval;
  238. /* Configure shadow loading on Period register */
  239. ti_ehrpwm_modify(TI_EHRPWM_TBCTL_PRDLD_SHDW, TI_EHRPWM_TBCTL_PRDLD_MASK,
  240. priv->regs + TI_EHRPWM_TBCTL);
  241. writew(period_cycles, priv->regs + TI_EHRPWM_TBPRD);
  242. /* Configure ehrpwm counter for up-count mode */
  243. ti_ehrpwm_modify(TI_EHRPWM_TBCTL_CTRMODE_UP,
  244. TI_EHRPWM_TBCTL_CTRMODE_MASK,
  245. priv->regs + TI_EHRPWM_TBCTL);
  246. if (channel == 1)
  247. /* Channel 1 configured with compare B register */
  248. cmp_reg = TI_EHRPWM_CMPB;
  249. else
  250. /* Channel 0 configured with compare A register */
  251. cmp_reg = TI_EHRPWM_CMPA;
  252. writew(duty_cycles, priv->regs + cmp_reg);
  253. return 0;
  254. }
  255. static int ti_ehrpwm_disable(struct udevice *dev, uint channel)
  256. {
  257. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  258. u16 aqcsfrc_val, aqcsfrc_mask;
  259. int err;
  260. if (channel >= TI_EHRPWM_NUM_CHANNELS)
  261. return -ENOSPC;
  262. /* Action Qualifier puts PWM output low forcefully */
  263. if (channel) {
  264. aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFB_FRCLOW;
  265. aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFB_MASK;
  266. } else {
  267. aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFA_FRCLOW;
  268. aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFA_MASK;
  269. }
  270. /* Update shadow register first before modifying active register */
  271. ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_ZRO,
  272. TI_EHRPWM_AQSFRC_RLDCSF_MASK,
  273. priv->regs + TI_EHRPWM_AQSFRC);
  274. ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask,
  275. priv->regs + TI_EHRPWM_AQCSFRC);
  276. /*
  277. * Changes to immediate action on Action Qualifier. This puts
  278. * Action Qualifier control on PWM output from next TBCLK
  279. */
  280. ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_IMDT,
  281. TI_EHRPWM_AQSFRC_RLDCSF_MASK,
  282. priv->regs + TI_EHRPWM_AQSFRC);
  283. ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask,
  284. priv->regs + TI_EHRPWM_AQCSFRC);
  285. /* Disabling TBCLK on PWM disable */
  286. err = clk_disable(&priv->tbclk);
  287. if (err) {
  288. dev_err(dev, "failed to disable tbclk\n");
  289. return err;
  290. }
  291. return 0;
  292. }
  293. static int ti_ehrpwm_enable(struct udevice *dev, uint channel)
  294. {
  295. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  296. u16 aqcsfrc_val, aqcsfrc_mask;
  297. int err;
  298. if (channel >= TI_EHRPWM_NUM_CHANNELS)
  299. return -ENOSPC;
  300. /* Disabling Action Qualifier on PWM output */
  301. if (channel) {
  302. aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFB_FRCDIS;
  303. aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFB_MASK;
  304. } else {
  305. aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFA_FRCDIS;
  306. aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFA_MASK;
  307. }
  308. /* Changes to shadow mode */
  309. ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_ZRO,
  310. TI_EHRPWM_AQSFRC_RLDCSF_MASK,
  311. priv->regs + TI_EHRPWM_AQSFRC);
  312. ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask,
  313. priv->regs + TI_EHRPWM_AQCSFRC);
  314. /* Channels polarity can be configured from action qualifier module */
  315. ti_ehrpwm_configure_polarity(dev, channel);
  316. err = clk_enable(&priv->tbclk);
  317. if (err) {
  318. dev_err(dev, "failed to enable tbclk\n");
  319. return err;
  320. }
  321. return 0;
  322. }
  323. static int ti_ehrpwm_set_enable(struct udevice *dev, uint channel, bool enable)
  324. {
  325. if (enable)
  326. return ti_ehrpwm_enable(dev, channel);
  327. return ti_ehrpwm_disable(dev, channel);
  328. }
  329. static int ti_ehrpwm_of_to_plat(struct udevice *dev)
  330. {
  331. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  332. priv->regs = dev_read_addr(dev);
  333. if (priv->regs == FDT_ADDR_T_NONE) {
  334. dev_err(dev, "invalid address\n");
  335. return -EINVAL;
  336. }
  337. dev_dbg(dev, "regs=0x%08lx\n", priv->regs);
  338. return 0;
  339. }
  340. static int ti_ehrpwm_remove(struct udevice *dev)
  341. {
  342. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  343. clk_release_all(&priv->tbclk, 1);
  344. return 0;
  345. }
  346. static int ti_ehrpwm_probe(struct udevice *dev)
  347. {
  348. struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
  349. struct clk clk;
  350. int err;
  351. err = clk_get_by_name(dev, "fck", &clk);
  352. if (err) {
  353. dev_err(dev, "failed to get clock\n");
  354. return err;
  355. }
  356. priv->clk_rate = clk_get_rate(&clk);
  357. if (IS_ERR_VALUE(priv->clk_rate) || !priv->clk_rate) {
  358. dev_err(dev, "failed to get clock rate\n");
  359. if (IS_ERR_VALUE(priv->clk_rate))
  360. return priv->clk_rate;
  361. return -EINVAL;
  362. }
  363. /* Acquire tbclk for Time Base EHRPWM submodule */
  364. err = clk_get_by_name(dev, "tbclk", &priv->tbclk);
  365. if (err) {
  366. dev_err(dev, "failed to get tbclk clock\n");
  367. return err;
  368. }
  369. return 0;
  370. }
  371. static const struct pwm_ops ti_ehrpwm_ops = {
  372. .set_config = ti_ehrpwm_set_config,
  373. .set_enable = ti_ehrpwm_set_enable,
  374. .set_invert = ti_ehrpwm_set_invert,
  375. };
  376. static const struct udevice_id ti_ehrpwm_ids[] = {
  377. {.compatible = "ti,am3352-ehrpwm"},
  378. {.compatible = "ti,am33xx-ehrpwm"},
  379. {}
  380. };
  381. U_BOOT_DRIVER(ti_ehrpwm) = {
  382. .name = "ti_ehrpwm",
  383. .id = UCLASS_PWM,
  384. .of_match = ti_ehrpwm_ids,
  385. .ops = &ti_ehrpwm_ops,
  386. .of_to_plat = ti_ehrpwm_of_to_plat,
  387. .probe = ti_ehrpwm_probe,
  388. .remove = ti_ehrpwm_remove,
  389. .priv_auto = sizeof(struct ti_ehrpwm_priv),
  390. };