pwm-sifive.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 SiFive, Inc
  4. * For SiFive's PWM IP block documentation please refer Chapter 14 of
  5. * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  6. *
  7. * Limitations:
  8. * - When changing both duty cycle and period, we cannot prevent in
  9. * software that the output might produce a period with mixed
  10. * settings (new period length and old duty cycle).
  11. * - The hardware cannot generate a 100% duty cycle.
  12. * - The hardware generates only inverted output.
  13. */
  14. #include <common.h>
  15. #include <clk.h>
  16. #include <div64.h>
  17. #include <dm.h>
  18. #include <pwm.h>
  19. #include <regmap.h>
  20. #include <asm/global_data.h>
  21. #include <linux/io.h>
  22. #include <linux/log2.h>
  23. #include <linux/bitfield.h>
  24. /* PWMCFG fields */
  25. #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
  26. #define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
  27. #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
  28. #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
  29. #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
  30. #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
  31. #define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
  32. #define PWM_SIFIVE_PWMCFG_GANG BIT(24)
  33. #define PWM_SIFIVE_PWMCFG_IP BIT(28)
  34. /* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
  35. #define PWM_SIFIVE_SIZE_PWMCMP 4
  36. #define PWM_SIFIVE_CMPWIDTH 16
  37. #define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0
  38. #define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff
  39. DECLARE_GLOBAL_DATA_PTR;
  40. struct pwm_sifive_regs {
  41. unsigned long cfg;
  42. unsigned long cnt;
  43. unsigned long pwms;
  44. unsigned long cmp0;
  45. };
  46. struct pwm_sifive_data {
  47. struct pwm_sifive_regs regs;
  48. };
  49. struct pwm_sifive_priv {
  50. void __iomem *base;
  51. ulong freq;
  52. const struct pwm_sifive_data *data;
  53. };
  54. static int pwm_sifive_set_config(struct udevice *dev, uint channel,
  55. uint period_ns, uint duty_ns)
  56. {
  57. struct pwm_sifive_priv *priv = dev_get_priv(dev);
  58. const struct pwm_sifive_regs *regs = &priv->data->regs;
  59. unsigned long scale_pow;
  60. unsigned long long num;
  61. u32 scale, val = 0, frac;
  62. debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  63. /*
  64. * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
  65. * period length is using pwmscale which provides the number of bits the
  66. * counter is shifted before being feed to the comparators. A period
  67. * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
  68. * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
  69. */
  70. scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000);
  71. scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
  72. val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS);
  73. /*
  74. * The problem of output producing mixed setting as mentioned at top,
  75. * occurs here. To minimize the window for this problem, we are
  76. * calculating the register values first and then writing them
  77. * consecutively
  78. */
  79. num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
  80. frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
  81. frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
  82. frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
  83. writel(val, priv->base + regs->cfg);
  84. writel(frac, priv->base + regs->cmp0 + channel *
  85. PWM_SIFIVE_SIZE_PWMCMP);
  86. return 0;
  87. }
  88. static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable)
  89. {
  90. struct pwm_sifive_priv *priv = dev_get_priv(dev);
  91. const struct pwm_sifive_regs *regs = &priv->data->regs;
  92. debug("%s: Enable '%s'\n", __func__, dev->name);
  93. if (enable)
  94. writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
  95. regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
  96. else
  97. writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
  98. regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
  99. return 0;
  100. }
  101. static int pwm_sifive_of_to_plat(struct udevice *dev)
  102. {
  103. struct pwm_sifive_priv *priv = dev_get_priv(dev);
  104. priv->base = dev_read_addr_ptr(dev);
  105. return 0;
  106. }
  107. static int pwm_sifive_probe(struct udevice *dev)
  108. {
  109. struct pwm_sifive_priv *priv = dev_get_priv(dev);
  110. struct clk clk;
  111. int ret = 0;
  112. ret = clk_get_by_index(dev, 0, &clk);
  113. if (ret < 0) {
  114. debug("%s get clock fail!\n", __func__);
  115. return -EINVAL;
  116. }
  117. priv->freq = clk_get_rate(&clk);
  118. priv->data = (struct pwm_sifive_data *)dev_get_driver_data(dev);
  119. return 0;
  120. }
  121. static const struct pwm_ops pwm_sifive_ops = {
  122. .set_config = pwm_sifive_set_config,
  123. .set_enable = pwm_sifive_set_enable,
  124. };
  125. static const struct pwm_sifive_data pwm_data = {
  126. .regs = {
  127. .cfg = 0x00,
  128. .cnt = 0x08,
  129. .pwms = 0x10,
  130. .cmp0 = 0x20,
  131. },
  132. };
  133. static const struct udevice_id pwm_sifive_ids[] = {
  134. { .compatible = "sifive,pwm0", .data = (ulong)&pwm_data},
  135. { }
  136. };
  137. U_BOOT_DRIVER(pwm_sifive) = {
  138. .name = "pwm_sifive",
  139. .id = UCLASS_PWM,
  140. .of_match = pwm_sifive_ids,
  141. .ops = &pwm_sifive_ops,
  142. .of_to_plat = pwm_sifive_of_to_plat,
  143. .probe = pwm_sifive_probe,
  144. .priv_auto = sizeof(struct pwm_sifive_priv),
  145. };