pwm-meson.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2020 BayLibre, SAS.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2014 Amlogic, Inc.
  6. *
  7. * This PWM is only a set of Gates, Dividers and Counters:
  8. * PWM output is achieved by calculating a clock that permits calculating
  9. * two periods (low and high). The counter then has to be set to switch after
  10. * N cycles for the first half period.
  11. * The hardware has no "polarity" setting. This driver reverses the period
  12. * cycles (the low length is inverted with the high length) for
  13. * PWM_POLARITY_INVERSED.
  14. * Setting the polarity will disable and re-enable the PWM output.
  15. * Disabling the PWM stops the output immediately (without waiting for the
  16. * current period to complete first).
  17. */
  18. #include <common.h>
  19. #include <clk.h>
  20. #include <div64.h>
  21. #include <dm.h>
  22. #include <pwm.h>
  23. #include <regmap.h>
  24. #include <linux/io.h>
  25. #include <linux/math64.h>
  26. #include <linux/bitfield.h>
  27. #include <linux/clk-provider.h>
  28. #define NSEC_PER_SEC 1000000000L
  29. #define REG_PWM_A 0x0
  30. #define REG_PWM_B 0x4
  31. #define PWM_LOW_MASK GENMASK(15, 0)
  32. #define PWM_HIGH_MASK GENMASK(31, 16)
  33. #define REG_MISC_AB 0x8
  34. #define MISC_B_CLK_EN BIT(23)
  35. #define MISC_A_CLK_EN BIT(15)
  36. #define MISC_CLK_DIV_MASK 0x7f
  37. #define MISC_B_CLK_DIV_SHIFT 16
  38. #define MISC_A_CLK_DIV_SHIFT 8
  39. #define MISC_B_CLK_SEL_SHIFT 6
  40. #define MISC_A_CLK_SEL_SHIFT 4
  41. #define MISC_CLK_SEL_MASK 0x3
  42. #define MISC_B_EN BIT(1)
  43. #define MISC_A_EN BIT(0)
  44. #define MESON_NUM_PWMS 2
  45. static struct meson_pwm_channel_data {
  46. u8 reg_offset;
  47. u8 clk_sel_shift;
  48. u8 clk_div_shift;
  49. u32 clk_en_mask;
  50. u32 pwm_en_mask;
  51. } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
  52. {
  53. .reg_offset = REG_PWM_A,
  54. .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
  55. .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
  56. .clk_en_mask = MISC_A_CLK_EN,
  57. .pwm_en_mask = MISC_A_EN,
  58. },
  59. {
  60. .reg_offset = REG_PWM_B,
  61. .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
  62. .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
  63. .clk_en_mask = MISC_B_CLK_EN,
  64. .pwm_en_mask = MISC_B_EN,
  65. }
  66. };
  67. struct meson_pwm_channel {
  68. unsigned int hi;
  69. unsigned int lo;
  70. u8 pre_div;
  71. uint period_ns;
  72. uint duty_ns;
  73. bool configured;
  74. bool enabled;
  75. bool polarity;
  76. struct clk clk;
  77. };
  78. struct meson_pwm_data {
  79. const long *parent_ids;
  80. unsigned int num_parents;
  81. };
  82. struct meson_pwm {
  83. const struct meson_pwm_data *data;
  84. struct meson_pwm_channel channels[MESON_NUM_PWMS];
  85. void __iomem *base;
  86. };
  87. static int meson_pwm_set_enable(struct udevice *dev, uint channel, bool enable);
  88. static int meson_pwm_set_config(struct udevice *dev, uint channeln,
  89. uint period_ns, uint duty_ns)
  90. {
  91. struct meson_pwm *priv = dev_get_priv(dev);
  92. struct meson_pwm_channel *channel;
  93. struct meson_pwm_channel_data *channel_data;
  94. unsigned int duty, period, pre_div, cnt, duty_cnt;
  95. unsigned long fin_freq;
  96. if (channeln >= MESON_NUM_PWMS)
  97. return -ENODEV;
  98. channel = &priv->channels[channeln];
  99. channel_data = &meson_pwm_per_channel_data[channeln];
  100. period = period_ns;
  101. if (channel->polarity)
  102. duty = period_ns - duty_ns;
  103. else
  104. duty = duty_ns;
  105. debug("%s%d: polarity %s duty %d period %d\n", __func__, channeln,
  106. channel->polarity ? "true" : "false", duty, period);
  107. fin_freq = clk_get_rate(&channel->clk);
  108. if (fin_freq == 0) {
  109. printf("%s%d: invalid source clock frequency\n", __func__, channeln);
  110. return -EINVAL;
  111. }
  112. debug("%s%d: fin_freq: %lu Hz\n", __func__, channeln, fin_freq);
  113. pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
  114. if (pre_div > MISC_CLK_DIV_MASK) {
  115. printf("%s%d: unable to get period pre_div\n", __func__, channeln);
  116. return -EINVAL;
  117. }
  118. cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
  119. if (cnt > 0xffff) {
  120. printf("%s%d: unable to get period cnt\n", __func__, channeln);
  121. return -EINVAL;
  122. }
  123. debug("%s%d: period=%u pre_div=%u cnt=%u\n", __func__, channeln, period, pre_div, cnt);
  124. if (duty == period) {
  125. channel->pre_div = pre_div;
  126. channel->hi = cnt;
  127. channel->lo = 0;
  128. } else if (duty == 0) {
  129. channel->pre_div = pre_div;
  130. channel->hi = 0;
  131. channel->lo = cnt;
  132. } else {
  133. /* Then check is we can have the duty with the same pre_div */
  134. duty_cnt = div64_u64(fin_freq * (u64)duty, NSEC_PER_SEC * (pre_div + 1));
  135. if (duty_cnt > 0xffff) {
  136. printf("%s%d: unable to get duty cycle\n", __func__, channeln);
  137. return -EINVAL;
  138. }
  139. debug("%s%d: duty=%u pre_div=%u duty_cnt=%u\n",
  140. __func__, channeln, duty, pre_div, duty_cnt);
  141. channel->pre_div = pre_div;
  142. channel->hi = duty_cnt;
  143. channel->lo = cnt - duty_cnt;
  144. }
  145. channel->period_ns = period_ns;
  146. channel->duty_ns = duty_ns;
  147. channel->configured = true;
  148. if (channel->enabled) {
  149. meson_pwm_set_enable(dev, channeln, false);
  150. meson_pwm_set_enable(dev, channeln, true);
  151. }
  152. return 0;
  153. }
  154. static int meson_pwm_set_enable(struct udevice *dev, uint channeln, bool enable)
  155. {
  156. struct meson_pwm *priv = dev_get_priv(dev);
  157. struct meson_pwm_channel *channel;
  158. struct meson_pwm_channel_data *channel_data;
  159. u32 value;
  160. if (channeln >= MESON_NUM_PWMS)
  161. return -ENODEV;
  162. channel = &priv->channels[channeln];
  163. channel_data = &meson_pwm_per_channel_data[channeln];
  164. if (!channel->configured)
  165. return -EINVAL;
  166. if (enable) {
  167. if (channel->enabled)
  168. return 0;
  169. value = readl(priv->base + REG_MISC_AB);
  170. value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
  171. value |= channel->pre_div << channel_data->clk_div_shift;
  172. value |= channel_data->clk_en_mask;
  173. writel(value, priv->base + REG_MISC_AB);
  174. value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
  175. FIELD_PREP(PWM_LOW_MASK, channel->lo);
  176. writel(value, priv->base + channel_data->reg_offset);
  177. value = readl(priv->base + REG_MISC_AB);
  178. value |= channel_data->pwm_en_mask;
  179. writel(value, priv->base + REG_MISC_AB);
  180. debug("%s%d: enabled\n", __func__, channeln);
  181. channel->enabled = true;
  182. } else {
  183. if (!channel->enabled)
  184. return 0;
  185. value = readl(priv->base + REG_MISC_AB);
  186. value &= channel_data->pwm_en_mask;
  187. writel(value, priv->base + REG_MISC_AB);
  188. debug("%s%d: disabled\n", __func__, channeln);
  189. channel->enabled = false;
  190. }
  191. return 0;
  192. }
  193. static int meson_pwm_set_invert(struct udevice *dev, uint channeln, bool polarity)
  194. {
  195. struct meson_pwm *priv = dev_get_priv(dev);
  196. struct meson_pwm_channel *channel;
  197. if (channeln >= MESON_NUM_PWMS)
  198. return -ENODEV;
  199. debug("%s%d: set invert %s\n", __func__, channeln, polarity ? "true" : "false");
  200. channel = &priv->channels[channeln];
  201. channel->polarity = polarity;
  202. if (!channel->configured)
  203. return 0;
  204. return meson_pwm_set_config(dev, channeln, channel->period_ns, channel->duty_ns);
  205. }
  206. static int meson_pwm_of_to_plat(struct udevice *dev)
  207. {
  208. struct meson_pwm *priv = dev_get_priv(dev);
  209. priv->base = dev_read_addr_ptr(dev);
  210. return 0;
  211. }
  212. static int meson_pwm_probe(struct udevice *dev)
  213. {
  214. struct meson_pwm *priv = dev_get_priv(dev);
  215. struct meson_pwm_data *data;
  216. unsigned int i, p;
  217. char name[255];
  218. int err;
  219. u32 reg;
  220. data = (struct meson_pwm_data *)dev_get_driver_data(dev);
  221. if (!data)
  222. return -EINVAL;
  223. for (i = 0; i < MESON_NUM_PWMS; i++) {
  224. struct meson_pwm_channel *channel = &priv->channels[i];
  225. struct meson_pwm_channel_data *channel_data = &meson_pwm_per_channel_data[i];
  226. snprintf(name, sizeof(name), "clkin%u", i);
  227. err = clk_get_by_name(dev, name, &channel->clk);
  228. /* If clock is not specified, use the already set clock */
  229. if (err == -ENODATA) {
  230. struct udevice *cdev;
  231. struct uclass *uc;
  232. /* Get parent from mux */
  233. p = (readl(priv->base + REG_MISC_AB) >> channel_data->clk_sel_shift) &
  234. MISC_CLK_SEL_MASK;
  235. if (p >= data->num_parents) {
  236. printf("%s%d: hw parent is invalid\n", __func__, i);
  237. return -EINVAL;
  238. }
  239. if (data->parent_ids[p] == -1) {
  240. /* Search for xtal clk */
  241. const char *str;
  242. err = uclass_get(UCLASS_CLK, &uc);
  243. if (err)
  244. return err;
  245. uclass_foreach_dev(cdev, uc) {
  246. if (strcmp(cdev->driver->name, "fixed_rate_clock"))
  247. continue;
  248. str = ofnode_read_string(dev_ofnode(cdev),
  249. "clock-output-names");
  250. if (!str)
  251. continue;
  252. if (!strcmp(str, "xtal")) {
  253. err = uclass_get_device_by_ofnode(UCLASS_CLK,
  254. dev_ofnode(cdev),
  255. &cdev);
  256. if (err) {
  257. printf("%s%d: Failed to get xtal clk\n", __func__, i);
  258. return err;
  259. }
  260. break;
  261. }
  262. }
  263. if (!cdev) {
  264. printf("%s%d: Failed to find xtal clk device\n", __func__, i);
  265. return -EINVAL;
  266. }
  267. channel->clk.dev = cdev;
  268. channel->clk.id = 0;
  269. channel->clk.data = 0;
  270. } else {
  271. /* Look for parent clock */
  272. err = uclass_get(UCLASS_CLK, &uc);
  273. if (err)
  274. return err;
  275. uclass_foreach_dev(cdev, uc) {
  276. if (strstr(cdev->driver->name, "meson_clk"))
  277. break;
  278. }
  279. if (!cdev) {
  280. printf("%s%d: Failed to find clk device\n", __func__, i);
  281. return -EINVAL;
  282. }
  283. err = uclass_get_device_by_ofnode(UCLASS_CLK,
  284. dev_ofnode(cdev),
  285. &cdev);
  286. if (err) {
  287. printf("%s%d: Failed to get clk controller\n", __func__, i);
  288. return err;
  289. }
  290. channel->clk.dev = cdev;
  291. channel->clk.id = data->parent_ids[p];
  292. channel->clk.data = 0;
  293. }
  294. /* We have our source clock, do not alter HW clock mux */
  295. continue;
  296. } else
  297. return err;
  298. /* Get id in list */
  299. for (p = 0 ; p < data->num_parents ; ++p) {
  300. if (!strcmp(channel->clk.dev->driver->name, "fixed_rate_clock")) {
  301. if (data->parent_ids[p] == -1)
  302. break;
  303. } else {
  304. if (data->parent_ids[p] == channel->clk.id)
  305. break;
  306. }
  307. }
  308. /* Invalid clock ID */
  309. if (p == data->num_parents) {
  310. printf("%s%d: source clock is invalid\n", __func__, i);
  311. return -EINVAL;
  312. }
  313. /* switch parent in mux */
  314. reg = readl(priv->base + REG_MISC_AB);
  315. debug("%s%d: switching parent %d to %d\n", __func__, i,
  316. (reg >> channel_data->clk_sel_shift) & MISC_CLK_SEL_MASK, p);
  317. reg &= MISC_CLK_SEL_MASK << channel_data->clk_sel_shift;
  318. reg |= (p & MISC_CLK_SEL_MASK) << channel_data->clk_sel_shift;
  319. writel(reg, priv->base + REG_MISC_AB);
  320. }
  321. return 0;
  322. }
  323. static const struct pwm_ops meson_pwm_ops = {
  324. .set_config = meson_pwm_set_config,
  325. .set_enable = meson_pwm_set_enable,
  326. .set_invert = meson_pwm_set_invert,
  327. };
  328. #define XTAL -1
  329. /* Local clock ids aliases to avoid define conflicts */
  330. #define GXBB_CLKID_HDMI_PLL 2
  331. #define GXBB_CLKID_FCLK_DIV3 5
  332. #define GXBB_CLKID_FCLK_DIV4 6
  333. #define GXBB_CLKID_CLK81 12
  334. static const long pwm_gxbb_parent_ids[] = {
  335. XTAL, GXBB_CLKID_HDMI_PLL, GXBB_CLKID_FCLK_DIV4, GXBB_CLKID_FCLK_DIV3
  336. };
  337. static const struct meson_pwm_data pwm_gxbb_data = {
  338. .parent_ids = pwm_gxbb_parent_ids,
  339. .num_parents = ARRAY_SIZE(pwm_gxbb_parent_ids),
  340. };
  341. /*
  342. * Only the 2 first inputs of the GXBB AO PWMs are valid
  343. * The last 2 are grounded
  344. */
  345. static const long pwm_gxbb_ao_parent_ids[] = {
  346. XTAL, GXBB_CLKID_CLK81
  347. };
  348. static const struct meson_pwm_data pwm_gxbb_ao_data = {
  349. .parent_ids = pwm_gxbb_ao_parent_ids,
  350. .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_ids),
  351. };
  352. /* Local clock ids aliases to avoid define conflicts */
  353. #define AXG_CLKID_FCLK_DIV3 3
  354. #define AXG_CLKID_FCLK_DIV4 4
  355. #define AXG_CLKID_FCLK_DIV5 5
  356. #define AXG_CLKID_CLK81 10
  357. static const long pwm_axg_ee_parent_ids[] = {
  358. XTAL, AXG_CLKID_FCLK_DIV5, AXG_CLKID_FCLK_DIV4, AXG_CLKID_FCLK_DIV3
  359. };
  360. static const struct meson_pwm_data pwm_axg_ee_data = {
  361. .parent_ids = pwm_axg_ee_parent_ids,
  362. .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_ids),
  363. };
  364. static const long pwm_axg_ao_parent_ids[] = {
  365. AXG_CLKID_CLK81, XTAL, AXG_CLKID_FCLK_DIV4, AXG_CLKID_FCLK_DIV5
  366. };
  367. static const struct meson_pwm_data pwm_axg_ao_data = {
  368. .parent_ids = pwm_axg_ao_parent_ids,
  369. .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_ids),
  370. };
  371. /* Local clock ids aliases to avoid define conflicts */
  372. #define G12A_CLKID_FCLK_DIV3 3
  373. #define G12A_CLKID_FCLK_DIV4 4
  374. #define G12A_CLKID_FCLK_DIV5 5
  375. #define G12A_CLKID_CLK81 10
  376. #define G12A_CLKID_HDMI_PLL 128
  377. static const long pwm_g12a_ao_ab_parent_ids[] = {
  378. XTAL, G12A_CLKID_CLK81, G12A_CLKID_FCLK_DIV4, G12A_CLKID_FCLK_DIV5
  379. };
  380. static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
  381. .parent_ids = pwm_g12a_ao_ab_parent_ids,
  382. .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_ids),
  383. };
  384. static const long pwm_g12a_ao_cd_parent_ids[] = {
  385. XTAL, G12A_CLKID_CLK81,
  386. };
  387. static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
  388. .parent_ids = pwm_g12a_ao_cd_parent_ids,
  389. .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_ids),
  390. };
  391. static const long pwm_g12a_ee_parent_ids[] = {
  392. XTAL, G12A_CLKID_HDMI_PLL, G12A_CLKID_FCLK_DIV4, G12A_CLKID_FCLK_DIV3
  393. };
  394. static const struct meson_pwm_data pwm_g12a_ee_data = {
  395. .parent_ids = pwm_g12a_ee_parent_ids,
  396. .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_ids),
  397. };
  398. static const struct udevice_id meson_pwm_ids[] = {
  399. {
  400. .compatible = "amlogic,meson-gxbb-pwm",
  401. .data = (ulong)&pwm_gxbb_data
  402. },
  403. {
  404. .compatible = "amlogic,meson-gxbb-ao-pwm",
  405. .data = (ulong)&pwm_gxbb_ao_data
  406. },
  407. {
  408. .compatible = "amlogic,meson-axg-ee-pwm",
  409. .data = (ulong)&pwm_axg_ee_data
  410. },
  411. {
  412. .compatible = "amlogic,meson-axg-ao-pwm",
  413. .data = (ulong)&pwm_axg_ao_data
  414. },
  415. {
  416. .compatible = "amlogic,meson-g12a-ee-pwm",
  417. .data = (ulong)&pwm_g12a_ee_data
  418. },
  419. {
  420. .compatible = "amlogic,meson-g12a-ao-pwm-ab",
  421. .data = (ulong)&pwm_g12a_ao_ab_data
  422. },
  423. {
  424. .compatible = "amlogic,meson-g12a-ao-pwm-cd",
  425. .data = (ulong)&pwm_g12a_ao_cd_data
  426. },
  427. };
  428. U_BOOT_DRIVER(meson_pwm) = {
  429. .name = "meson_pwm",
  430. .id = UCLASS_PWM,
  431. .of_match = meson_pwm_ids,
  432. .ops = &meson_pwm_ops,
  433. .of_to_plat = meson_pwm_of_to_plat,
  434. .probe = meson_pwm_probe,
  435. .priv_auto = sizeof(struct meson_pwm),
  436. };